schizo.c revision 220038
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005 - 2011 by Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 220038 2011-03-26 16:49:12Z marius $"); 36 37/* 38 * Driver for `Schizo' Fireplane/Safari to PCI 2.1, `Tomatillo' JBus to 39 * PCI 2.2 and `XMITS' Fireplane/Safari to PCI-X bridges 40 */ 41 42#include "opt_ofw_pci.h" 43#include "opt_schizo.h" 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48#include <sys/kernel.h> 49#include <sys/lock.h> 50#include <sys/malloc.h> 51#include <sys/module.h> 52#include <sys/mutex.h> 53#include <sys/pcpu.h> 54#include <sys/rman.h> 55#include <sys/sysctl.h> 56#include <sys/time.h> 57#include <sys/timetc.h> 58 59#include <dev/ofw/ofw_bus.h> 60#include <dev/ofw/ofw_pci.h> 61#include <dev/ofw/openfirm.h> 62 63#include <machine/bus.h> 64#include <machine/bus_common.h> 65#include <machine/bus_private.h> 66#include <machine/fsr.h> 67#include <machine/iommureg.h> 68#include <machine/iommuvar.h> 69#include <machine/resource.h> 70 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <sparc64/pci/ofw_pci.h> 75#include <sparc64/pci/schizoreg.h> 76#include <sparc64/pci/schizovar.h> 77 78#include "pcib_if.h" 79 80static const struct schizo_desc *schizo_get_desc(device_t); 81static void schizo_set_intr(struct schizo_softc *, u_int, u_int, 82 driver_filter_t); 83static void schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 84 bus_dmasync_op_t op); 85static void ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 86 bus_dmasync_op_t op); 87static void schizo_intr_enable(void *); 88static void schizo_intr_disable(void *); 89static void schizo_intr_assign(void *); 90static void schizo_intr_clear(void *); 91static int schizo_intr_register(struct schizo_softc *sc, u_int ino); 92static int schizo_get_intrmap(struct schizo_softc *, u_int, 93 bus_addr_t *, bus_addr_t *); 94static bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int); 95static timecounter_get_t schizo_get_timecount; 96 97/* Interrupt handlers */ 98static driver_filter_t schizo_pci_bus; 99static driver_filter_t schizo_ue; 100static driver_filter_t schizo_ce; 101static driver_filter_t schizo_host_bus; 102static driver_filter_t schizo_cdma; 103 104/* IOMMU support */ 105static void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 106 107/* 108 * Methods 109 */ 110static device_probe_t schizo_probe; 111static device_attach_t schizo_attach; 112static bus_read_ivar_t schizo_read_ivar; 113static bus_setup_intr_t schizo_setup_intr; 114static bus_alloc_resource_t schizo_alloc_resource; 115static bus_activate_resource_t schizo_activate_resource; 116static bus_deactivate_resource_t schizo_deactivate_resource; 117static bus_release_resource_t schizo_release_resource; 118static bus_get_dma_tag_t schizo_get_dma_tag; 119static pcib_maxslots_t schizo_maxslots; 120static pcib_read_config_t schizo_read_config; 121static pcib_write_config_t schizo_write_config; 122static pcib_route_interrupt_t schizo_route_interrupt; 123static ofw_bus_get_node_t schizo_get_node; 124static ofw_pci_setup_device_t schizo_setup_device; 125 126static device_method_t schizo_methods[] = { 127 /* Device interface */ 128 DEVMETHOD(device_probe, schizo_probe), 129 DEVMETHOD(device_attach, schizo_attach), 130 DEVMETHOD(device_shutdown, bus_generic_shutdown), 131 DEVMETHOD(device_suspend, bus_generic_suspend), 132 DEVMETHOD(device_resume, bus_generic_resume), 133 134 /* Bus interface */ 135 DEVMETHOD(bus_print_child, bus_generic_print_child), 136 DEVMETHOD(bus_read_ivar, schizo_read_ivar), 137 DEVMETHOD(bus_setup_intr, schizo_setup_intr), 138 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 139 DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 140 DEVMETHOD(bus_activate_resource, schizo_activate_resource), 141 DEVMETHOD(bus_deactivate_resource, schizo_deactivate_resource), 142 DEVMETHOD(bus_release_resource, schizo_release_resource), 143 DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 144 145 /* pcib interface */ 146 DEVMETHOD(pcib_maxslots, schizo_maxslots), 147 DEVMETHOD(pcib_read_config, schizo_read_config), 148 DEVMETHOD(pcib_write_config, schizo_write_config), 149 DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 150 151 /* ofw_bus interface */ 152 DEVMETHOD(ofw_bus_get_node, schizo_get_node), 153 154 /* ofw_pci interface */ 155 DEVMETHOD(ofw_pci_setup_device, schizo_setup_device), 156 157 KOBJMETHOD_END 158}; 159 160static devclass_t schizo_devclass; 161 162DEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 163 sizeof(struct schizo_softc)); 164EARLY_DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0, 165 BUS_PASS_BUS); 166 167static SLIST_HEAD(, schizo_softc) schizo_softcs = 168 SLIST_HEAD_INITIALIZER(schizo_softcs); 169 170static const struct intr_controller schizo_ic = { 171 schizo_intr_enable, 172 schizo_intr_disable, 173 schizo_intr_assign, 174 schizo_intr_clear 175}; 176 177struct schizo_icarg { 178 struct schizo_softc *sica_sc; 179 bus_addr_t sica_map; 180 bus_addr_t sica_clr; 181}; 182 183#define SCHIZO_PERF_CNT_QLTY 100 184 185#define SCHIZO_SPC_BARRIER(spc, sc, offs, len, flags) \ 186 bus_barrier((sc)->sc_mem_res[(spc)], (offs), (len), (flags)) 187#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 188 bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 189#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 190 bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 191 192#ifndef SCHIZO_DEBUG 193#define SCHIZO_SPC_SET(spc, sc, offs, reg, v) \ 194 SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)) 195#else 196#define SCHIZO_SPC_SET(spc, sc, offs, reg, v) do { \ 197 device_printf((sc)->sc_dev, reg " 0x%016llx -> 0x%016llx\n", \ 198 (unsigned long long)SCHIZO_SPC_READ_8((spc), (sc), (offs)), \ 199 (unsigned long long)(v)); \ 200 SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)); \ 201 } while (0) 202#endif 203 204#define SCHIZO_PCI_READ_8(sc, offs) \ 205 SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 206#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 207 SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 208#define SCHIZO_CTRL_READ_8(sc, offs) \ 209 SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 210#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 211 SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 212#define SCHIZO_PCICFG_READ_8(sc, offs) \ 213 SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 214#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 215 SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 216#define SCHIZO_ICON_READ_8(sc, offs) \ 217 SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 218#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 219 SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 220 221#define SCHIZO_PCI_SET(sc, offs, v) \ 222 SCHIZO_SPC_SET(STX_PCI, (sc), (offs), # offs, (v)) 223#define SCHIZO_CTRL_SET(sc, offs, v) \ 224 SCHIZO_SPC_SET(STX_CTRL, (sc), (offs), # offs, (v)) 225 226struct schizo_desc { 227 const char *sd_string; 228 int sd_mode; 229 const char *sd_name; 230}; 231 232static const struct schizo_desc const schizo_compats[] = { 233 { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 234#if 0 235 { "pci108e,8002", SCHIZO_MODE_XMS, "XMITS" }, 236#endif 237 { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 238 { NULL, 0, NULL } 239}; 240 241static const struct schizo_desc * 242schizo_get_desc(device_t dev) 243{ 244 const struct schizo_desc *desc; 245 const char *compat; 246 247 compat = ofw_bus_get_compat(dev); 248 if (compat == NULL) 249 return (NULL); 250 for (desc = schizo_compats; desc->sd_string != NULL; desc++) 251 if (strcmp(desc->sd_string, compat) == 0) 252 return (desc); 253 return (NULL); 254} 255 256static int 257schizo_probe(device_t dev) 258{ 259 const char *dtype; 260 261 dtype = ofw_bus_get_type(dev); 262 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 263 schizo_get_desc(dev) != NULL) { 264 device_set_desc(dev, "Sun Host-PCI bridge"); 265 return (0); 266 } 267 return (ENXIO); 268} 269 270static int 271schizo_attach(device_t dev) 272{ 273 struct ofw_pci_ranges *range; 274 const struct schizo_desc *desc; 275 struct schizo_softc *asc, *sc, *osc; 276 struct timecounter *tc; 277 uint64_t ino_bitmap, reg; 278 phandle_t node; 279 uint32_t prop, prop_array[2]; 280 int i, j, mode, rid, tsbsize; 281 282 sc = device_get_softc(dev); 283 node = ofw_bus_get_node(dev); 284 desc = schizo_get_desc(dev); 285 mode = desc->sd_mode; 286 287 sc->sc_dev = dev; 288 sc->sc_node = node; 289 sc->sc_mode = mode; 290 sc->sc_flags = 0; 291 292 /* 293 * The Schizo has three register banks: 294 * (0) per-PBM PCI configuration and status registers, but for bus B 295 * shared with the UPA64s interrupt mapping register banks 296 * (1) shared Schizo controller configuration and status registers 297 * (2) per-PBM PCI configuration space 298 * 299 * The Tomatillo has four register banks: 300 * (0) per-PBM PCI configuration and status registers 301 * (1) per-PBM Tomatillo controller configuration registers, but on 302 * machines having the `jbusppm' device shared with its Estar 303 * register bank for bus A 304 * (2) per-PBM PCI configuration space 305 * (3) per-PBM interrupt concentrator registers 306 */ 307 sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 308 20) & 1; 309 for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 310 i++) { 311 rid = i; 312 sc->sc_mem_res[i] = bus_alloc_resource_any(dev, 313 SYS_RES_MEMORY, &rid, 314 (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 315 i == STX_PCI) || i == STX_CTRL)) || 316 (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 317 i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 318 if (sc->sc_mem_res[i] == NULL) 319 panic("%s: could not allocate register bank %d", 320 __func__, i); 321 } 322 323 /* 324 * Match other Schizos that are already configured against 325 * the controller base physical address. This will be the 326 * same for a pair of devices that share register space. 327 */ 328 osc = NULL; 329 SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 330 if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 331 rman_get_start(sc->sc_mem_res[STX_CTRL])) { 332 /* Found partner. */ 333 osc = asc; 334 break; 335 } 336 } 337 if (osc == NULL) { 338 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 339 M_NOWAIT | M_ZERO); 340 if (sc->sc_mtx == NULL) 341 panic("%s: could not malloc mutex", __func__); 342 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 343 } else { 344 if (sc->sc_mode != SCHIZO_MODE_SCZ) 345 panic("%s: no partner expected", __func__); 346 if (mtx_initialized(osc->sc_mtx) == 0) 347 panic("%s: mutex not initialized", __func__); 348 sc->sc_mtx = osc->sc_mtx; 349 } 350 351 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 352 panic("%s: could not determine IGN", __func__); 353 if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == 354 -1) 355 panic("%s: could not determine version", __func__); 356 if (mode == SCHIZO_MODE_XMS && OF_getprop(node, "module-revision#", 357 &sc->sc_mrev, sizeof(sc->sc_mrev)) == -1) 358 panic("%s: could not determine module-revision", __func__); 359 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 360 prop = 33000000; 361 362 if (mode == SCHIZO_MODE_XMS && (SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL) & 363 XMS_PCI_CTRL_X_MODE) != 0) { 364 if (sc->sc_mrev < 1) 365 panic("PCI-X mode unsupported"); 366 sc->sc_flags |= SCHIZO_FLAGS_XMODE; 367 } 368 369 device_printf(dev, "%s, version %d, ", desc->sd_name, sc->sc_ver); 370 if (mode == SCHIZO_MODE_XMS) 371 printf("module-revision %d, ", sc->sc_mrev); 372 printf("IGN %#x, bus %c, PCI%s mode, %dMHz\n", sc->sc_ign, 373 'A' + sc->sc_half, (sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 374 "-X" : "", prop / 1000 / 1000); 375 376 /* Set up the PCI interrupt retry timer. */ 377 SCHIZO_PCI_SET(sc, STX_PCI_INTR_RETRY_TIM, 5); 378 379 /* Set up the PCI control register. */ 380 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 381 reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK | 382 STX_PCI_CTRL_ARB_MASK); 383 reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 384 STX_PCI_CTRL_ERR_IEN; 385 if (OF_getproplen(node, "no-bus-parking") < 0) 386 reg |= STX_PCI_CTRL_ARB_PARK; 387 if (mode == SCHIZO_MODE_XMS && sc->sc_mrev == 1) 388 reg |= XMS_PCI_CTRL_XMITS10_ARB_MASK; 389 else 390 reg |= STX_PCI_CTRL_ARB_MASK; 391 if (mode == SCHIZO_MODE_TOM) { 392 reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 393 if (sc->sc_ver <= 1) /* revision <= 2.0 */ 394 reg |= TOM_PCI_CTRL_DTO_IEN; 395 else 396 reg |= STX_PCI_CTRL_PTO; 397 } else if (mode == SCHIZO_MODE_XMS) { 398 SCHIZO_PCI_SET(sc, XMS_PCI_PARITY_DETECT, 0x3fff); 399 SCHIZO_PCI_SET(sc, XMS_PCI_UPPER_RETRY_COUNTER, 0x3e8); 400 reg |= XMS_PCI_CTRL_X_ERRINT_EN; 401 } 402 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, reg); 403 404 /* Set up the PCI diagnostic register. */ 405 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 406 reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 407 STX_PCI_DIAG_INTRSYNC_DIS); 408 SCHIZO_PCI_SET(sc, STX_PCI_DIAG, reg); 409 410 /* 411 * Enable DMA write parity error interrupts of version >= 7 (i.e. 412 * revision >= 2.5) Schizo and XMITS (enabling it on XMITS < 3.0 has 413 * no effect though). 414 */ 415 if ((mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 7) || 416 mode == SCHIZO_MODE_XMS) { 417 reg = SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD); 418 reg |= SX_PCI_CFG_ICD_DMAW_PERR_IEN; 419 SCHIZO_PCI_SET(sc, SX_PCI_CFG_ICD, reg); 420 } 421 422 /* 423 * On Tomatillo clear the I/O prefetch lengths (workaround for a 424 * Jalapeno bug). 425 */ 426 if (mode == SCHIZO_MODE_TOM) 427 SCHIZO_PCI_SET(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 428 (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 429 TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 430 431 /* 432 * Hunt through all the interrupt mapping regs and register 433 * the interrupt controller for our interrupt vectors. We do 434 * this early in order to be able to catch stray interrupts. 435 * This is complicated by the fact that a pair of Schizo PBMs 436 * shares one IGN. 437 */ 438 i = OF_getprop(node, "ino-bitmap", (void *)prop_array, 439 sizeof(prop_array)); 440 if (i != -1) 441 ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 442 else { 443 /* 444 * If the ino-bitmap property is missing, just provide the 445 * default set of interrupts for this controller and let 446 * schizo_setup_intr() take care of child interrupts. 447 */ 448 if (sc->sc_half == 0) 449 ino_bitmap = (1ULL << STX_UE_INO) | 450 (1ULL << STX_CE_INO) | 451 (1ULL << STX_PCIERR_A_INO) | 452 (1ULL << STX_BUS_INO); 453 else 454 ino_bitmap = 1ULL << STX_PCIERR_B_INO; 455 } 456 for (i = 0; i <= STX_MAX_INO; i++) { 457 if ((ino_bitmap & (1ULL << i)) == 0) 458 continue; 459 if (i == STX_FB0_INO || i == STX_FB1_INO) 460 /* Leave for upa(4). */ 461 continue; 462 j = schizo_intr_register(sc, i); 463 if (j != 0) 464 device_printf(dev, "could not register interrupt " 465 "controller for INO %d (%d)\n", i, j); 466 } 467 468 /* 469 * Setup Safari/JBus performance counter 0 in bus cycle counting 470 * mode as timecounter. Unfortunately, this is broken with at 471 * least the version 4 Tomatillos found in Fire V120 and Blade 472 * 1500, which apparently actually count some different event at 473 * ~0.5 and 3MHz respectively instead (also when running in full 474 * power mode). Besides, one counter seems to be shared by a 475 * "pair" of Tomatillos, too. 476 */ 477 if (sc->sc_half == 0) { 478 SCHIZO_CTRL_SET(sc, STX_CTRL_PERF, 479 (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 480 (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 481 tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 482 if (tc == NULL) 483 panic("%s: could not malloc timecounter", __func__); 484 tc->tc_get_timecount = schizo_get_timecount; 485 tc->tc_poll_pps = NULL; 486 tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 487 if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 488 sizeof(prop)) == -1) 489 panic("%s: could not determine clock frequency", 490 __func__); 491 tc->tc_frequency = prop; 492 tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 493 if (mode == SCHIZO_MODE_SCZ) 494 tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 495 else 496 tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 497 tc->tc_priv = sc; 498 tc_init(tc); 499 } 500 501 /* 502 * Set up the IOMMU. Schizo, Tomatillo and XMITS all have 503 * one per PBM. Schizo and XMITS additionally have a streaming 504 * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's 505 * affected by several errata and basically unusable though. 506 */ 507 memcpy(&sc->sc_dma_methods, &iommu_dma_methods, 508 sizeof(sc->sc_dma_methods)); 509 sc->sc_is.sis_sc = sc; 510 sc->sc_is.sis_is.is_flags = IOMMU_PRESERVE_PROM; 511 sc->sc_is.sis_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 512 sc->sc_is.sis_is.is_sb[0] = sc->sc_is.sis_is.is_sb[1] = 0; 513 if (OF_getproplen(node, "no-streaming-cache") < 0 && 514 !(sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver < 5)) 515 sc->sc_is.sis_is.is_sb[0] = STX_PCI_STRBUF; 516 517#define TSBCASE(x) \ 518 case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 519 tsbsize = (x); \ 520 break; \ 521 522 i = OF_getprop(node, "virtual-dma", (void *)prop_array, 523 sizeof(prop_array)); 524 if (i == -1 || i != sizeof(prop_array)) 525 schizo_iommu_init(sc, 7, -1); 526 else { 527 switch (prop_array[1]) { 528 TSBCASE(1); 529 TSBCASE(2); 530 TSBCASE(3); 531 TSBCASE(4); 532 TSBCASE(5); 533 TSBCASE(6); 534 TSBCASE(7); 535 TSBCASE(8); 536 default: 537 panic("%s: unsupported DVMA size 0x%x", 538 __func__, prop_array[1]); 539 /* NOTREACHED */ 540 } 541 schizo_iommu_init(sc, tsbsize, prop_array[0]); 542 } 543 544#undef TSBCASE 545 546 /* Initialize memory and I/O rmans. */ 547 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 548 sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 549 if (rman_init(&sc->sc_pci_io_rman) != 0 || 550 rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 551 panic("%s: failed to set up I/O rman", __func__); 552 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 553 sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 554 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 555 rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 556 panic("%s: failed to set up memory rman", __func__); 557 558 i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range); 559 /* 560 * Make sure that the expected ranges are present. The 561 * OFW_PCI_CS_MEM64 one is not currently used though. 562 */ 563 if (i != STX_NRANGE) 564 panic("%s: unsupported number of ranges", __func__); 565 /* 566 * Find the addresses of the various bus spaces. 567 * There should not be multiple ones of one kind. 568 * The physical start addresses of the ranges are the configuration, 569 * memory and I/O handles. 570 */ 571 for (i = 0; i < STX_NRANGE; i++) { 572 j = OFW_PCI_RANGE_CS(&range[i]); 573 if (sc->sc_pci_bh[j] != 0) 574 panic("%s: duplicate range for space %d", 575 __func__, j); 576 sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]); 577 } 578 free(range, M_OFWPROP); 579 580 /* Register the softc, this is needed for paired Schizos. */ 581 SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 582 583 /* Allocate our tags. */ 584 sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 585 sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 586 sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 587 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 588 sc->sc_is.sis_is.is_pmaxaddr, ~0, NULL, NULL, 589 sc->sc_is.sis_is.is_pmaxaddr, 0xff, 0xffffffff, 0, NULL, NULL, 590 &sc->sc_pci_dmat) != 0) 591 panic("%s: bus_dma_tag_create failed", __func__); 592 /* Customize the tag. */ 593 sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 594 sc->sc_pci_dmat->dt_mt = &sc->sc_dma_methods; 595 596 /* 597 * Get the bus range from the firmware. 598 * NB: Tomatillos don't support PCI bus reenumeration. 599 */ 600 i = OF_getprop(node, "bus-range", (void *)prop_array, 601 sizeof(prop_array)); 602 if (i == -1) 603 panic("%s: could not get bus-range", __func__); 604 if (i != sizeof(prop_array)) 605 panic("%s: broken bus-range (%d)", __func__, i); 606 sc->sc_pci_secbus = prop_array[0]; 607 sc->sc_pci_subbus = prop_array[1]; 608 if (bootverbose) 609 device_printf(dev, "bus range %u to %u; PCI bus %d\n", 610 sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus); 611 612 /* Clear any pending PCI error bits. */ 613 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 614 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 615 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 616 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 617 SCHIZO_PCI_SET(sc, STX_PCI_AFSR, SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 618 619 /* 620 * Establish handlers for interesting interrupts... 621 * Someone at Sun clearly was smoking crack; with Schizos PCI 622 * bus error interrupts for one PBM can be routed to the other 623 * PBM though we obviously need to use the softc of the former 624 * as the argument for the interrupt handler and the softc of 625 * the latter as the argument for the interrupt controller. 626 */ 627 if (sc->sc_half == 0) { 628 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 629 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 630 INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 631 sica_sc == osc)) 632 /* 633 * We are the driver for PBM A and either also 634 * registered the interrupt controller for us or 635 * the driver for PBM B has probed first and 636 * registered it for us. 637 */ 638 schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 639 schizo_pci_bus); 640 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 641 osc != NULL) 642 /* 643 * We are the driver for PBM A but registered 644 * the interrupt controller for PBM B, i.e. the 645 * driver for PBM B attached first but couldn't 646 * set up a handler for PBM B. 647 */ 648 schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 649 schizo_pci_bus); 650 } else { 651 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 652 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 653 INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 654 sica_sc == osc)) 655 /* 656 * We are the driver for PBM B and either also 657 * registered the interrupt controller for us or 658 * the driver for PBM A has probed first and 659 * registered it for us. 660 */ 661 schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 662 schizo_pci_bus); 663 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 664 osc != NULL) 665 /* 666 * We are the driver for PBM B but registered 667 * the interrupt controller for PBM A, i.e. the 668 * driver for PBM A attached first but couldn't 669 * set up a handler for PBM A. 670 */ 671 schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 672 schizo_pci_bus); 673 } 674 if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 675 schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 676 if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 677 schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 678 if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 679 schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 680 681 /* 682 * According to the Schizo Errata I-13, consistent DMA flushing/ 683 * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 684 * so we can't use it and need to live with the consequences. With 685 * Schizo version >= 5, CDMA flushing/syncing is usable but requires 686 * the workaround described in Schizo Errata I-23. With Tomatillo 687 * and XMITS, CDMA flushing/syncing works as expected, Tomatillo 688 * version <= 4 (i.e. revision <= 2.3) bridges additionally require 689 * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though. 690 */ 691 if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 692 sc->sc_mode == SCHIZO_MODE_TOM || 693 sc->sc_mode == SCHIZO_MODE_XMS) { 694 if (sc->sc_mode == SCHIZO_MODE_SCZ) { 695 sc->sc_dma_methods.dm_dmamap_sync = 696 schizo_dmamap_sync; 697 sc->sc_cdma_state = SCHIZO_CDMA_STATE_IDLE; 698 /* 699 * Some firmware versions include the CDMA interrupt 700 * at RID 4 but most don't. With the latter we add 701 * it ourselves at the spare RID 5. 702 */ 703 i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ, 704 4)); 705 if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) { 706 (void)schizo_get_intrmap(sc, i, NULL, 707 &sc->sc_cdma_clr); 708 schizo_set_intr(sc, 4, i, schizo_cdma); 709 } else { 710 i = STX_CDMA_A_INO + sc->sc_half; 711 if (bus_set_resource(dev, SYS_RES_IRQ, 5, 712 INTMAP_VEC(sc->sc_ign, i), 1) != 0) 713 panic("%s: failed to add CDMA " 714 "interrupt", __func__); 715 j = schizo_intr_register(sc, i); 716 if (j != 0) 717 panic("%s: could not register " 718 "interrupt controller for CDMA " 719 "(%d)", __func__, j); 720 (void)schizo_get_intrmap(sc, i, NULL, 721 &sc->sc_cdma_clr); 722 schizo_set_intr(sc, 5, i, schizo_cdma); 723 } 724 } else { 725 if (sc->sc_mode == SCHIZO_MODE_XMS) 726 mtx_init(&sc->sc_sync_mtx, "pcib_sync_mtx", 727 NULL, MTX_SPIN); 728 sc->sc_sync_val = 1ULL << (STX_PCIERR_A_INO + 729 sc->sc_half); 730 sc->sc_dma_methods.dm_dmamap_sync = 731 ichip_dmamap_sync; 732 } 733 if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 734 sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 735 } 736 737 /* 738 * Set the latency timer register as this isn't always done by the 739 * firmware. 740 */ 741 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 742 PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 743 744 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 745 746#define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \ 747 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \ 748 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, \ 749 (name), CTLFLAG_RD, (arg), 0, (desc)) 750 751 SCHIZO_SYSCTL_ADD_UINT("dma_ce", &sc->sc_stats_dma_ce, 752 "DMA correctable errors"); 753 SCHIZO_SYSCTL_ADD_UINT("pci_non_fatal", &sc->sc_stats_pci_non_fatal, 754 "PCI bus non-fatal errors"); 755 756#undef SCHIZO_SYSCTL_ADD_UINT 757 758 device_add_child(dev, "pci", -1); 759 return (bus_generic_attach(dev)); 760} 761 762static void 763schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 764 driver_filter_t handler) 765{ 766 u_long vec; 767 int rid; 768 769 rid = index; 770 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 771 SYS_RES_IRQ, &rid, RF_ACTIVE); 772 if (sc->sc_irq_res[index] == NULL || 773 INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino || 774 INTIGN(vec) != sc->sc_ign || 775 intr_vectors[vec].iv_ic != &schizo_ic || 776 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 777 INTR_TYPE_MISC | INTR_BRIDGE, handler, NULL, sc, 778 &sc->sc_ihand[index]) != 0) 779 panic("%s: failed to set up interrupt %d", __func__, index); 780} 781 782static int 783schizo_intr_register(struct schizo_softc *sc, u_int ino) 784{ 785 struct schizo_icarg *sica; 786 bus_addr_t intrclr, intrmap; 787 int error; 788 789 if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 790 return (ENXIO); 791 sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 792 if (sica == NULL) 793 return (ENOMEM); 794 sica->sica_sc = sc; 795 sica->sica_map = intrmap; 796 sica->sica_clr = intrclr; 797#ifdef SCHIZO_DEBUG 798 device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 799 ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 800 (u_long)intrclr); 801#endif 802 error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 803 &schizo_ic, sica)); 804 if (error != 0) 805 free(sica, M_DEVBUF); 806 return (error); 807} 808 809static int 810schizo_get_intrmap(struct schizo_softc *sc, u_int ino, 811 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr) 812{ 813 bus_addr_t intrclr, intrmap; 814 uint64_t mr; 815 816 /* 817 * XXX we only look for INOs rather than INRs since the firmware 818 * may not provide the IGN and the IGN is constant for all devices 819 * on that PCI controller. 820 */ 821 822 if (ino > STX_MAX_INO) { 823 device_printf(sc->sc_dev, "out of range INO %d requested\n", 824 ino); 825 return (0); 826 } 827 828 intrmap = STX_PCI_IMAP_BASE + (ino << 3); 829 intrclr = STX_PCI_ICLR_BASE + (ino << 3); 830 mr = SCHIZO_PCI_READ_8(sc, intrmap); 831 if (INTINO(mr) != ino) { 832 device_printf(sc->sc_dev, 833 "interrupt map entry does not match INO (%d != %d)\n", 834 (int)INTINO(mr), ino); 835 return (0); 836 } 837 838 if (intrmapptr != NULL) 839 *intrmapptr = intrmap; 840 if (intrclrptr != NULL) 841 *intrclrptr = intrclr; 842 return (1); 843} 844 845/* 846 * Interrupt handlers 847 */ 848static int 849schizo_pci_bus(void *arg) 850{ 851 struct schizo_softc *sc = arg; 852 uint64_t afar, afsr, csr, iommu, xstat; 853 uint32_t status; 854 u_int fatal; 855 856 fatal = 0; 857 858 mtx_lock_spin(sc->sc_mtx); 859 860 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 861 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 862 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 863 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 864 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 865 xstat = SCHIZO_PCI_READ_8(sc, XMS_PCI_X_ERR_STAT); 866 else 867 xstat = 0; 868 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 869 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 870 871 /* 872 * IOMMU errors are only fatal on Tomatillo and there also only if 873 * target abort was not signaled. 874 */ 875 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0 && 876 (iommu & TOM_PCI_IOMMU_ERR) != 0 && 877 ((status & PCIM_STATUS_STABORT) == 0 || 878 ((iommu & TOM_PCI_IOMMU_ERRMASK) != TOM_PCI_IOMMU_INVALID_ERR && 879 (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) == 0 && 880 (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) == 0))) 881 fatal = 1; 882 else if ((status & PCIM_STATUS_STABORT) != 0) 883 fatal = 1; 884 if ((status & (PCIM_STATUS_PERR | PCIM_STATUS_SERR | 885 PCIM_STATUS_RMABORT | PCIM_STATUS_RTABORT | 886 PCIM_STATUS_MDPERR)) != 0 || 887 (csr & (SCZ_PCI_CTRL_BUS_UNUS | TOM_PCI_CTRL_DTO_ERR | 888 STX_PCI_CTRL_TTO_ERR | STX_PCI_CTRL_RTRY_ERR | 889 SCZ_PCI_CTRL_SBH_ERR | STX_PCI_CTRL_SERR)) != 0 || 890 (afsr & (STX_PCI_AFSR_P_MA | STX_PCI_AFSR_P_TA | 891 STX_PCI_AFSR_P_RTRY | STX_PCI_AFSR_P_PERR | STX_PCI_AFSR_P_TTO | 892 STX_PCI_AFSR_P_UNUS)) != 0) 893 fatal = 1; 894 if (xstat & (XMS_PCI_X_ERR_STAT_P_SC_DSCRD | 895 XMS_PCI_X_ERR_STAT_P_SC_TTO | XMS_PCI_X_ERR_STAT_P_SDSTAT | 896 XMS_PCI_X_ERR_STAT_P_SMMU | XMS_PCI_X_ERR_STAT_P_CDSTAT | 897 XMS_PCI_X_ERR_STAT_P_CMMU | XMS_PCI_X_ERR_STAT_PERR_RCV)) 898 fatal = 1; 899 if (fatal == 0) 900 sc->sc_stats_pci_non_fatal++; 901 902 device_printf(sc->sc_dev, "PCI bus %c error AFAR %#llx AFSR %#llx " 903 "PCI CSR %#llx IOMMU %#llx PCI-X %#llx STATUS %#x\n", 904 'A' + sc->sc_half, (unsigned long long)afar, 905 (unsigned long long)afsr, (unsigned long long)csr, 906 (unsigned long long)iommu, (unsigned long long)xstat, status); 907 908 /* Clear the error bits that we caught. */ 909 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 910 STX_CS_FUNC, PCIR_STATUS, status, 2); 911 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 912 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 913 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 914 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 915 SCHIZO_PCI_WRITE_8(sc, XMS_PCI_X_ERR_STAT, xstat); 916 917 mtx_unlock_spin(sc->sc_mtx); 918 919 if (fatal != 0) 920 panic("%s: fatal PCI bus error", 921 device_get_nameunit(sc->sc_dev)); 922 return (FILTER_HANDLED); 923} 924 925static int 926schizo_ue(void *arg) 927{ 928 struct schizo_softc *sc = arg; 929 uint64_t afar, afsr; 930 int i; 931 932 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 933 for (i = 0; i < 1000; i++) 934 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 935 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 936 break; 937 panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 938 device_get_nameunit(sc->sc_dev), (unsigned long long)afar, 939 (unsigned long long)afsr); 940 return (FILTER_HANDLED); 941} 942 943static int 944schizo_ce(void *arg) 945{ 946 struct schizo_softc *sc = arg; 947 uint64_t afar, afsr; 948 int i; 949 950 mtx_lock_spin(sc->sc_mtx); 951 952 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 953 for (i = 0; i < 1000; i++) 954 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 955 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 956 break; 957 sc->sc_stats_dma_ce++; 958 device_printf(sc->sc_dev, 959 "correctable DMA error AFAR %#llx AFSR %#llx\n", 960 (unsigned long long)afar, (unsigned long long)afsr); 961 962 /* Clear the error bits that we caught. */ 963 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 964 965 mtx_unlock_spin(sc->sc_mtx); 966 967 return (FILTER_HANDLED); 968} 969 970static int 971schizo_host_bus(void *arg) 972{ 973 struct schizo_softc *sc = arg; 974 uint64_t errlog; 975 976 errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 977 panic("%s: %s error %#llx", device_get_nameunit(sc->sc_dev), 978 sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 979 (unsigned long long)errlog); 980 return (FILTER_HANDLED); 981} 982 983static int 984schizo_cdma(void *arg) 985{ 986 struct schizo_softc *sc = arg; 987 988 atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_RECEIVED); 989 return (FILTER_HANDLED); 990} 991 992static void 993schizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 994{ 995 996 /* Punch in our copies. */ 997 sc->sc_is.sis_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 998 sc->sc_is.sis_is.is_bushandle = 999 rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 1000 sc->sc_is.sis_is.is_iommu = STX_PCI_IOMMU; 1001 sc->sc_is.sis_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 1002 sc->sc_is.sis_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 1003 sc->sc_is.sis_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 1004 sc->sc_is.sis_is.is_dva = STX_PCI_IOMMU_SVADIAG; 1005 sc->sc_is.sis_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 1006 1007 iommu_init(device_get_nameunit(sc->sc_dev), 1008 (struct iommu_state *)&sc->sc_is, tsbsize, dvmabase, 0); 1009} 1010 1011static int 1012schizo_maxslots(device_t dev) 1013{ 1014 struct schizo_softc *sc; 1015 1016 sc = device_get_softc(dev); 1017 if (sc->sc_mode == SCHIZO_MODE_SCZ) 1018 return (sc->sc_half == 0 ? 4 : 6); 1019 1020 /* XXX: is this correct? */ 1021 return (PCI_SLOTMAX); 1022} 1023 1024static uint32_t 1025schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 1026 int width) 1027{ 1028 struct schizo_softc *sc; 1029 bus_space_handle_t bh; 1030 u_long offset = 0; 1031 uint32_t r, wrd; 1032 int i; 1033 uint16_t shrt; 1034 uint8_t byte; 1035 1036 sc = device_get_softc(dev); 1037 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1038 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1039 return (-1); 1040 1041 /* 1042 * The Schizo bridges contain a dupe of their header at 0x80. 1043 */ 1044 if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 1045 slot == STX_CS_DEVICE && func == STX_CS_FUNC && 1046 reg + width > 0x80) 1047 return (0); 1048 1049 offset = STX_CONF_OFF(bus, slot, func, reg); 1050 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1051 switch (width) { 1052 case 1: 1053 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 1054 r = byte; 1055 break; 1056 case 2: 1057 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 1058 r = shrt; 1059 break; 1060 case 4: 1061 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 1062 r = wrd; 1063 break; 1064 default: 1065 panic("%s: bad width", __func__); 1066 /* NOTREACHED */ 1067 } 1068 1069 if (i) { 1070#ifdef SCHIZO_DEBUG 1071 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 1072 __func__, bus, slot, func, reg); 1073#endif 1074 r = -1; 1075 } 1076 return (r); 1077} 1078 1079static void 1080schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1081 u_int reg, uint32_t val, int width) 1082{ 1083 struct schizo_softc *sc; 1084 bus_space_handle_t bh; 1085 u_long offset = 0; 1086 1087 sc = device_get_softc(dev); 1088 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1089 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1090 return; 1091 1092 offset = STX_CONF_OFF(bus, slot, func, reg); 1093 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1094 switch (width) { 1095 case 1: 1096 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1097 break; 1098 case 2: 1099 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1100 break; 1101 case 4: 1102 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1103 break; 1104 default: 1105 panic("%s: bad width", __func__); 1106 /* NOTREACHED */ 1107 } 1108} 1109 1110static int 1111schizo_route_interrupt(device_t bridge, device_t dev, int pin) 1112{ 1113 struct schizo_softc *sc; 1114 struct ofw_pci_register reg; 1115 ofw_pci_intr_t pintr, mintr; 1116 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 1117 1118 sc = device_get_softc(bridge); 1119 pintr = pin; 1120 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1121 ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), 1122 NULL, maskbuf)) 1123 return (mintr); 1124 1125 device_printf(bridge, "could not route pin %d for device %d.%d\n", 1126 pin, pci_get_slot(dev), pci_get_function(dev)); 1127 return (PCI_INVALID_IRQ); 1128} 1129 1130static int 1131schizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1132{ 1133 struct schizo_softc *sc; 1134 1135 sc = device_get_softc(dev); 1136 switch (which) { 1137 case PCIB_IVAR_DOMAIN: 1138 *result = device_get_unit(dev); 1139 return (0); 1140 case PCIB_IVAR_BUS: 1141 *result = sc->sc_pci_secbus; 1142 return (0); 1143 } 1144 return (ENOENT); 1145} 1146 1147static void 1148schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1149{ 1150 struct timeval cur, end; 1151 struct schizo_iommu_state *sis = dt->dt_cookie; 1152 struct schizo_softc *sc = sis->sis_sc; 1153 int res; 1154 1155 if ((map->dm_flags & DMF_STREAMED) != 0) { 1156 iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1157 return; 1158 } 1159 1160 if ((map->dm_flags & DMF_LOADED) == 0) 1161 return; 1162 1163 if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1164 /* 1165 * Note that in order to allow this function to be called from 1166 * filters we would need to use a spin mutex for serialization 1167 * but given that these disable interrupts we have to emulate 1168 * one. 1169 */ 1170 for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, 1171 SCHIZO_CDMA_STATE_IDLE, SCHIZO_CDMA_STATE_PENDING) == 0;) 1172 ; 1173 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, INTCLR_RECEIVED); 1174 microuptime(&cur); 1175 end.tv_sec = 1; 1176 end.tv_usec = 0; 1177 timevaladd(&end, &cur); 1178 for (; (res = atomic_cmpset_rel_32(&sc->sc_cdma_state, 1179 SCHIZO_CDMA_STATE_RECEIVED, SCHIZO_CDMA_STATE_IDLE)) == 1180 0 && timevalcmp(&cur, &end, <=);) 1181 microuptime(&cur); 1182 if (res == 0) 1183 panic("%s: DMA does not sync", __func__); 1184 } 1185 1186 if ((op & BUS_DMASYNC_PREWRITE) != 0) 1187 membar(Sync); 1188} 1189 1190#define VIS_BLOCKSIZE 64 1191 1192static void 1193ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1194{ 1195 static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 1196 struct timeval cur, end; 1197 struct schizo_iommu_state *sis = dt->dt_cookie; 1198 struct schizo_softc *sc = sis->sis_sc; 1199 register_t reg, s; 1200 1201 if ((map->dm_flags & DMF_STREAMED) != 0) { 1202 iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1203 return; 1204 } 1205 1206 if ((map->dm_flags & DMF_LOADED) == 0) 1207 return; 1208 1209 if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1210 if (sc->sc_mode == SCHIZO_MODE_XMS) 1211 mtx_lock_spin(&sc->sc_sync_mtx); 1212 SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, 1213 sc->sc_sync_val); 1214 microuptime(&cur); 1215 end.tv_sec = 1; 1216 end.tv_usec = 0; 1217 timevaladd(&end, &cur); 1218 for (; ((reg = SCHIZO_PCI_READ_8(sc, 1219 TOMXMS_PCI_DMA_SYNC_PEND)) & sc->sc_sync_val) != 0 && 1220 timevalcmp(&cur, &end, <=);) 1221 microuptime(&cur); 1222 if ((reg & sc->sc_sync_val) != 0) 1223 panic("%s: DMA does not sync", __func__); 1224 if (sc->sc_mode == SCHIZO_MODE_XMS) 1225 mtx_unlock_spin(&sc->sc_sync_mtx); 1226 else if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1227 s = intr_disable(); 1228 reg = rd(fprs); 1229 wr(fprs, reg | FPRS_FEF, 0); 1230 __asm __volatile("stda %%f0, [%0] %1" 1231 : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 1232 membar(Sync); 1233 wr(fprs, reg, 0); 1234 intr_restore(s); 1235 return; 1236 } 1237 } 1238 1239 if ((op & BUS_DMASYNC_PREWRITE) != 0) 1240 membar(Sync); 1241} 1242 1243static void 1244schizo_intr_enable(void *arg) 1245{ 1246 struct intr_vector *iv = arg; 1247 struct schizo_icarg *sica = iv->iv_icarg; 1248 1249 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1250 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1251} 1252 1253static void 1254schizo_intr_disable(void *arg) 1255{ 1256 struct intr_vector *iv = arg; 1257 struct schizo_icarg *sica = iv->iv_icarg; 1258 1259 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1260} 1261 1262static void 1263schizo_intr_assign(void *arg) 1264{ 1265 struct intr_vector *iv = arg; 1266 struct schizo_icarg *sica = iv->iv_icarg; 1267 1268 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1269 SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1270} 1271 1272static void 1273schizo_intr_clear(void *arg) 1274{ 1275 struct intr_vector *iv = arg; 1276 struct schizo_icarg *sica = iv->iv_icarg; 1277 1278 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE); 1279} 1280 1281static int 1282schizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1283 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1284 void **cookiep) 1285{ 1286 struct schizo_softc *sc; 1287 u_long vec; 1288 int error; 1289 1290 sc = device_get_softc(dev); 1291 /* 1292 * Make sure the vector is fully specified. 1293 */ 1294 vec = rman_get_start(ires); 1295 if (INTIGN(vec) != sc->sc_ign) { 1296 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1297 return (EINVAL); 1298 } 1299 1300 if (intr_vectors[vec].iv_ic == &schizo_ic) { 1301 /* 1302 * Ensure we use the right softc in case the interrupt 1303 * is routed to our companion PBM for some odd reason. 1304 */ 1305 sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 1306 sica_sc; 1307 } else if (intr_vectors[vec].iv_ic == NULL) { 1308 /* 1309 * Work around broken firmware which misses entries in 1310 * the ino-bitmap. 1311 */ 1312 error = schizo_intr_register(sc, INTINO(vec)); 1313 if (error != 0) { 1314 device_printf(dev, "could not register interrupt " 1315 "controller for vector 0x%lx (%d)\n", vec, error); 1316 return (error); 1317 } 1318 if (bootverbose) 1319 device_printf(dev, "belatedly registered as " 1320 "interrupt controller for vector 0x%lx\n", vec); 1321 } else { 1322 device_printf(dev, 1323 "invalid interrupt controller for vector 0x%lx\n", vec); 1324 return (EINVAL); 1325 } 1326 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1327 arg, cookiep)); 1328} 1329 1330static struct resource * 1331schizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1332 u_long start, u_long end, u_long count, u_int flags) 1333{ 1334 struct schizo_softc *sc; 1335 struct resource *rv; 1336 struct rman *rm; 1337 bus_space_tag_t bt; 1338 bus_space_handle_t bh; 1339 int needactivate = flags & RF_ACTIVE; 1340 1341 flags &= ~RF_ACTIVE; 1342 1343 sc = device_get_softc(bus); 1344 if (type == SYS_RES_IRQ) { 1345 /* 1346 * XXX: Don't accept blank ranges for now, only single 1347 * interrupts. The other case should not happen with 1348 * the MI PCI code... 1349 * XXX: This may return a resource that is out of the 1350 * range that was specified. Is this correct...? 1351 */ 1352 if (start != end) 1353 panic("%s: XXX: interrupt range", __func__); 1354 start = end = INTMAP_VEC(sc->sc_ign, end); 1355 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, 1356 type, rid, start, end, count, flags)); 1357 } 1358 switch (type) { 1359 case SYS_RES_MEMORY: 1360 rm = &sc->sc_pci_mem_rman; 1361 bt = sc->sc_pci_memt; 1362 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1363 break; 1364 case SYS_RES_IOPORT: 1365 rm = &sc->sc_pci_io_rman; 1366 bt = sc->sc_pci_iot; 1367 bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1368 break; 1369 default: 1370 return (NULL); 1371 /* NOTREACHED */ 1372 } 1373 1374 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1375 if (rv == NULL) 1376 return (NULL); 1377 rman_set_rid(rv, *rid); 1378 bh += rman_get_start(rv); 1379 rman_set_bustag(rv, bt); 1380 rman_set_bushandle(rv, bh); 1381 1382 if (needactivate) { 1383 if (bus_activate_resource(child, type, *rid, rv)) { 1384 rman_release_resource(rv); 1385 return (NULL); 1386 } 1387 } 1388 return (rv); 1389} 1390 1391static int 1392schizo_activate_resource(device_t bus, device_t child, int type, int rid, 1393 struct resource *r) 1394{ 1395 void *p; 1396 int error; 1397 1398 if (type == SYS_RES_IRQ) 1399 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1400 type, rid, r)); 1401 if (type == SYS_RES_MEMORY) { 1402 /* 1403 * Need to memory-map the device space, as some drivers 1404 * depend on the virtual address being set and usable. 1405 */ 1406 error = sparc64_bus_mem_map(rman_get_bustag(r), 1407 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1408 if (error != 0) 1409 return (error); 1410 rman_set_virtual(r, p); 1411 } 1412 return (rman_activate_resource(r)); 1413} 1414 1415static int 1416schizo_deactivate_resource(device_t bus, device_t child, int type, int rid, 1417 struct resource *r) 1418{ 1419 1420 if (type == SYS_RES_IRQ) 1421 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1422 type, rid, r)); 1423 if (type == SYS_RES_MEMORY) { 1424 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1425 rman_set_virtual(r, NULL); 1426 } 1427 return (rman_deactivate_resource(r)); 1428} 1429 1430static int 1431schizo_release_resource(device_t bus, device_t child, int type, int rid, 1432 struct resource *r) 1433{ 1434 int error; 1435 1436 if (type == SYS_RES_IRQ) 1437 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1438 type, rid, r)); 1439 if (rman_get_flags(r) & RF_ACTIVE) { 1440 error = bus_deactivate_resource(child, type, rid, r); 1441 if (error) 1442 return (error); 1443 } 1444 return (rman_release_resource(r)); 1445} 1446 1447static bus_dma_tag_t 1448schizo_get_dma_tag(device_t bus, device_t child __unused) 1449{ 1450 struct schizo_softc *sc; 1451 1452 sc = device_get_softc(bus); 1453 return (sc->sc_pci_dmat); 1454} 1455 1456static phandle_t 1457schizo_get_node(device_t bus, device_t child __unused) 1458{ 1459 struct schizo_softc *sc; 1460 1461 sc = device_get_softc(bus); 1462 /* We only have one child, the PCI bus, which needs our own node. */ 1463 return (sc->sc_node); 1464} 1465 1466static void 1467schizo_setup_device(device_t bus, device_t child) 1468{ 1469 struct schizo_softc *sc; 1470 uint64_t reg; 1471 int capreg; 1472 1473 sc = device_get_softc(bus); 1474 /* 1475 * Disable bus parking in order to work around a bus hang caused by 1476 * Casinni/Skyhawk combinations. 1477 */ 1478 if (OF_getproplen(ofw_bus_get_node(child), "pci-req-removal") >= 0) 1479 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, 1480 STX_PCI_CTRL) & ~STX_PCI_CTRL_ARB_PARK); 1481 1482 if (sc->sc_mode == SCHIZO_MODE_XMS) { 1483 /* XMITS NCPQ WAR: set outstanding split transactions to 1. */ 1484 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 && 1485 (pci_read_config(child, PCIR_HDRTYPE, 1) & 1486 PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE && 1487 pci_find_cap(child, PCIY_PCIX, &capreg) == 0) 1488 pci_write_config(child, capreg + PCIXR_COMMAND, 1489 pci_read_config(child, capreg + PCIXR_COMMAND, 1490 2) & 0x7c, 2); 1491 /* XMITS 3.x WAR: set BUGCNTL iff value is unexpected. */ 1492 if (sc->sc_mrev >= 4) { 1493 reg = ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 1494 0xa0UL : 0xffUL) << XMS_PCI_X_DIAG_BUGCNTL_SHIFT; 1495 if ((SCHIZO_PCI_READ_8(sc, XMS_PCI_X_DIAG) & 1496 XMS_PCI_X_DIAG_BUGCNTL_MASK) != reg) 1497 SCHIZO_PCI_SET(sc, XMS_PCI_X_DIAG, reg); 1498 } 1499 } 1500} 1501 1502static bus_space_tag_t 1503schizo_alloc_bus_tag(struct schizo_softc *sc, int type) 1504{ 1505 bus_space_tag_t bt; 1506 1507 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1508 M_NOWAIT | M_ZERO); 1509 if (bt == NULL) 1510 panic("%s: out of memory", __func__); 1511 1512 bt->bst_cookie = sc; 1513 bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1514 bt->bst_type = type; 1515 return (bt); 1516} 1517 1518static u_int 1519schizo_get_timecount(struct timecounter *tc) 1520{ 1521 struct schizo_softc *sc; 1522 1523 sc = tc->tc_priv; 1524 return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1525 (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)); 1526} 1527