schizo.c revision 216961
1183423Smarius/*- 2183423Smarius * Copyright (c) 1999, 2000 Matthew R. Green 3183423Smarius * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4183423Smarius * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org> 5183423Smarius * All rights reserved. 6183423Smarius * 7183423Smarius * Redistribution and use in source and binary forms, with or without 8183423Smarius * modification, are permitted provided that the following conditions 9183423Smarius * are met: 10183423Smarius * 1. Redistributions of source code must retain the above copyright 11183423Smarius * notice, this list of conditions and the following disclaimer. 12183423Smarius * 2. Redistributions in binary form must reproduce the above copyright 13183423Smarius * notice, this list of conditions and the following disclaimer in the 14183423Smarius * documentation and/or other materials provided with the distribution. 15183423Smarius * 3. The name of the author may not be used to endorse or promote products 16183423Smarius * derived from this software without specific prior written permission. 17183423Smarius * 18183423Smarius * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19183423Smarius * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20183423Smarius * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21183423Smarius * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22183423Smarius * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23183423Smarius * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24183423Smarius * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25183423Smarius * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26183423Smarius * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27183423Smarius * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28183423Smarius * SUCH DAMAGE. 29183423Smarius * 30183423Smarius * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31183423Smarius * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32183423Smarius */ 33183423Smarius 34183423Smarius#include <sys/cdefs.h> 35183423Smarius__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 216961 2011-01-04 16:11:32Z marius $"); 36183423Smarius 37183423Smarius/* 38183423Smarius * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to 39183423Smarius * PCI 2.2 bridges 40183423Smarius */ 41183423Smarius 42183423Smarius#include "opt_ofw_pci.h" 43183423Smarius#include "opt_schizo.h" 44183423Smarius 45183423Smarius#include <sys/param.h> 46183423Smarius#include <sys/systm.h> 47183423Smarius#include <sys/bus.h> 48183423Smarius#include <sys/kernel.h> 49183423Smarius#include <sys/lock.h> 50183423Smarius#include <sys/malloc.h> 51183423Smarius#include <sys/module.h> 52183423Smarius#include <sys/mutex.h> 53183423Smarius#include <sys/pcpu.h> 54183423Smarius#include <sys/rman.h> 55208097Smarius#include <sys/sysctl.h> 56185133Smarius#include <sys/time.h> 57183423Smarius#include <sys/timetc.h> 58183423Smarius 59183423Smarius#include <dev/ofw/ofw_bus.h> 60183423Smarius#include <dev/ofw/ofw_pci.h> 61183423Smarius#include <dev/ofw/openfirm.h> 62183423Smarius 63183423Smarius#include <machine/bus.h> 64183423Smarius#include <machine/bus_common.h> 65183423Smarius#include <machine/bus_private.h> 66183423Smarius#include <machine/fsr.h> 67183423Smarius#include <machine/iommureg.h> 68183423Smarius#include <machine/iommuvar.h> 69183423Smarius#include <machine/resource.h> 70183423Smarius 71183423Smarius#include <dev/pci/pcireg.h> 72183423Smarius#include <dev/pci/pcivar.h> 73183423Smarius 74183423Smarius#include <sparc64/pci/ofw_pci.h> 75183423Smarius#include <sparc64/pci/schizoreg.h> 76183423Smarius#include <sparc64/pci/schizovar.h> 77183423Smarius 78183423Smarius#include "pcib_if.h" 79183423Smarius 80183423Smariusstatic const struct schizo_desc *schizo_get_desc(device_t); 81183423Smariusstatic void schizo_set_intr(struct schizo_softc *, u_int, u_int, 82183423Smarius driver_filter_t); 83185133Smariusstatic driver_filter_t schizo_dma_sync_stub; 84185133Smariusstatic driver_filter_t ichip_dma_sync_stub; 85183423Smariusstatic void schizo_intr_enable(void *); 86183423Smariusstatic void schizo_intr_disable(void *); 87183423Smariusstatic void schizo_intr_assign(void *); 88183423Smariusstatic void schizo_intr_clear(void *); 89185133Smariusstatic int schizo_intr_register(struct schizo_softc *sc, u_int ino); 90183423Smariusstatic int schizo_get_intrmap(struct schizo_softc *, u_int, 91183423Smarius bus_addr_t *, bus_addr_t *); 92183423Smariusstatic bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int); 93183423Smariusstatic timecounter_get_t schizo_get_timecount; 94183423Smarius 95183423Smarius/* Interrupt handlers */ 96183423Smariusstatic driver_filter_t schizo_pci_bus; 97183423Smariusstatic driver_filter_t schizo_ue; 98183423Smariusstatic driver_filter_t schizo_ce; 99183423Smariusstatic driver_filter_t schizo_host_bus; 100185133Smariusstatic driver_filter_t schizo_cdma; 101183423Smarius 102183423Smarius/* IOMMU support */ 103183423Smariusstatic void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 104183423Smarius 105183423Smarius/* 106183423Smarius * Methods 107183423Smarius */ 108183423Smariusstatic device_probe_t schizo_probe; 109183423Smariusstatic device_attach_t schizo_attach; 110183423Smariusstatic bus_read_ivar_t schizo_read_ivar; 111183423Smariusstatic bus_setup_intr_t schizo_setup_intr; 112183423Smariusstatic bus_teardown_intr_t schizo_teardown_intr; 113183423Smariusstatic bus_alloc_resource_t schizo_alloc_resource; 114183423Smariusstatic bus_activate_resource_t schizo_activate_resource; 115183423Smariusstatic bus_deactivate_resource_t schizo_deactivate_resource; 116183423Smariusstatic bus_release_resource_t schizo_release_resource; 117200948Smariusstatic bus_describe_intr_t schizo_describe_intr; 118183423Smariusstatic bus_get_dma_tag_t schizo_get_dma_tag; 119183423Smariusstatic pcib_maxslots_t schizo_maxslots; 120183423Smariusstatic pcib_read_config_t schizo_read_config; 121183423Smariusstatic pcib_write_config_t schizo_write_config; 122183423Smariusstatic pcib_route_interrupt_t schizo_route_interrupt; 123183423Smariusstatic ofw_bus_get_node_t schizo_get_node; 124183423Smarius 125183423Smariusstatic device_method_t schizo_methods[] = { 126183423Smarius /* Device interface */ 127183423Smarius DEVMETHOD(device_probe, schizo_probe), 128183423Smarius DEVMETHOD(device_attach, schizo_attach), 129183423Smarius DEVMETHOD(device_shutdown, bus_generic_shutdown), 130183423Smarius DEVMETHOD(device_suspend, bus_generic_suspend), 131183423Smarius DEVMETHOD(device_resume, bus_generic_resume), 132183423Smarius 133183423Smarius /* Bus interface */ 134183423Smarius DEVMETHOD(bus_print_child, bus_generic_print_child), 135183423Smarius DEVMETHOD(bus_read_ivar, schizo_read_ivar), 136183423Smarius DEVMETHOD(bus_setup_intr, schizo_setup_intr), 137183423Smarius DEVMETHOD(bus_teardown_intr, schizo_teardown_intr), 138183423Smarius DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 139183423Smarius DEVMETHOD(bus_activate_resource, schizo_activate_resource), 140183423Smarius DEVMETHOD(bus_deactivate_resource, schizo_deactivate_resource), 141183423Smarius DEVMETHOD(bus_release_resource, schizo_release_resource), 142200948Smarius DEVMETHOD(bus_describe_intr, schizo_describe_intr), 143183423Smarius DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 144183423Smarius 145183423Smarius /* pcib interface */ 146183423Smarius DEVMETHOD(pcib_maxslots, schizo_maxslots), 147183423Smarius DEVMETHOD(pcib_read_config, schizo_read_config), 148183423Smarius DEVMETHOD(pcib_write_config, schizo_write_config), 149183423Smarius DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 150183423Smarius 151183423Smarius /* ofw_bus interface */ 152183423Smarius DEVMETHOD(ofw_bus_get_node, schizo_get_node), 153183423Smarius 154190108Smarius KOBJMETHOD_END 155183423Smarius}; 156183423Smarius 157183423Smariusstatic devclass_t schizo_devclass; 158183423Smarius 159183423SmariusDEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 160183423Smarius sizeof(struct schizo_softc)); 161215349SmariusEARLY_DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0, 162215349Smarius BUS_PASS_BUS); 163183423Smarius 164183423Smariusstatic SLIST_HEAD(, schizo_softc) schizo_softcs = 165183423Smarius SLIST_HEAD_INITIALIZER(schizo_softcs); 166183423Smarius 167183423Smariusstatic const struct intr_controller schizo_ic = { 168183423Smarius schizo_intr_enable, 169183423Smarius schizo_intr_disable, 170183423Smarius schizo_intr_assign, 171183423Smarius schizo_intr_clear 172183423Smarius}; 173183423Smarius 174183423Smariusstruct schizo_icarg { 175183423Smarius struct schizo_softc *sica_sc; 176183423Smarius bus_addr_t sica_map; 177183423Smarius bus_addr_t sica_clr; 178183423Smarius}; 179183423Smarius 180185133Smariusstruct schizo_dma_sync { 181183423Smarius struct schizo_softc *sds_sc; 182183423Smarius driver_filter_t *sds_handler; 183183423Smarius void *sds_arg; 184183423Smarius void *sds_cookie; 185183423Smarius uint64_t sds_syncval; 186185133Smarius device_t sds_ppb; /* farest PCI-PCI bridge */ 187201199Smarius uint8_t sds_bus; /* bus of farest PCI dev. */ 188201199Smarius uint8_t sds_slot; /* slot of farest PCI dev. */ 189201199Smarius uint8_t sds_func; /* func. of farest PCI dev. */ 190183423Smarius}; 191183423Smarius 192183423Smarius#define SCHIZO_PERF_CNT_QLTY 100 193183423Smarius 194206018Smarius#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 195183423Smarius bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 196206018Smarius#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 197183423Smarius bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 198183423Smarius 199206018Smarius#define SCHIZO_PCI_READ_8(sc, offs) \ 200183423Smarius SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 201206018Smarius#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 202183423Smarius SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 203206018Smarius#define SCHIZO_CTRL_READ_8(sc, offs) \ 204183423Smarius SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 205206018Smarius#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 206183423Smarius SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 207206018Smarius#define SCHIZO_PCICFG_READ_8(sc, offs) \ 208183423Smarius SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 209206018Smarius#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 210183423Smarius SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 211206018Smarius#define SCHIZO_ICON_READ_8(sc, offs) \ 212183423Smarius SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 213206018Smarius#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 214183423Smarius SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 215183423Smarius 216183423Smariusstruct schizo_desc { 217183423Smarius const char *sd_string; 218183423Smarius int sd_mode; 219183423Smarius const char *sd_name; 220183423Smarius}; 221183423Smarius 222185133Smariusstatic const struct schizo_desc const schizo_compats[] = { 223183423Smarius { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 224183423Smarius { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 225183423Smarius { NULL, 0, NULL } 226183423Smarius}; 227183423Smarius 228183423Smariusstatic const struct schizo_desc * 229183423Smariusschizo_get_desc(device_t dev) 230183423Smarius{ 231183423Smarius const struct schizo_desc *desc; 232183423Smarius const char *compat; 233183423Smarius 234183423Smarius compat = ofw_bus_get_compat(dev); 235183423Smarius if (compat == NULL) 236183423Smarius return (NULL); 237183423Smarius for (desc = schizo_compats; desc->sd_string != NULL; desc++) 238183423Smarius if (strcmp(desc->sd_string, compat) == 0) 239183423Smarius return (desc); 240183423Smarius return (NULL); 241183423Smarius} 242183423Smarius 243183423Smariusstatic int 244183423Smariusschizo_probe(device_t dev) 245183423Smarius{ 246183423Smarius const char *dtype; 247183423Smarius 248183423Smarius dtype = ofw_bus_get_type(dev); 249197164Smarius if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 250183423Smarius schizo_get_desc(dev) != NULL) { 251183423Smarius device_set_desc(dev, "Sun Host-PCI bridge"); 252183423Smarius return (0); 253183423Smarius } 254183423Smarius return (ENXIO); 255183423Smarius} 256183423Smarius 257183423Smariusstatic int 258183423Smariusschizo_attach(device_t dev) 259183423Smarius{ 260183423Smarius struct ofw_pci_ranges *range; 261183423Smarius const struct schizo_desc *desc; 262183423Smarius struct schizo_softc *asc, *sc, *osc; 263183423Smarius struct timecounter *tc; 264183423Smarius uint64_t ino_bitmap, reg; 265183423Smarius phandle_t node; 266183423Smarius uint32_t prop, prop_array[2]; 267201199Smarius int i, j, mode, rid, tsbsize; 268183423Smarius 269183423Smarius sc = device_get_softc(dev); 270183423Smarius node = ofw_bus_get_node(dev); 271183423Smarius desc = schizo_get_desc(dev); 272183423Smarius mode = desc->sd_mode; 273183423Smarius 274183423Smarius sc->sc_dev = dev; 275183423Smarius sc->sc_node = node; 276183423Smarius sc->sc_mode = mode; 277185133Smarius sc->sc_flags = 0; 278183423Smarius 279183423Smarius /* 280183423Smarius * The Schizo has three register banks: 281183423Smarius * (0) per-PBM PCI configuration and status registers, but for bus B 282183423Smarius * shared with the UPA64s interrupt mapping register banks 283183423Smarius * (1) shared Schizo controller configuration and status registers 284183423Smarius * (2) per-PBM PCI configuration space 285183423Smarius * 286183423Smarius * The Tomatillo has four register banks: 287183423Smarius * (0) per-PBM PCI configuration and status registers 288183423Smarius * (1) per-PBM Tomatillo controller configuration registers, but on 289183423Smarius * machines having the `jbusppm' device shared with its Estar 290183423Smarius * register bank for bus A 291183423Smarius * (2) per-PBM PCI configuration space 292183423Smarius * (3) per-PBM interrupt concentrator registers 293183423Smarius */ 294183423Smarius sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 295183423Smarius 20) & 1; 296201199Smarius for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 297201199Smarius i++) { 298201199Smarius rid = i; 299201199Smarius sc->sc_mem_res[i] = bus_alloc_resource_any(dev, 300183423Smarius SYS_RES_MEMORY, &rid, 301183423Smarius (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 302201199Smarius i == STX_PCI) || i == STX_CTRL)) || 303183423Smarius (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 304201199Smarius i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 305201199Smarius if (sc->sc_mem_res[i] == NULL) 306183423Smarius panic("%s: could not allocate register bank %d", 307201199Smarius __func__, i); 308183423Smarius } 309183423Smarius 310183423Smarius /* 311183423Smarius * Match other Schizos that are already configured against 312183423Smarius * the controller base physical address. This will be the 313183423Smarius * same for a pair of devices that share register space. 314183423Smarius */ 315183423Smarius osc = NULL; 316183423Smarius SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 317183423Smarius if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 318183423Smarius rman_get_start(sc->sc_mem_res[STX_CTRL])) { 319183423Smarius /* Found partner. */ 320183423Smarius osc = asc; 321183423Smarius break; 322183423Smarius } 323183423Smarius } 324183423Smarius if (osc == NULL) { 325183423Smarius sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 326183423Smarius M_NOWAIT | M_ZERO); 327183423Smarius if (sc->sc_mtx == NULL) 328183423Smarius panic("%s: could not malloc mutex", __func__); 329183423Smarius mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 330183423Smarius } else { 331185133Smarius if (sc->sc_mode != SCHIZO_MODE_SCZ) 332185133Smarius panic("%s: no partner expected", __func__); 333183423Smarius if (mtx_initialized(osc->sc_mtx) == 0) 334183423Smarius panic("%s: mutex not initialized", __func__); 335183423Smarius sc->sc_mtx = osc->sc_mtx; 336183423Smarius } 337183423Smarius 338183423Smarius if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 339183423Smarius panic("%s: could not determine IGN", __func__); 340201199Smarius if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == 341201199Smarius -1) 342183423Smarius panic("%s: could not determine version", __func__); 343183423Smarius if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 344183423Smarius prop = 33000000; 345183423Smarius 346183423Smarius device_printf(dev, "%s, version %d, IGN %#x, bus %c, %dMHz\n", 347183423Smarius desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half, 348183423Smarius prop / 1000 / 1000); 349183423Smarius 350183423Smarius /* Set up the PCI interrupt retry timer. */ 351183423Smarius#ifdef SCHIZO_DEBUG 352183423Smarius device_printf(dev, "PCI IRT 0x%016llx\n", (unsigned long long) 353183423Smarius SCHIZO_PCI_READ_8(sc, STX_PCI_INTR_RETRY_TIM)); 354183423Smarius#endif 355183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_INTR_RETRY_TIM, 5); 356183423Smarius 357183423Smarius /* Set up the PCI control register. */ 358183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 359183423Smarius reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 360183423Smarius STX_PCI_CTRL_ERR_IEN | STX_PCI_CTRL_ARB_MASK; 361183423Smarius reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK); 362183423Smarius if (OF_getproplen(node, "no-bus-parking") < 0) 363183423Smarius reg |= STX_PCI_CTRL_ARB_PARK; 364183423Smarius if (mode == SCHIZO_MODE_TOM) { 365183423Smarius reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 366183423Smarius if (sc->sc_ver <= 1) /* revision <= 2.0 */ 367183423Smarius reg |= TOM_PCI_CTRL_DTO_IEN; 368183423Smarius else 369183423Smarius reg |= STX_PCI_CTRL_PTO; 370183423Smarius } 371183423Smarius#ifdef SCHIZO_DEBUG 372183423Smarius device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 373183423Smarius (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL), 374183423Smarius (unsigned long long)reg); 375183423Smarius#endif 376183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, reg); 377183423Smarius 378183423Smarius /* Set up the PCI diagnostic register. */ 379183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 380183423Smarius reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 381183423Smarius STX_PCI_DIAG_INTRSYNC_DIS); 382183423Smarius#ifdef SCHIZO_DEBUG 383183423Smarius device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 384183423Smarius (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG), 385183423Smarius (unsigned long long)reg); 386183423Smarius#endif 387183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg); 388183423Smarius 389183423Smarius /* 390208097Smarius * Enable DMA write parity error interrupts of version >= 7 (i.e. 391208097Smarius * revision >= 2.5) Schizo. 392208097Smarius */ 393208097Smarius if (mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 7) { 394208097Smarius reg = SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD); 395208097Smarius reg |= SX_PCI_CFG_ICD_DMAW_PERR_IEN; 396208097Smarius#ifdef SCHIZO_DEBUG 397208097Smarius device_printf(dev, "PCI CFG/ICD 0x%016llx -> 0x%016llx\n", 398208097Smarius (unsigned long long)SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD), 399208097Smarius (unsigned long long)reg); 400208097Smarius#endif 401208097Smarius SCHIZO_PCI_WRITE_8(sc, SX_PCI_CFG_ICD, reg); 402208097Smarius } 403208097Smarius 404208097Smarius /* 405183423Smarius * On Tomatillo clear the I/O prefetch lengths (workaround for a 406183423Smarius * Jalapeno bug). 407183423Smarius */ 408183423Smarius if (mode == SCHIZO_MODE_TOM) 409183423Smarius SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 410183423Smarius (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 411183423Smarius TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 412183423Smarius 413183423Smarius /* 414183423Smarius * Hunt through all the interrupt mapping regs and register 415186290Smarius * the interrupt controller for our interrupt vectors. We do 416186290Smarius * this early in order to be able to catch stray interrupts. 417186290Smarius * This is complicated by the fact that a pair of Schizo PBMs 418186290Smarius * shares one IGN. 419183423Smarius */ 420201199Smarius i = OF_getprop(node, "ino-bitmap", (void *)prop_array, 421183423Smarius sizeof(prop_array)); 422205254Smarius if (i != -1) 423205254Smarius ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 424205254Smarius else { 425205254Smarius /* 426205254Smarius * If the ino-bitmap property is missing, just provide the 427205254Smarius * default set of interrupts for this controller and let 428205254Smarius * schizo_setup_intr() take care of child interrupts. 429205254Smarius */ 430205254Smarius if (sc->sc_half == 0) 431205254Smarius ino_bitmap = (1ULL << STX_UE_INO) | 432205254Smarius (1ULL << STX_CE_INO) | 433205254Smarius (1ULL << STX_PCIERR_A_INO) | 434205254Smarius (1ULL << STX_BUS_INO); 435205254Smarius else 436205254Smarius ino_bitmap = 1ULL << STX_PCIERR_B_INO; 437205254Smarius } 438201199Smarius for (i = 0; i <= STX_MAX_INO; i++) { 439201199Smarius if ((ino_bitmap & (1ULL << i)) == 0) 440183423Smarius continue; 441201199Smarius if (i == STX_FB0_INO || i == STX_FB1_INO) 442183423Smarius /* Leave for upa(4). */ 443183423Smarius continue; 444201199Smarius j = schizo_intr_register(sc, i); 445201199Smarius if (j != 0) 446186290Smarius device_printf(dev, "could not register interrupt " 447201199Smarius "controller for INO %d (%d)\n", i, j); 448183423Smarius } 449183423Smarius 450183423Smarius /* 451183423Smarius * Setup Safari/JBus performance counter 0 in bus cycle counting 452183423Smarius * mode as timecounter. Unfortunately, this is broken with at 453183423Smarius * least the version 4 Tomatillos found in Fire V120 and Blade 454183423Smarius * 1500, which apparently actually count some different event at 455183423Smarius * ~0.5 and 3MHz respectively instead (also when running in full 456183423Smarius * power mode). Besides, one counter seems to be shared by a 457183423Smarius * "pair" of Tomatillos, too. 458183423Smarius */ 459183423Smarius if (sc->sc_half == 0) { 460183423Smarius SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_PERF, 461183423Smarius (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 462183423Smarius (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 463183423Smarius tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 464183423Smarius if (tc == NULL) 465183423Smarius panic("%s: could not malloc timecounter", __func__); 466183423Smarius tc->tc_get_timecount = schizo_get_timecount; 467183423Smarius tc->tc_poll_pps = NULL; 468183423Smarius tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 469183423Smarius if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 470183423Smarius sizeof(prop)) == -1) 471183423Smarius panic("%s: could not determine clock frequency", 472183423Smarius __func__); 473183423Smarius tc->tc_frequency = prop; 474183423Smarius tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 475183423Smarius if (mode == SCHIZO_MODE_SCZ) 476183423Smarius tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 477183423Smarius else 478183423Smarius tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 479183423Smarius tc->tc_priv = sc; 480183423Smarius tc_init(tc); 481183423Smarius } 482183423Smarius 483190108Smarius /* 484190108Smarius * Set up the IOMMU. Schizo, Tomatillo and XMITS all have 485190108Smarius * one per PBM. Schizo and XMITS additionally have a streaming 486190108Smarius * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's 487190108Smarius * affected by several errata and basically unusable though. 488190108Smarius */ 489201395Smarius sc->sc_is.is_flags = IOMMU_PRESERVE_PROM; 490183423Smarius sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 491190108Smarius sc->sc_is.is_sb[0] = sc->sc_is.is_sb[1] = 0; 492190108Smarius if (OF_getproplen(node, "no-streaming-cache") < 0 && 493190108Smarius !(sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver < 5)) 494183423Smarius sc->sc_is.is_sb[0] = STX_PCI_STRBUF; 495183423Smarius 496183423Smarius#define TSBCASE(x) \ 497183423Smarius case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 498183423Smarius tsbsize = (x); \ 499183423Smarius break; \ 500183423Smarius 501201199Smarius i = OF_getprop(node, "virtual-dma", (void *)prop_array, 502183423Smarius sizeof(prop_array)); 503201199Smarius if (i == -1 || i != sizeof(prop_array)) 504183423Smarius schizo_iommu_init(sc, 7, -1); 505183423Smarius else { 506183423Smarius switch (prop_array[1]) { 507183423Smarius TSBCASE(1); 508183423Smarius TSBCASE(2); 509183423Smarius TSBCASE(3); 510183423Smarius TSBCASE(4); 511183423Smarius TSBCASE(5); 512183423Smarius TSBCASE(6); 513183423Smarius TSBCASE(7); 514183423Smarius TSBCASE(8); 515183423Smarius default: 516183423Smarius panic("%s: unsupported DVMA size 0x%x", 517183423Smarius __func__, prop_array[1]); 518183423Smarius /* NOTREACHED */ 519183423Smarius } 520183423Smarius schizo_iommu_init(sc, tsbsize, prop_array[0]); 521183423Smarius } 522185133Smarius 523183423Smarius#undef TSBCASE 524183423Smarius 525183423Smarius /* Initialize memory and I/O rmans. */ 526183423Smarius sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 527183423Smarius sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 528183423Smarius if (rman_init(&sc->sc_pci_io_rman) != 0 || 529183423Smarius rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 530183423Smarius panic("%s: failed to set up I/O rman", __func__); 531183423Smarius sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 532183423Smarius sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 533183423Smarius if (rman_init(&sc->sc_pci_mem_rman) != 0 || 534183423Smarius rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 535183423Smarius panic("%s: failed to set up memory rman", __func__); 536183423Smarius 537201199Smarius i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range); 538183423Smarius /* 539183423Smarius * Make sure that the expected ranges are present. The 540183423Smarius * OFW_PCI_CS_MEM64 one is not currently used though. 541183423Smarius */ 542201199Smarius if (i != STX_NRANGE) 543183423Smarius panic("%s: unsupported number of ranges", __func__); 544183423Smarius /* 545183423Smarius * Find the addresses of the various bus spaces. 546183423Smarius * There should not be multiple ones of one kind. 547183423Smarius * The physical start addresses of the ranges are the configuration, 548183423Smarius * memory and I/O handles. 549183423Smarius */ 550201199Smarius for (i = 0; i < STX_NRANGE; i++) { 551201199Smarius j = OFW_PCI_RANGE_CS(&range[i]); 552201199Smarius if (sc->sc_pci_bh[j] != 0) 553201199Smarius panic("%s: duplicate range for space %d", 554201199Smarius __func__, j); 555201199Smarius sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]); 556183423Smarius } 557183423Smarius free(range, M_OFWPROP); 558183423Smarius 559183423Smarius /* Register the softc, this is needed for paired Schizos. */ 560183423Smarius SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 561183423Smarius 562183423Smarius /* Allocate our tags. */ 563183423Smarius sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 564183423Smarius sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 565183423Smarius sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 566183423Smarius if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 567183423Smarius sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr, 568183423Smarius 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 569183423Smarius panic("%s: bus_dma_tag_create failed", __func__); 570183423Smarius /* Customize the tag. */ 571183423Smarius sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 572183423Smarius sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 573183423Smarius 574183423Smarius /* 575183423Smarius * Get the bus range from the firmware. 576183423Smarius * NB: Tomatillos don't support PCI bus reenumeration. 577183423Smarius */ 578201199Smarius i = OF_getprop(node, "bus-range", (void *)prop_array, 579183423Smarius sizeof(prop_array)); 580201199Smarius if (i == -1) 581183423Smarius panic("%s: could not get bus-range", __func__); 582201199Smarius if (i != sizeof(prop_array)) 583201199Smarius panic("%s: broken bus-range (%d)", __func__, i); 584201395Smarius sc->sc_pci_secbus = prop_array[0]; 585201395Smarius sc->sc_pci_subbus = prop_array[1]; 586183423Smarius if (bootverbose) 587183423Smarius device_printf(dev, "bus range %u to %u; PCI bus %d\n", 588201395Smarius sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus); 589183423Smarius 590183423Smarius /* Clear any pending PCI error bits. */ 591183423Smarius PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 592183423Smarius PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 593183423Smarius STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 594183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, 595183423Smarius SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 596183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, 597183423Smarius SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 598183423Smarius 599183423Smarius /* 600183423Smarius * Establish handlers for interesting interrupts... 601183423Smarius * Someone at Sun clearly was smoking crack; with Schizos PCI 602183423Smarius * bus error interrupts for one PBM can be routed to the other 603183423Smarius * PBM though we obviously need to use the softc of the former 604183423Smarius * as the argument for the interrupt handler and the softc of 605183423Smarius * the latter as the argument for the interrupt controller. 606183423Smarius */ 607183423Smarius if (sc->sc_half == 0) { 608183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 609183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 610183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 611183423Smarius sica_sc == osc)) 612183423Smarius /* 613183423Smarius * We are the driver for PBM A and either also 614183423Smarius * registered the interrupt controller for us or 615183423Smarius * the driver for PBM B has probed first and 616183423Smarius * registered it for us. 617183423Smarius */ 618183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 619183423Smarius schizo_pci_bus); 620183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 621183423Smarius osc != NULL) 622183423Smarius /* 623183423Smarius * We are the driver for PBM A but registered 624183423Smarius * the interrupt controller for PBM B, i.e. the 625183423Smarius * driver for PBM B attached first but couldn't 626183423Smarius * set up a handler for PBM B. 627183423Smarius */ 628183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 629183423Smarius schizo_pci_bus); 630183423Smarius } else { 631183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 632183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 633183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 634183423Smarius sica_sc == osc)) 635183423Smarius /* 636183423Smarius * We are the driver for PBM B and either also 637183423Smarius * registered the interrupt controller for us or 638183423Smarius * the driver for PBM A has probed first and 639183423Smarius * registered it for us. 640183423Smarius */ 641183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 642183423Smarius schizo_pci_bus); 643183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 644183423Smarius osc != NULL) 645183423Smarius /* 646183423Smarius * We are the driver for PBM B but registered 647183423Smarius * the interrupt controller for PBM A, i.e. the 648183423Smarius * driver for PBM A attached first but couldn't 649183423Smarius * set up a handler for PBM A. 650183423Smarius */ 651183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 652183423Smarius schizo_pci_bus); 653183423Smarius } 654183423Smarius if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 655183423Smarius schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 656183423Smarius if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 657183423Smarius schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 658183423Smarius if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 659183423Smarius schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 660183423Smarius 661183423Smarius /* 662185133Smarius * According to the Schizo Errata I-13, consistent DMA flushing/ 663185133Smarius * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 664201126Smarius * so we can't use it and need to live with the consequences. With 665201126Smarius * Schizo version >= 5, CDMA flushing/syncing is usable but requires 666201126Smarius * the workaround described in Schizo Errata I-23. With Tomatillo 667201126Smarius * and XMITS, CDMA flushing/syncing works as expected, Tomatillo 668201126Smarius * version <= 4 (i.e. revision <= 2.3) bridges additionally require 669201126Smarius * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though. 670185133Smarius */ 671185133Smarius if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 672201199Smarius sc->sc_mode == SCHIZO_MODE_TOM || 673201199Smarius sc->sc_mode == SCHIZO_MODE_XMS) { 674185133Smarius sc->sc_flags |= SCHIZO_FLAGS_CDMA; 675185133Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ) { 676185133Smarius sc->sc_cdma_state = SCHIZO_CDMA_STATE_DONE; 677201126Smarius /* 678201126Smarius * Some firmware versions include the CDMA interrupt 679201126Smarius * at RID 4 but most don't. With the latter we add 680201126Smarius * it ourselves at the spare RID 5. 681201126Smarius */ 682201199Smarius i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ, 683201126Smarius 4)); 684201199Smarius if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) { 685201199Smarius (void)schizo_get_intrmap(sc, i, NULL, 686201126Smarius &sc->sc_cdma_clr); 687201199Smarius schizo_set_intr(sc, 4, i, schizo_cdma); 688201126Smarius } else { 689201199Smarius i = STX_CDMA_A_INO + sc->sc_half; 690201126Smarius if (bus_set_resource(dev, SYS_RES_IRQ, 5, 691201199Smarius INTMAP_VEC(sc->sc_ign, i), 1) != 0) 692201126Smarius panic("%s: failed to add CDMA " 693201126Smarius "interrupt", __func__); 694201199Smarius j = schizo_intr_register(sc, i); 695201199Smarius if (j != 0) 696201126Smarius panic("%s: could not register " 697201126Smarius "interrupt controller for CDMA " 698201199Smarius "(%d)", __func__, j); 699201199Smarius (void)schizo_get_intrmap(sc, i, NULL, 700201126Smarius &sc->sc_cdma_clr); 701201199Smarius schizo_set_intr(sc, 5, i, schizo_cdma); 702201126Smarius } 703185133Smarius } 704185133Smarius if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 705185133Smarius sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 706185133Smarius } 707185133Smarius 708185133Smarius /* 709183423Smarius * Set the latency timer register as this isn't always done by the 710183423Smarius * firmware. 711183423Smarius */ 712183423Smarius PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 713183423Smarius PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 714183423Smarius 715183423Smarius ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 716183423Smarius 717208097Smarius#define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \ 718208097Smarius SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \ 719208097Smarius SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, \ 720208097Smarius (name), CTLFLAG_RD, (arg), 0, (desc)) 721208097Smarius 722208097Smarius SCHIZO_SYSCTL_ADD_UINT("dma_ce", &sc->sc_stats_dma_ce, 723208097Smarius "DMA correctable errors"); 724208097Smarius SCHIZO_SYSCTL_ADD_UINT("pci_non_fatal", &sc->sc_stats_pci_non_fatal, 725208097Smarius "PCI bus non-fatal errors"); 726208097Smarius 727208097Smarius#undef SCHIZO_SYSCTL_ADD_UINT 728208097Smarius 729183423Smarius device_add_child(dev, "pci", -1); 730183423Smarius return (bus_generic_attach(dev)); 731183423Smarius} 732183423Smarius 733183423Smariusstatic void 734183423Smariusschizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 735183423Smarius driver_filter_t handler) 736183423Smarius{ 737183423Smarius u_long vec; 738183423Smarius int rid; 739183423Smarius 740183423Smarius rid = index; 741201199Smarius sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 742201199Smarius SYS_RES_IRQ, &rid, RF_ACTIVE); 743183423Smarius if (sc->sc_irq_res[index] == NULL || 744201199Smarius INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino || 745201199Smarius INTIGN(vec) != sc->sc_ign || 746183423Smarius intr_vectors[vec].iv_ic != &schizo_ic || 747185133Smarius bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 748216961Smarius INTR_TYPE_MISC | INTR_BRIDGE, handler, NULL, sc, 749185133Smarius &sc->sc_ihand[index]) != 0) 750183423Smarius panic("%s: failed to set up interrupt %d", __func__, index); 751183423Smarius} 752183423Smarius 753183423Smariusstatic int 754185133Smariusschizo_intr_register(struct schizo_softc *sc, u_int ino) 755185133Smarius{ 756185133Smarius struct schizo_icarg *sica; 757185133Smarius bus_addr_t intrclr, intrmap; 758185133Smarius int error; 759185133Smarius 760185133Smarius if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 761185133Smarius return (ENXIO); 762185133Smarius sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 763185133Smarius if (sica == NULL) 764185133Smarius return (ENOMEM); 765185133Smarius sica->sica_sc = sc; 766185133Smarius sica->sica_map = intrmap; 767185133Smarius sica->sica_clr = intrclr; 768185133Smarius#ifdef SCHIZO_DEBUG 769185133Smarius device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 770185133Smarius ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 771185133Smarius (u_long)intrclr); 772185133Smarius#endif 773185133Smarius error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 774185133Smarius &schizo_ic, sica)); 775185133Smarius if (error != 0) 776185133Smarius free(sica, M_DEVBUF); 777185133Smarius return (error); 778185133Smarius} 779185133Smarius 780185133Smariusstatic int 781201199Smariusschizo_get_intrmap(struct schizo_softc *sc, u_int ino, 782201199Smarius bus_addr_t *intrmapptr, bus_addr_t *intrclrptr) 783183423Smarius{ 784183423Smarius bus_addr_t intrclr, intrmap; 785183423Smarius uint64_t mr; 786183423Smarius 787183423Smarius /* 788183423Smarius * XXX we only look for INOs rather than INRs since the firmware 789183423Smarius * may not provide the IGN and the IGN is constant for all devices 790183423Smarius * on that PCI controller. 791183423Smarius */ 792183423Smarius 793183423Smarius if (ino > STX_MAX_INO) { 794183423Smarius device_printf(sc->sc_dev, "out of range INO %d requested\n", 795183423Smarius ino); 796183423Smarius return (0); 797183423Smarius } 798183423Smarius 799183423Smarius intrmap = STX_PCI_IMAP_BASE + (ino << 3); 800183423Smarius intrclr = STX_PCI_ICLR_BASE + (ino << 3); 801183423Smarius mr = SCHIZO_PCI_READ_8(sc, intrmap); 802183423Smarius if (INTINO(mr) != ino) { 803183423Smarius device_printf(sc->sc_dev, 804183423Smarius "interrupt map entry does not match INO (%d != %d)\n", 805183423Smarius (int)INTINO(mr), ino); 806183423Smarius return (0); 807183423Smarius } 808183423Smarius 809183423Smarius if (intrmapptr != NULL) 810183423Smarius *intrmapptr = intrmap; 811183423Smarius if (intrclrptr != NULL) 812183423Smarius *intrclrptr = intrclr; 813183423Smarius return (1); 814183423Smarius} 815183423Smarius 816183423Smarius/* 817183423Smarius * Interrupt handlers 818183423Smarius */ 819183423Smariusstatic int 820183423Smariusschizo_pci_bus(void *arg) 821183423Smarius{ 822183423Smarius struct schizo_softc *sc = arg; 823183423Smarius uint64_t afar, afsr, csr, iommu; 824183423Smarius uint32_t status; 825208097Smarius u_int fatal; 826183423Smarius 827208097Smarius fatal = 0; 828208097Smarius 829208097Smarius mtx_lock_spin(sc->sc_mtx); 830208097Smarius 831183423Smarius afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 832183423Smarius afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 833183423Smarius csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 834183423Smarius iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 835183423Smarius status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 836183423Smarius STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 837183423Smarius 838208097Smarius /* 839208097Smarius * IOMMU errors are only fatal on Tomatillo and there also only if 840208097Smarius * target abort was not signaled. 841208097Smarius */ 842208097Smarius if ((csr & STX_PCI_CTRL_MMU_ERR) != 0 && 843208097Smarius (iommu & TOM_PCI_IOMMU_ERR) != 0 && 844208097Smarius ((status & PCIM_STATUS_STABORT) == 0 || 845208097Smarius ((iommu & TOM_PCI_IOMMU_ERRMASK) != TOM_PCI_IOMMU_INVALID_ERR && 846208097Smarius (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) == 0 && 847208097Smarius (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) == 0))) 848208097Smarius fatal = 1; 849208097Smarius else if ((status & PCIM_STATUS_STABORT) != 0) 850208097Smarius fatal = 1; 851208097Smarius if ((status & (PCIM_STATUS_PERR | PCIM_STATUS_SERR | 852208097Smarius PCIM_STATUS_RMABORT | PCIM_STATUS_RTABORT | 853212378Sjhb PCIM_STATUS_MDPERR)) != 0 || 854208097Smarius (csr & (SCZ_PCI_CTRL_BUS_UNUS | TOM_PCI_CTRL_DTO_ERR | 855208097Smarius STX_PCI_CTRL_TTO_ERR | STX_PCI_CTRL_RTRY_ERR | 856208097Smarius SCZ_PCI_CTRL_SBH_ERR | STX_PCI_CTRL_SERR)) != 0 || 857208097Smarius (afsr & (STX_PCI_AFSR_P_MA | STX_PCI_AFSR_P_TA | 858208097Smarius STX_PCI_AFSR_P_RTRY | STX_PCI_AFSR_P_PERR | STX_PCI_AFSR_P_TTO | 859208097Smarius STX_PCI_AFSR_P_UNUS)) != 0) 860208097Smarius fatal = 1; 861208097Smarius if (fatal == 0) 862208097Smarius sc->sc_stats_pci_non_fatal++; 863183423Smarius 864208097Smarius device_printf(sc->sc_dev, "PCI bus %c error AFAR %#llx AFSR %#llx " 865208097Smarius "PCI CSR %#llx IOMMU %#llx STATUS %#llx\n", 'A' + sc->sc_half, 866208097Smarius (unsigned long long)afar, (unsigned long long)afsr, 867208097Smarius (unsigned long long)csr, (unsigned long long)iommu, 868208097Smarius (unsigned long long)status); 869183423Smarius 870183423Smarius /* Clear the error bits that we caught. */ 871183423Smarius PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 872183423Smarius STX_CS_FUNC, PCIR_STATUS, status, 2); 873183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 874183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 875208097Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 876208097Smarius 877208097Smarius mtx_unlock_spin(sc->sc_mtx); 878208097Smarius 879208097Smarius if (fatal != 0) 880208097Smarius panic("%s: fatal PCI bus error", 881208097Smarius device_get_nameunit(sc->sc_dev)); 882183423Smarius return (FILTER_HANDLED); 883183423Smarius} 884183423Smarius 885183423Smariusstatic int 886183423Smariusschizo_ue(void *arg) 887183423Smarius{ 888183423Smarius struct schizo_softc *sc = arg; 889183423Smarius uint64_t afar, afsr; 890183423Smarius int i; 891183423Smarius 892183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 893183423Smarius for (i = 0; i < 1000; i++) 894183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 895183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 896183423Smarius break; 897183423Smarius panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 898206020Smarius device_get_nameunit(sc->sc_dev), (unsigned long long)afar, 899183423Smarius (unsigned long long)afsr); 900183423Smarius return (FILTER_HANDLED); 901183423Smarius} 902183423Smarius 903183423Smariusstatic int 904183423Smariusschizo_ce(void *arg) 905183423Smarius{ 906183423Smarius struct schizo_softc *sc = arg; 907183423Smarius uint64_t afar, afsr; 908183423Smarius int i; 909183423Smarius 910183423Smarius mtx_lock_spin(sc->sc_mtx); 911208097Smarius 912183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 913183423Smarius for (i = 0; i < 1000; i++) 914183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 915183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 916183423Smarius break; 917208097Smarius sc->sc_stats_dma_ce++; 918183423Smarius device_printf(sc->sc_dev, 919183423Smarius "correctable DMA error AFAR %#llx AFSR %#llx\n", 920183423Smarius (unsigned long long)afar, (unsigned long long)afsr); 921208097Smarius 922183423Smarius /* Clear the error bits that we caught. */ 923183423Smarius SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 924208097Smarius 925183423Smarius mtx_unlock_spin(sc->sc_mtx); 926208097Smarius 927183423Smarius return (FILTER_HANDLED); 928183423Smarius} 929183423Smarius 930183423Smariusstatic int 931183423Smariusschizo_host_bus(void *arg) 932183423Smarius{ 933183423Smarius struct schizo_softc *sc = arg; 934183423Smarius uint64_t errlog; 935183423Smarius 936183423Smarius errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 937206020Smarius panic("%s: %s error %#llx", device_get_nameunit(sc->sc_dev), 938183423Smarius sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 939183423Smarius (unsigned long long)errlog); 940183423Smarius return (FILTER_HANDLED); 941183423Smarius} 942183423Smarius 943185133Smariusstatic int 944185133Smariusschizo_cdma(void *arg) 945185133Smarius{ 946185133Smarius struct schizo_softc *sc = arg; 947185133Smarius 948185133Smarius atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE); 949185133Smarius return (FILTER_HANDLED); 950185133Smarius} 951185133Smarius 952183423Smariusstatic void 953183423Smariusschizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 954183423Smarius{ 955183423Smarius 956183423Smarius /* Punch in our copies. */ 957183423Smarius sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 958183423Smarius sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 959183423Smarius sc->sc_is.is_iommu = STX_PCI_IOMMU; 960183423Smarius sc->sc_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 961183423Smarius sc->sc_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 962183423Smarius sc->sc_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 963183423Smarius sc->sc_is.is_dva = STX_PCI_IOMMU_SVADIAG; 964183423Smarius sc->sc_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 965183423Smarius 966183423Smarius iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, tsbsize, 967183423Smarius dvmabase, 0); 968183423Smarius} 969183423Smarius 970183423Smariusstatic int 971183423Smariusschizo_maxslots(device_t dev) 972183423Smarius{ 973183423Smarius struct schizo_softc *sc; 974183423Smarius 975183423Smarius sc = device_get_softc(dev); 976183423Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ) 977183423Smarius return (sc->sc_half == 0 ? 4 : 6); 978183423Smarius 979183423Smarius /* XXX: is this correct? */ 980183423Smarius return (PCI_SLOTMAX); 981183423Smarius} 982183423Smarius 983183423Smariusstatic uint32_t 984183423Smariusschizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 985183423Smarius int width) 986183423Smarius{ 987183423Smarius struct schizo_softc *sc; 988183423Smarius bus_space_handle_t bh; 989183423Smarius u_long offset = 0; 990183423Smarius uint32_t r, wrd; 991183423Smarius int i; 992183423Smarius uint16_t shrt; 993183423Smarius uint8_t byte; 994183423Smarius 995183423Smarius sc = device_get_softc(dev); 996201395Smarius if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 997201395Smarius slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 998201395Smarius return (-1); 999183423Smarius 1000183423Smarius /* 1001183423Smarius * The Schizo bridges contain a dupe of their header at 0x80. 1002183423Smarius */ 1003183423Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 1004183423Smarius slot == STX_CS_DEVICE && func == STX_CS_FUNC && 1005183423Smarius reg + width > 0x80) 1006183423Smarius return (0); 1007183423Smarius 1008183423Smarius offset = STX_CONF_OFF(bus, slot, func, reg); 1009183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1010183423Smarius switch (width) { 1011183423Smarius case 1: 1012183423Smarius i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 1013183423Smarius r = byte; 1014183423Smarius break; 1015183423Smarius case 2: 1016183423Smarius i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 1017183423Smarius r = shrt; 1018183423Smarius break; 1019183423Smarius case 4: 1020183423Smarius i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 1021183423Smarius r = wrd; 1022183423Smarius break; 1023183423Smarius default: 1024183423Smarius panic("%s: bad width", __func__); 1025183423Smarius /* NOTREACHED */ 1026183423Smarius } 1027183423Smarius 1028183423Smarius if (i) { 1029183423Smarius#ifdef SCHIZO_DEBUG 1030183423Smarius printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 1031183423Smarius __func__, bus, slot, func, reg); 1032183423Smarius#endif 1033183423Smarius r = -1; 1034183423Smarius } 1035183423Smarius return (r); 1036183423Smarius} 1037183423Smarius 1038183423Smariusstatic void 1039201199Smariusschizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1040201199Smarius u_int reg, uint32_t val, int width) 1041183423Smarius{ 1042183423Smarius struct schizo_softc *sc; 1043183423Smarius bus_space_handle_t bh; 1044183423Smarius u_long offset = 0; 1045183423Smarius 1046183423Smarius sc = device_get_softc(dev); 1047201395Smarius if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1048201395Smarius slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1049201395Smarius return; 1050201395Smarius 1051183423Smarius offset = STX_CONF_OFF(bus, slot, func, reg); 1052183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1053183423Smarius switch (width) { 1054183423Smarius case 1: 1055183423Smarius bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1056183423Smarius break; 1057183423Smarius case 2: 1058183423Smarius bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1059183423Smarius break; 1060183423Smarius case 4: 1061183423Smarius bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1062183423Smarius break; 1063183423Smarius default: 1064183423Smarius panic("%s: bad width", __func__); 1065183423Smarius /* NOTREACHED */ 1066183423Smarius } 1067183423Smarius} 1068183423Smarius 1069183423Smariusstatic int 1070183423Smariusschizo_route_interrupt(device_t bridge, device_t dev, int pin) 1071183423Smarius{ 1072183423Smarius struct schizo_softc *sc; 1073183423Smarius struct ofw_pci_register reg; 1074183423Smarius ofw_pci_intr_t pintr, mintr; 1075183423Smarius uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 1076183423Smarius 1077183423Smarius sc = device_get_softc(bridge); 1078183423Smarius pintr = pin; 1079201199Smarius if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1080201199Smarius ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), 1081209298Snwhitehorn NULL, maskbuf)) 1082183423Smarius return (mintr); 1083183423Smarius 1084183423Smarius device_printf(bridge, "could not route pin %d for device %d.%d\n", 1085183423Smarius pin, pci_get_slot(dev), pci_get_function(dev)); 1086183423Smarius return (PCI_INVALID_IRQ); 1087183423Smarius} 1088183423Smarius 1089183423Smariusstatic int 1090183423Smariusschizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1091183423Smarius{ 1092183423Smarius struct schizo_softc *sc; 1093183423Smarius 1094183423Smarius sc = device_get_softc(dev); 1095183423Smarius switch (which) { 1096183423Smarius case PCIB_IVAR_DOMAIN: 1097183423Smarius *result = device_get_unit(dev); 1098183423Smarius return (0); 1099183423Smarius case PCIB_IVAR_BUS: 1100183423Smarius *result = sc->sc_pci_secbus; 1101183423Smarius return (0); 1102183423Smarius } 1103183423Smarius return (ENOENT); 1104183423Smarius} 1105183423Smarius 1106185133Smariusstatic int 1107185133Smariusschizo_dma_sync_stub(void *arg) 1108185133Smarius{ 1109185133Smarius struct timeval cur, end; 1110185133Smarius struct schizo_dma_sync *sds = arg; 1111185133Smarius struct schizo_softc *sc = sds->sds_sc; 1112185133Smarius uint32_t state; 1113185133Smarius 1114185133Smarius (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1115185133Smarius sds->sds_func, PCIR_VENDOR, 2); 1116201199Smarius for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, 1117201199Smarius SCHIZO_CDMA_STATE_DONE, SCHIZO_CDMA_STATE_PENDING) == 0;) 1118185133Smarius ; 1119206018Smarius SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, INTCLR_RECEIVED); 1120185133Smarius microuptime(&cur); 1121185133Smarius end.tv_sec = 1; 1122185133Smarius end.tv_usec = 0; 1123185133Smarius timevaladd(&end, &cur); 1124185133Smarius for (; (state = atomic_load_32(&sc->sc_cdma_state)) != 1125185133Smarius SCHIZO_CDMA_STATE_DONE && timevalcmp(&cur, &end, <=);) 1126185133Smarius microuptime(&cur); 1127185133Smarius if (state != SCHIZO_CDMA_STATE_DONE) 1128185133Smarius panic("%s: DMA does not sync", __func__); 1129185133Smarius return (sds->sds_handler(sds->sds_arg)); 1130185133Smarius} 1131185133Smarius 1132183423Smarius#define VIS_BLOCKSIZE 64 1133183423Smarius 1134183423Smariusstatic int 1135185133Smariusichip_dma_sync_stub(void *arg) 1136183423Smarius{ 1137183423Smarius static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 1138185133Smarius struct timeval cur, end; 1139185133Smarius struct schizo_dma_sync *sds = arg; 1140183423Smarius struct schizo_softc *sc = sds->sds_sc; 1141184428Smarius register_t reg, s; 1142183423Smarius 1143185133Smarius (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1144185133Smarius sds->sds_func, PCIR_VENDOR, 2); 1145184428Smarius SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, sds->sds_syncval); 1146185133Smarius microuptime(&cur); 1147185133Smarius end.tv_sec = 1; 1148185133Smarius end.tv_usec = 0; 1149185133Smarius timevaladd(&end, &cur); 1150185133Smarius for (; ((reg = SCHIZO_PCI_READ_8(sc, TOMXMS_PCI_DMA_SYNC_PEND)) & 1151185133Smarius sds->sds_syncval) != 0 && timevalcmp(&cur, &end, <=);) 1152185133Smarius microuptime(&cur); 1153185133Smarius if ((reg & sds->sds_syncval) != 0) 1154185133Smarius panic("%s: DMA does not sync", __func__); 1155183423Smarius 1156185133Smarius if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1157184428Smarius s = intr_disable(); 1158183423Smarius reg = rd(fprs); 1159183423Smarius wr(fprs, reg | FPRS_FEF, 0); 1160184428Smarius __asm __volatile("stda %%f0, [%0] %1" 1161183423Smarius : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 1162184428Smarius membar(Sync); 1163183423Smarius wr(fprs, reg, 0); 1164184428Smarius intr_restore(s); 1165183423Smarius } 1166183423Smarius return (sds->sds_handler(sds->sds_arg)); 1167183423Smarius} 1168183423Smarius 1169183423Smariusstatic void 1170183423Smariusschizo_intr_enable(void *arg) 1171183423Smarius{ 1172183423Smarius struct intr_vector *iv = arg; 1173183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1174183423Smarius 1175183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1176183423Smarius INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1177183423Smarius} 1178183423Smarius 1179183423Smariusstatic void 1180183423Smariusschizo_intr_disable(void *arg) 1181183423Smarius{ 1182183423Smarius struct intr_vector *iv = arg; 1183183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1184183423Smarius 1185183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1186183423Smarius} 1187183423Smarius 1188183423Smariusstatic void 1189183423Smariusschizo_intr_assign(void *arg) 1190183423Smarius{ 1191183423Smarius struct intr_vector *iv = arg; 1192183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1193183423Smarius 1194183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1195183423Smarius SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1196183423Smarius} 1197183423Smarius 1198183423Smariusstatic void 1199183423Smariusschizo_intr_clear(void *arg) 1200183423Smarius{ 1201183423Smarius struct intr_vector *iv = arg; 1202183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1203183423Smarius 1204206018Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE); 1205183423Smarius} 1206183423Smarius 1207183423Smariusstatic int 1208183423Smariusschizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1209183423Smarius int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1210183423Smarius void **cookiep) 1211183423Smarius{ 1212185133Smarius devclass_t pci_devclass; 1213185133Smarius device_t cdev, pdev, pcidev; 1214185133Smarius struct schizo_dma_sync *sds; 1215183423Smarius struct schizo_softc *sc; 1216183423Smarius u_long vec; 1217185133Smarius int error, found; 1218183423Smarius 1219183423Smarius sc = device_get_softc(dev); 1220183423Smarius /* 1221186290Smarius * Make sure the vector is fully specified. 1222183423Smarius */ 1223183423Smarius vec = rman_get_start(ires); 1224186290Smarius if (INTIGN(vec) != sc->sc_ign) { 1225183423Smarius device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1226183423Smarius return (EINVAL); 1227183423Smarius } 1228183423Smarius 1229186290Smarius if (intr_vectors[vec].iv_ic == &schizo_ic) { 1230186290Smarius /* 1231186290Smarius * Ensure we use the right softc in case the interrupt 1232186290Smarius * is routed to our companion PBM for some odd reason. 1233186290Smarius */ 1234186290Smarius sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 1235186290Smarius sica_sc; 1236186290Smarius } else if (intr_vectors[vec].iv_ic == NULL) { 1237186290Smarius /* 1238186290Smarius * Work around broken firmware which misses entries in 1239186290Smarius * the ino-bitmap. 1240186290Smarius */ 1241186290Smarius error = schizo_intr_register(sc, INTINO(vec)); 1242186290Smarius if (error != 0) { 1243186290Smarius device_printf(dev, "could not register interrupt " 1244186290Smarius "controller for vector 0x%lx (%d)\n", vec, error); 1245186290Smarius return (error); 1246186290Smarius } 1247190108Smarius if (bootverbose) 1248190108Smarius device_printf(dev, "belatedly registered as " 1249190108Smarius "interrupt controller for vector 0x%lx\n", vec); 1250186290Smarius } else { 1251186290Smarius device_printf(dev, 1252186290Smarius "invalid interrupt controller for vector 0x%lx\n", vec); 1253186290Smarius return (EINVAL); 1254186290Smarius } 1255186290Smarius 1256183423Smarius /* 1257185133Smarius * Install a a wrapper for CDMA flushing/syncing for devices 1258185133Smarius * behind PCI-PCI bridges if possible. 1259183423Smarius */ 1260185133Smarius pcidev = NULL; 1261185133Smarius found = 0; 1262185133Smarius pci_devclass = devclass_find("pci"); 1263185133Smarius for (cdev = child; cdev != dev; cdev = pdev) { 1264185133Smarius pdev = device_get_parent(cdev); 1265185133Smarius if (pcidev == NULL) { 1266185133Smarius if (device_get_devclass(pdev) != pci_devclass) 1267185133Smarius continue; 1268185133Smarius pcidev = cdev; 1269185133Smarius continue; 1270185133Smarius } 1271185133Smarius if (pci_get_class(cdev) == PCIC_BRIDGE && 1272185133Smarius pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1273185133Smarius found = 1; 1274185133Smarius } 1275185133Smarius if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1276183423Smarius sds = malloc(sizeof(*sds), M_DEVBUF, M_NOWAIT | M_ZERO); 1277183423Smarius if (sds == NULL) 1278183423Smarius return (ENOMEM); 1279185133Smarius if (found != 0 && pcidev != NULL) { 1280185133Smarius sds->sds_sc = sc; 1281185133Smarius sds->sds_arg = arg; 1282185133Smarius sds->sds_ppb = 1283185133Smarius device_get_parent(device_get_parent(pcidev)); 1284185133Smarius sds->sds_bus = pci_get_bus(pcidev); 1285185133Smarius sds->sds_slot = pci_get_slot(pcidev); 1286185133Smarius sds->sds_func = pci_get_function(pcidev); 1287185133Smarius sds->sds_syncval = 1ULL << INTINO(vec); 1288185133Smarius if (bootverbose) 1289185133Smarius device_printf(dev, "installed DMA sync " 1290185133Smarius "wrapper for device %d.%d on bus %d\n", 1291185133Smarius sds->sds_slot, sds->sds_func, 1292185133Smarius sds->sds_bus); 1293185133Smarius 1294185133Smarius#define DMA_SYNC_STUB \ 1295185133Smarius (sc->sc_mode == SCHIZO_MODE_SCZ ? schizo_dma_sync_stub : \ 1296185133Smarius ichip_dma_sync_stub) 1297185133Smarius 1298185133Smarius if (intr == NULL) { 1299185133Smarius sds->sds_handler = filt; 1300185133Smarius error = bus_generic_setup_intr(dev, child, 1301185133Smarius ires, flags, DMA_SYNC_STUB, intr, sds, 1302185133Smarius cookiep); 1303185133Smarius } else { 1304185133Smarius sds->sds_handler = (driver_filter_t *)intr; 1305185133Smarius error = bus_generic_setup_intr(dev, child, 1306185133Smarius ires, flags, filt, (driver_intr_t *) 1307185133Smarius DMA_SYNC_STUB, sds, cookiep); 1308185133Smarius } 1309185133Smarius 1310185133Smarius#undef DMA_SYNC_STUB 1311185133Smarius 1312185133Smarius } else 1313183423Smarius error = bus_generic_setup_intr(dev, child, ires, 1314185133Smarius flags, filt, intr, arg, cookiep); 1315183423Smarius if (error != 0) { 1316183423Smarius free(sds, M_DEVBUF); 1317183423Smarius return (error); 1318183423Smarius } 1319183423Smarius sds->sds_cookie = *cookiep; 1320183423Smarius *cookiep = sds; 1321183423Smarius return (error); 1322185133Smarius } else if (found != 0) 1323185133Smarius device_printf(dev, "WARNING: using devices behind PCI-PCI " 1324186290Smarius "bridges may cause data corruption\n"); 1325183423Smarius return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1326183423Smarius arg, cookiep)); 1327183423Smarius} 1328183423Smarius 1329183423Smariusstatic int 1330183423Smariusschizo_teardown_intr(device_t dev, device_t child, struct resource *vec, 1331183423Smarius void *cookie) 1332183423Smarius{ 1333185133Smarius struct schizo_dma_sync *sds; 1334183423Smarius struct schizo_softc *sc; 1335183423Smarius int error; 1336183423Smarius 1337183423Smarius sc = device_get_softc(dev); 1338185133Smarius if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1339183423Smarius sds = cookie; 1340183423Smarius error = bus_generic_teardown_intr(dev, child, vec, 1341183423Smarius sds->sds_cookie); 1342183423Smarius if (error == 0) 1343183423Smarius free(sds, M_DEVBUF); 1344183423Smarius return (error); 1345183423Smarius } 1346183423Smarius return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1347183423Smarius} 1348183423Smarius 1349200948Smariusstatic int 1350200948Smariusschizo_describe_intr(device_t dev, device_t child, struct resource *vec, 1351200948Smarius void *cookie, const char *descr) 1352200948Smarius{ 1353200948Smarius struct schizo_softc *sc; 1354200948Smarius 1355200948Smarius sc = device_get_softc(dev); 1356200948Smarius if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) 1357200948Smarius cookie = ((struct schizo_dma_sync *)cookie)->sds_cookie; 1358200948Smarius return (bus_generic_describe_intr(dev, child, vec, cookie, descr)); 1359200948Smarius} 1360200948Smarius 1361183423Smariusstatic struct resource * 1362183423Smariusschizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1363183423Smarius u_long start, u_long end, u_long count, u_int flags) 1364183423Smarius{ 1365183423Smarius struct schizo_softc *sc; 1366183423Smarius struct resource *rv; 1367183423Smarius struct rman *rm; 1368183423Smarius bus_space_tag_t bt; 1369183423Smarius bus_space_handle_t bh; 1370183423Smarius int needactivate = flags & RF_ACTIVE; 1371183423Smarius 1372183423Smarius flags &= ~RF_ACTIVE; 1373183423Smarius 1374183423Smarius sc = device_get_softc(bus); 1375183423Smarius if (type == SYS_RES_IRQ) { 1376183423Smarius /* 1377183423Smarius * XXX: Don't accept blank ranges for now, only single 1378183423Smarius * interrupts. The other case should not happen with 1379183423Smarius * the MI PCI code... 1380183423Smarius * XXX: This may return a resource that is out of the 1381183423Smarius * range that was specified. Is this correct...? 1382183423Smarius */ 1383183423Smarius if (start != end) 1384183423Smarius panic("%s: XXX: interrupt range", __func__); 1385183423Smarius start = end = INTMAP_VEC(sc->sc_ign, end); 1386201199Smarius return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, 1387201199Smarius type, rid, start, end, count, flags)); 1388183423Smarius } 1389183423Smarius switch (type) { 1390183423Smarius case SYS_RES_MEMORY: 1391183423Smarius rm = &sc->sc_pci_mem_rman; 1392183423Smarius bt = sc->sc_pci_memt; 1393183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1394183423Smarius break; 1395183423Smarius case SYS_RES_IOPORT: 1396183423Smarius rm = &sc->sc_pci_io_rman; 1397183423Smarius bt = sc->sc_pci_iot; 1398183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1399183423Smarius break; 1400183423Smarius default: 1401183423Smarius return (NULL); 1402183423Smarius /* NOTREACHED */ 1403183423Smarius } 1404183423Smarius 1405183423Smarius rv = rman_reserve_resource(rm, start, end, count, flags, child); 1406183423Smarius if (rv == NULL) 1407183423Smarius return (NULL); 1408183423Smarius rman_set_rid(rv, *rid); 1409183423Smarius bh += rman_get_start(rv); 1410183423Smarius rman_set_bustag(rv, bt); 1411183423Smarius rman_set_bushandle(rv, bh); 1412183423Smarius 1413183423Smarius if (needactivate) { 1414183423Smarius if (bus_activate_resource(child, type, *rid, rv)) { 1415183423Smarius rman_release_resource(rv); 1416183423Smarius return (NULL); 1417183423Smarius } 1418183423Smarius } 1419183423Smarius return (rv); 1420183423Smarius} 1421183423Smarius 1422183423Smariusstatic int 1423183423Smariusschizo_activate_resource(device_t bus, device_t child, int type, int rid, 1424183423Smarius struct resource *r) 1425183423Smarius{ 1426183423Smarius void *p; 1427183423Smarius int error; 1428183423Smarius 1429183423Smarius if (type == SYS_RES_IRQ) 1430183423Smarius return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1431183423Smarius type, rid, r)); 1432183423Smarius if (type == SYS_RES_MEMORY) { 1433183423Smarius /* 1434185133Smarius * Need to memory-map the device space, as some drivers 1435185133Smarius * depend on the virtual address being set and usable. 1436183423Smarius */ 1437183423Smarius error = sparc64_bus_mem_map(rman_get_bustag(r), 1438183423Smarius rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1439183423Smarius if (error != 0) 1440183423Smarius return (error); 1441183423Smarius rman_set_virtual(r, p); 1442183423Smarius } 1443183423Smarius return (rman_activate_resource(r)); 1444183423Smarius} 1445183423Smarius 1446183423Smariusstatic int 1447183423Smariusschizo_deactivate_resource(device_t bus, device_t child, int type, int rid, 1448183423Smarius struct resource *r) 1449183423Smarius{ 1450183423Smarius 1451183423Smarius if (type == SYS_RES_IRQ) 1452183423Smarius return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1453183423Smarius type, rid, r)); 1454183423Smarius if (type == SYS_RES_MEMORY) { 1455183423Smarius sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1456183423Smarius rman_set_virtual(r, NULL); 1457183423Smarius } 1458183423Smarius return (rman_deactivate_resource(r)); 1459183423Smarius} 1460183423Smarius 1461183423Smariusstatic int 1462183423Smariusschizo_release_resource(device_t bus, device_t child, int type, int rid, 1463183423Smarius struct resource *r) 1464183423Smarius{ 1465183423Smarius int error; 1466183423Smarius 1467183423Smarius if (type == SYS_RES_IRQ) 1468183423Smarius return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1469183423Smarius type, rid, r)); 1470183423Smarius if (rman_get_flags(r) & RF_ACTIVE) { 1471183423Smarius error = bus_deactivate_resource(child, type, rid, r); 1472183423Smarius if (error) 1473183423Smarius return (error); 1474183423Smarius } 1475183423Smarius return (rman_release_resource(r)); 1476183423Smarius} 1477183423Smarius 1478183423Smariusstatic bus_dma_tag_t 1479183423Smariusschizo_get_dma_tag(device_t bus, device_t child) 1480183423Smarius{ 1481183423Smarius struct schizo_softc *sc; 1482183423Smarius 1483183423Smarius sc = device_get_softc(bus); 1484183423Smarius return (sc->sc_pci_dmat); 1485183423Smarius} 1486183423Smarius 1487183423Smariusstatic phandle_t 1488183423Smariusschizo_get_node(device_t bus, device_t dev) 1489183423Smarius{ 1490183423Smarius struct schizo_softc *sc; 1491183423Smarius 1492183423Smarius sc = device_get_softc(bus); 1493183423Smarius /* We only have one child, the PCI bus, which needs our own node. */ 1494183423Smarius return (sc->sc_node); 1495183423Smarius} 1496183423Smarius 1497183423Smariusstatic bus_space_tag_t 1498183423Smariusschizo_alloc_bus_tag(struct schizo_softc *sc, int type) 1499183423Smarius{ 1500183423Smarius bus_space_tag_t bt; 1501183423Smarius 1502201199Smarius bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1503183423Smarius M_NOWAIT | M_ZERO); 1504183423Smarius if (bt == NULL) 1505183423Smarius panic("%s: out of memory", __func__); 1506183423Smarius 1507183423Smarius bt->bst_cookie = sc; 1508183423Smarius bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1509183423Smarius bt->bst_type = type; 1510183423Smarius return (bt); 1511183423Smarius} 1512183423Smarius 1513183423Smariusstatic u_int 1514183423Smariusschizo_get_timecount(struct timecounter *tc) 1515183423Smarius{ 1516183423Smarius struct schizo_softc *sc; 1517183423Smarius 1518183423Smarius sc = tc->tc_priv; 1519183423Smarius return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1520183423Smarius (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)); 1521183423Smarius} 1522