schizo.c revision 215349
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 215349 2010-11-15 21:58:10Z marius $"); 36 37/* 38 * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to 39 * PCI 2.2 bridges 40 */ 41 42#include "opt_ofw_pci.h" 43#include "opt_schizo.h" 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48#include <sys/kernel.h> 49#include <sys/lock.h> 50#include <sys/malloc.h> 51#include <sys/module.h> 52#include <sys/mutex.h> 53#include <sys/pcpu.h> 54#include <sys/rman.h> 55#include <sys/sysctl.h> 56#include <sys/time.h> 57#include <sys/timetc.h> 58 59#include <dev/ofw/ofw_bus.h> 60#include <dev/ofw/ofw_pci.h> 61#include <dev/ofw/openfirm.h> 62 63#include <machine/bus.h> 64#include <machine/bus_common.h> 65#include <machine/bus_private.h> 66#include <machine/fsr.h> 67#include <machine/iommureg.h> 68#include <machine/iommuvar.h> 69#include <machine/resource.h> 70 71#include <dev/pci/pcireg.h> 72#include <dev/pci/pcivar.h> 73 74#include <sparc64/pci/ofw_pci.h> 75#include <sparc64/pci/schizoreg.h> 76#include <sparc64/pci/schizovar.h> 77 78#include "pcib_if.h" 79 80static const struct schizo_desc *schizo_get_desc(device_t); 81static void schizo_set_intr(struct schizo_softc *, u_int, u_int, 82 driver_filter_t); 83static driver_filter_t schizo_dma_sync_stub; 84static driver_filter_t ichip_dma_sync_stub; 85static void schizo_intr_enable(void *); 86static void schizo_intr_disable(void *); 87static void schizo_intr_assign(void *); 88static void schizo_intr_clear(void *); 89static int schizo_intr_register(struct schizo_softc *sc, u_int ino); 90static int schizo_get_intrmap(struct schizo_softc *, u_int, 91 bus_addr_t *, bus_addr_t *); 92static bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int); 93static timecounter_get_t schizo_get_timecount; 94 95/* Interrupt handlers */ 96static driver_filter_t schizo_pci_bus; 97static driver_filter_t schizo_ue; 98static driver_filter_t schizo_ce; 99static driver_filter_t schizo_host_bus; 100static driver_filter_t schizo_cdma; 101 102/* IOMMU support */ 103static void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 104 105/* 106 * Methods 107 */ 108static device_probe_t schizo_probe; 109static device_attach_t schizo_attach; 110static bus_read_ivar_t schizo_read_ivar; 111static bus_setup_intr_t schizo_setup_intr; 112static bus_teardown_intr_t schizo_teardown_intr; 113static bus_alloc_resource_t schizo_alloc_resource; 114static bus_activate_resource_t schizo_activate_resource; 115static bus_deactivate_resource_t schizo_deactivate_resource; 116static bus_release_resource_t schizo_release_resource; 117static bus_describe_intr_t schizo_describe_intr; 118static bus_get_dma_tag_t schizo_get_dma_tag; 119static pcib_maxslots_t schizo_maxslots; 120static pcib_read_config_t schizo_read_config; 121static pcib_write_config_t schizo_write_config; 122static pcib_route_interrupt_t schizo_route_interrupt; 123static ofw_bus_get_node_t schizo_get_node; 124 125static device_method_t schizo_methods[] = { 126 /* Device interface */ 127 DEVMETHOD(device_probe, schizo_probe), 128 DEVMETHOD(device_attach, schizo_attach), 129 DEVMETHOD(device_shutdown, bus_generic_shutdown), 130 DEVMETHOD(device_suspend, bus_generic_suspend), 131 DEVMETHOD(device_resume, bus_generic_resume), 132 133 /* Bus interface */ 134 DEVMETHOD(bus_print_child, bus_generic_print_child), 135 DEVMETHOD(bus_read_ivar, schizo_read_ivar), 136 DEVMETHOD(bus_setup_intr, schizo_setup_intr), 137 DEVMETHOD(bus_teardown_intr, schizo_teardown_intr), 138 DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 139 DEVMETHOD(bus_activate_resource, schizo_activate_resource), 140 DEVMETHOD(bus_deactivate_resource, schizo_deactivate_resource), 141 DEVMETHOD(bus_release_resource, schizo_release_resource), 142 DEVMETHOD(bus_describe_intr, schizo_describe_intr), 143 DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 144 145 /* pcib interface */ 146 DEVMETHOD(pcib_maxslots, schizo_maxslots), 147 DEVMETHOD(pcib_read_config, schizo_read_config), 148 DEVMETHOD(pcib_write_config, schizo_write_config), 149 DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 150 151 /* ofw_bus interface */ 152 DEVMETHOD(ofw_bus_get_node, schizo_get_node), 153 154 KOBJMETHOD_END 155}; 156 157static devclass_t schizo_devclass; 158 159DEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 160 sizeof(struct schizo_softc)); 161EARLY_DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0, 162 BUS_PASS_BUS); 163 164static SLIST_HEAD(, schizo_softc) schizo_softcs = 165 SLIST_HEAD_INITIALIZER(schizo_softcs); 166 167static const struct intr_controller schizo_ic = { 168 schizo_intr_enable, 169 schizo_intr_disable, 170 schizo_intr_assign, 171 schizo_intr_clear 172}; 173 174struct schizo_icarg { 175 struct schizo_softc *sica_sc; 176 bus_addr_t sica_map; 177 bus_addr_t sica_clr; 178}; 179 180struct schizo_dma_sync { 181 struct schizo_softc *sds_sc; 182 driver_filter_t *sds_handler; 183 void *sds_arg; 184 void *sds_cookie; 185 uint64_t sds_syncval; 186 device_t sds_ppb; /* farest PCI-PCI bridge */ 187 uint8_t sds_bus; /* bus of farest PCI dev. */ 188 uint8_t sds_slot; /* slot of farest PCI dev. */ 189 uint8_t sds_func; /* func. of farest PCI dev. */ 190}; 191 192#define SCHIZO_PERF_CNT_QLTY 100 193 194#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 195 bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 196#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 197 bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 198 199#define SCHIZO_PCI_READ_8(sc, offs) \ 200 SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 201#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 202 SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 203#define SCHIZO_CTRL_READ_8(sc, offs) \ 204 SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 205#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 206 SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 207#define SCHIZO_PCICFG_READ_8(sc, offs) \ 208 SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 209#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 210 SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 211#define SCHIZO_ICON_READ_8(sc, offs) \ 212 SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 213#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 214 SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 215 216struct schizo_desc { 217 const char *sd_string; 218 int sd_mode; 219 const char *sd_name; 220}; 221 222static const struct schizo_desc const schizo_compats[] = { 223 { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 224 { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 225 { NULL, 0, NULL } 226}; 227 228static const struct schizo_desc * 229schizo_get_desc(device_t dev) 230{ 231 const struct schizo_desc *desc; 232 const char *compat; 233 234 compat = ofw_bus_get_compat(dev); 235 if (compat == NULL) 236 return (NULL); 237 for (desc = schizo_compats; desc->sd_string != NULL; desc++) 238 if (strcmp(desc->sd_string, compat) == 0) 239 return (desc); 240 return (NULL); 241} 242 243static int 244schizo_probe(device_t dev) 245{ 246 const char *dtype; 247 248 dtype = ofw_bus_get_type(dev); 249 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 250 schizo_get_desc(dev) != NULL) { 251 device_set_desc(dev, "Sun Host-PCI bridge"); 252 return (0); 253 } 254 return (ENXIO); 255} 256 257static int 258schizo_attach(device_t dev) 259{ 260 struct ofw_pci_ranges *range; 261 const struct schizo_desc *desc; 262 struct schizo_softc *asc, *sc, *osc; 263 struct timecounter *tc; 264 uint64_t ino_bitmap, reg; 265 phandle_t node; 266 uint32_t prop, prop_array[2]; 267 int i, j, mode, rid, tsbsize; 268 269 sc = device_get_softc(dev); 270 node = ofw_bus_get_node(dev); 271 desc = schizo_get_desc(dev); 272 mode = desc->sd_mode; 273 274 sc->sc_dev = dev; 275 sc->sc_node = node; 276 sc->sc_mode = mode; 277 sc->sc_flags = 0; 278 279 /* 280 * The Schizo has three register banks: 281 * (0) per-PBM PCI configuration and status registers, but for bus B 282 * shared with the UPA64s interrupt mapping register banks 283 * (1) shared Schizo controller configuration and status registers 284 * (2) per-PBM PCI configuration space 285 * 286 * The Tomatillo has four register banks: 287 * (0) per-PBM PCI configuration and status registers 288 * (1) per-PBM Tomatillo controller configuration registers, but on 289 * machines having the `jbusppm' device shared with its Estar 290 * register bank for bus A 291 * (2) per-PBM PCI configuration space 292 * (3) per-PBM interrupt concentrator registers 293 */ 294 sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 295 20) & 1; 296 for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 297 i++) { 298 rid = i; 299 sc->sc_mem_res[i] = bus_alloc_resource_any(dev, 300 SYS_RES_MEMORY, &rid, 301 (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 302 i == STX_PCI) || i == STX_CTRL)) || 303 (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 304 i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 305 if (sc->sc_mem_res[i] == NULL) 306 panic("%s: could not allocate register bank %d", 307 __func__, i); 308 } 309 310 /* 311 * Match other Schizos that are already configured against 312 * the controller base physical address. This will be the 313 * same for a pair of devices that share register space. 314 */ 315 osc = NULL; 316 SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 317 if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 318 rman_get_start(sc->sc_mem_res[STX_CTRL])) { 319 /* Found partner. */ 320 osc = asc; 321 break; 322 } 323 } 324 if (osc == NULL) { 325 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 326 M_NOWAIT | M_ZERO); 327 if (sc->sc_mtx == NULL) 328 panic("%s: could not malloc mutex", __func__); 329 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 330 } else { 331 if (sc->sc_mode != SCHIZO_MODE_SCZ) 332 panic("%s: no partner expected", __func__); 333 if (mtx_initialized(osc->sc_mtx) == 0) 334 panic("%s: mutex not initialized", __func__); 335 sc->sc_mtx = osc->sc_mtx; 336 } 337 338 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 339 panic("%s: could not determine IGN", __func__); 340 if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == 341 -1) 342 panic("%s: could not determine version", __func__); 343 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 344 prop = 33000000; 345 346 device_printf(dev, "%s, version %d, IGN %#x, bus %c, %dMHz\n", 347 desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half, 348 prop / 1000 / 1000); 349 350 /* Set up the PCI interrupt retry timer. */ 351#ifdef SCHIZO_DEBUG 352 device_printf(dev, "PCI IRT 0x%016llx\n", (unsigned long long) 353 SCHIZO_PCI_READ_8(sc, STX_PCI_INTR_RETRY_TIM)); 354#endif 355 SCHIZO_PCI_WRITE_8(sc, STX_PCI_INTR_RETRY_TIM, 5); 356 357 /* Set up the PCI control register. */ 358 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 359 reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 360 STX_PCI_CTRL_ERR_IEN | STX_PCI_CTRL_ARB_MASK; 361 reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK); 362 if (OF_getproplen(node, "no-bus-parking") < 0) 363 reg |= STX_PCI_CTRL_ARB_PARK; 364 if (mode == SCHIZO_MODE_TOM) { 365 reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 366 if (sc->sc_ver <= 1) /* revision <= 2.0 */ 367 reg |= TOM_PCI_CTRL_DTO_IEN; 368 else 369 reg |= STX_PCI_CTRL_PTO; 370 } 371#ifdef SCHIZO_DEBUG 372 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 373 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL), 374 (unsigned long long)reg); 375#endif 376 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, reg); 377 378 /* Set up the PCI diagnostic register. */ 379 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 380 reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 381 STX_PCI_DIAG_INTRSYNC_DIS); 382#ifdef SCHIZO_DEBUG 383 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 384 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG), 385 (unsigned long long)reg); 386#endif 387 SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg); 388 389 /* 390 * Enable DMA write parity error interrupts of version >= 7 (i.e. 391 * revision >= 2.5) Schizo. 392 */ 393 if (mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 7) { 394 reg = SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD); 395 reg |= SX_PCI_CFG_ICD_DMAW_PERR_IEN; 396#ifdef SCHIZO_DEBUG 397 device_printf(dev, "PCI CFG/ICD 0x%016llx -> 0x%016llx\n", 398 (unsigned long long)SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD), 399 (unsigned long long)reg); 400#endif 401 SCHIZO_PCI_WRITE_8(sc, SX_PCI_CFG_ICD, reg); 402 } 403 404 /* 405 * On Tomatillo clear the I/O prefetch lengths (workaround for a 406 * Jalapeno bug). 407 */ 408 if (mode == SCHIZO_MODE_TOM) 409 SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 410 (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 411 TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 412 413 /* 414 * Hunt through all the interrupt mapping regs and register 415 * the interrupt controller for our interrupt vectors. We do 416 * this early in order to be able to catch stray interrupts. 417 * This is complicated by the fact that a pair of Schizo PBMs 418 * shares one IGN. 419 */ 420 i = OF_getprop(node, "ino-bitmap", (void *)prop_array, 421 sizeof(prop_array)); 422 if (i != -1) 423 ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 424 else { 425 /* 426 * If the ino-bitmap property is missing, just provide the 427 * default set of interrupts for this controller and let 428 * schizo_setup_intr() take care of child interrupts. 429 */ 430 if (sc->sc_half == 0) 431 ino_bitmap = (1ULL << STX_UE_INO) | 432 (1ULL << STX_CE_INO) | 433 (1ULL << STX_PCIERR_A_INO) | 434 (1ULL << STX_BUS_INO); 435 else 436 ino_bitmap = 1ULL << STX_PCIERR_B_INO; 437 } 438 for (i = 0; i <= STX_MAX_INO; i++) { 439 if ((ino_bitmap & (1ULL << i)) == 0) 440 continue; 441 if (i == STX_FB0_INO || i == STX_FB1_INO) 442 /* Leave for upa(4). */ 443 continue; 444 j = schizo_intr_register(sc, i); 445 if (j != 0) 446 device_printf(dev, "could not register interrupt " 447 "controller for INO %d (%d)\n", i, j); 448 } 449 450 /* 451 * Setup Safari/JBus performance counter 0 in bus cycle counting 452 * mode as timecounter. Unfortunately, this is broken with at 453 * least the version 4 Tomatillos found in Fire V120 and Blade 454 * 1500, which apparently actually count some different event at 455 * ~0.5 and 3MHz respectively instead (also when running in full 456 * power mode). Besides, one counter seems to be shared by a 457 * "pair" of Tomatillos, too. 458 */ 459 if (sc->sc_half == 0) { 460 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_PERF, 461 (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 462 (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 463 tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 464 if (tc == NULL) 465 panic("%s: could not malloc timecounter", __func__); 466 tc->tc_get_timecount = schizo_get_timecount; 467 tc->tc_poll_pps = NULL; 468 tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 469 if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 470 sizeof(prop)) == -1) 471 panic("%s: could not determine clock frequency", 472 __func__); 473 tc->tc_frequency = prop; 474 tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 475 if (mode == SCHIZO_MODE_SCZ) 476 tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 477 else 478 tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 479 tc->tc_priv = sc; 480 tc_init(tc); 481 } 482 483 /* 484 * Set up the IOMMU. Schizo, Tomatillo and XMITS all have 485 * one per PBM. Schizo and XMITS additionally have a streaming 486 * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's 487 * affected by several errata and basically unusable though. 488 */ 489 sc->sc_is.is_flags = IOMMU_PRESERVE_PROM; 490 sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 491 sc->sc_is.is_sb[0] = sc->sc_is.is_sb[1] = 0; 492 if (OF_getproplen(node, "no-streaming-cache") < 0 && 493 !(sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver < 5)) 494 sc->sc_is.is_sb[0] = STX_PCI_STRBUF; 495 496#define TSBCASE(x) \ 497 case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 498 tsbsize = (x); \ 499 break; \ 500 501 i = OF_getprop(node, "virtual-dma", (void *)prop_array, 502 sizeof(prop_array)); 503 if (i == -1 || i != sizeof(prop_array)) 504 schizo_iommu_init(sc, 7, -1); 505 else { 506 switch (prop_array[1]) { 507 TSBCASE(1); 508 TSBCASE(2); 509 TSBCASE(3); 510 TSBCASE(4); 511 TSBCASE(5); 512 TSBCASE(6); 513 TSBCASE(7); 514 TSBCASE(8); 515 default: 516 panic("%s: unsupported DVMA size 0x%x", 517 __func__, prop_array[1]); 518 /* NOTREACHED */ 519 } 520 schizo_iommu_init(sc, tsbsize, prop_array[0]); 521 } 522 523#undef TSBCASE 524 525 /* Initialize memory and I/O rmans. */ 526 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 527 sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 528 if (rman_init(&sc->sc_pci_io_rman) != 0 || 529 rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 530 panic("%s: failed to set up I/O rman", __func__); 531 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 532 sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 533 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 534 rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 535 panic("%s: failed to set up memory rman", __func__); 536 537 i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range); 538 /* 539 * Make sure that the expected ranges are present. The 540 * OFW_PCI_CS_MEM64 one is not currently used though. 541 */ 542 if (i != STX_NRANGE) 543 panic("%s: unsupported number of ranges", __func__); 544 /* 545 * Find the addresses of the various bus spaces. 546 * There should not be multiple ones of one kind. 547 * The physical start addresses of the ranges are the configuration, 548 * memory and I/O handles. 549 */ 550 for (i = 0; i < STX_NRANGE; i++) { 551 j = OFW_PCI_RANGE_CS(&range[i]); 552 if (sc->sc_pci_bh[j] != 0) 553 panic("%s: duplicate range for space %d", 554 __func__, j); 555 sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]); 556 } 557 free(range, M_OFWPROP); 558 559 /* Register the softc, this is needed for paired Schizos. */ 560 SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 561 562 /* Allocate our tags. */ 563 sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 564 sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 565 sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 566 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 567 sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr, 568 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 569 panic("%s: bus_dma_tag_create failed", __func__); 570 /* Customize the tag. */ 571 sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 572 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 573 574 /* 575 * Get the bus range from the firmware. 576 * NB: Tomatillos don't support PCI bus reenumeration. 577 */ 578 i = OF_getprop(node, "bus-range", (void *)prop_array, 579 sizeof(prop_array)); 580 if (i == -1) 581 panic("%s: could not get bus-range", __func__); 582 if (i != sizeof(prop_array)) 583 panic("%s: broken bus-range (%d)", __func__, i); 584 sc->sc_pci_secbus = prop_array[0]; 585 sc->sc_pci_subbus = prop_array[1]; 586 if (bootverbose) 587 device_printf(dev, "bus range %u to %u; PCI bus %d\n", 588 sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus); 589 590 /* Clear any pending PCI error bits. */ 591 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 592 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 593 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 594 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, 595 SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 596 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, 597 SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 598 599 /* 600 * Establish handlers for interesting interrupts... 601 * Someone at Sun clearly was smoking crack; with Schizos PCI 602 * bus error interrupts for one PBM can be routed to the other 603 * PBM though we obviously need to use the softc of the former 604 * as the argument for the interrupt handler and the softc of 605 * the latter as the argument for the interrupt controller. 606 */ 607 if (sc->sc_half == 0) { 608 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 609 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 610 INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 611 sica_sc == osc)) 612 /* 613 * We are the driver for PBM A and either also 614 * registered the interrupt controller for us or 615 * the driver for PBM B has probed first and 616 * registered it for us. 617 */ 618 schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 619 schizo_pci_bus); 620 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 621 osc != NULL) 622 /* 623 * We are the driver for PBM A but registered 624 * the interrupt controller for PBM B, i.e. the 625 * driver for PBM B attached first but couldn't 626 * set up a handler for PBM B. 627 */ 628 schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 629 schizo_pci_bus); 630 } else { 631 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 632 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 633 INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 634 sica_sc == osc)) 635 /* 636 * We are the driver for PBM B and either also 637 * registered the interrupt controller for us or 638 * the driver for PBM A has probed first and 639 * registered it for us. 640 */ 641 schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 642 schizo_pci_bus); 643 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 644 osc != NULL) 645 /* 646 * We are the driver for PBM B but registered 647 * the interrupt controller for PBM A, i.e. the 648 * driver for PBM A attached first but couldn't 649 * set up a handler for PBM A. 650 */ 651 schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 652 schizo_pci_bus); 653 } 654 if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 655 schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 656 if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 657 schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 658 if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 659 schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 660 661 /* 662 * According to the Schizo Errata I-13, consistent DMA flushing/ 663 * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 664 * so we can't use it and need to live with the consequences. With 665 * Schizo version >= 5, CDMA flushing/syncing is usable but requires 666 * the workaround described in Schizo Errata I-23. With Tomatillo 667 * and XMITS, CDMA flushing/syncing works as expected, Tomatillo 668 * version <= 4 (i.e. revision <= 2.3) bridges additionally require 669 * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though. 670 */ 671 if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 672 sc->sc_mode == SCHIZO_MODE_TOM || 673 sc->sc_mode == SCHIZO_MODE_XMS) { 674 sc->sc_flags |= SCHIZO_FLAGS_CDMA; 675 if (sc->sc_mode == SCHIZO_MODE_SCZ) { 676 sc->sc_cdma_state = SCHIZO_CDMA_STATE_DONE; 677 /* 678 * Some firmware versions include the CDMA interrupt 679 * at RID 4 but most don't. With the latter we add 680 * it ourselves at the spare RID 5. 681 */ 682 i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ, 683 4)); 684 if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) { 685 (void)schizo_get_intrmap(sc, i, NULL, 686 &sc->sc_cdma_clr); 687 schizo_set_intr(sc, 4, i, schizo_cdma); 688 } else { 689 i = STX_CDMA_A_INO + sc->sc_half; 690 if (bus_set_resource(dev, SYS_RES_IRQ, 5, 691 INTMAP_VEC(sc->sc_ign, i), 1) != 0) 692 panic("%s: failed to add CDMA " 693 "interrupt", __func__); 694 j = schizo_intr_register(sc, i); 695 if (j != 0) 696 panic("%s: could not register " 697 "interrupt controller for CDMA " 698 "(%d)", __func__, j); 699 (void)schizo_get_intrmap(sc, i, NULL, 700 &sc->sc_cdma_clr); 701 schizo_set_intr(sc, 5, i, schizo_cdma); 702 } 703 } 704 if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 705 sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 706 } 707 708 /* 709 * Set the latency timer register as this isn't always done by the 710 * firmware. 711 */ 712 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 713 PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 714 715 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 716 717#define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \ 718 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \ 719 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, \ 720 (name), CTLFLAG_RD, (arg), 0, (desc)) 721 722 SCHIZO_SYSCTL_ADD_UINT("dma_ce", &sc->sc_stats_dma_ce, 723 "DMA correctable errors"); 724 SCHIZO_SYSCTL_ADD_UINT("pci_non_fatal", &sc->sc_stats_pci_non_fatal, 725 "PCI bus non-fatal errors"); 726 727#undef SCHIZO_SYSCTL_ADD_UINT 728 729 device_add_child(dev, "pci", -1); 730 return (bus_generic_attach(dev)); 731} 732 733static void 734schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 735 driver_filter_t handler) 736{ 737 u_long vec; 738 int rid; 739 740 rid = index; 741 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 742 SYS_RES_IRQ, &rid, RF_ACTIVE); 743 if (sc->sc_irq_res[index] == NULL || 744 INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino || 745 INTIGN(vec) != sc->sc_ign || 746 intr_vectors[vec].iv_ic != &schizo_ic || 747 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 748 INTR_TYPE_MISC | INTR_FAST, handler, NULL, sc, 749 &sc->sc_ihand[index]) != 0) 750 panic("%s: failed to set up interrupt %d", __func__, index); 751} 752 753static int 754schizo_intr_register(struct schizo_softc *sc, u_int ino) 755{ 756 struct schizo_icarg *sica; 757 bus_addr_t intrclr, intrmap; 758 int error; 759 760 if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 761 return (ENXIO); 762 sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 763 if (sica == NULL) 764 return (ENOMEM); 765 sica->sica_sc = sc; 766 sica->sica_map = intrmap; 767 sica->sica_clr = intrclr; 768#ifdef SCHIZO_DEBUG 769 device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 770 ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 771 (u_long)intrclr); 772#endif 773 error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 774 &schizo_ic, sica)); 775 if (error != 0) 776 free(sica, M_DEVBUF); 777 return (error); 778} 779 780static int 781schizo_get_intrmap(struct schizo_softc *sc, u_int ino, 782 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr) 783{ 784 bus_addr_t intrclr, intrmap; 785 uint64_t mr; 786 787 /* 788 * XXX we only look for INOs rather than INRs since the firmware 789 * may not provide the IGN and the IGN is constant for all devices 790 * on that PCI controller. 791 */ 792 793 if (ino > STX_MAX_INO) { 794 device_printf(sc->sc_dev, "out of range INO %d requested\n", 795 ino); 796 return (0); 797 } 798 799 intrmap = STX_PCI_IMAP_BASE + (ino << 3); 800 intrclr = STX_PCI_ICLR_BASE + (ino << 3); 801 mr = SCHIZO_PCI_READ_8(sc, intrmap); 802 if (INTINO(mr) != ino) { 803 device_printf(sc->sc_dev, 804 "interrupt map entry does not match INO (%d != %d)\n", 805 (int)INTINO(mr), ino); 806 return (0); 807 } 808 809 if (intrmapptr != NULL) 810 *intrmapptr = intrmap; 811 if (intrclrptr != NULL) 812 *intrclrptr = intrclr; 813 return (1); 814} 815 816/* 817 * Interrupt handlers 818 */ 819static int 820schizo_pci_bus(void *arg) 821{ 822 struct schizo_softc *sc = arg; 823 uint64_t afar, afsr, csr, iommu; 824 uint32_t status; 825 u_int fatal; 826 827 fatal = 0; 828 829 mtx_lock_spin(sc->sc_mtx); 830 831 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 832 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 833 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 834 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 835 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 836 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 837 838 /* 839 * IOMMU errors are only fatal on Tomatillo and there also only if 840 * target abort was not signaled. 841 */ 842 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0 && 843 (iommu & TOM_PCI_IOMMU_ERR) != 0 && 844 ((status & PCIM_STATUS_STABORT) == 0 || 845 ((iommu & TOM_PCI_IOMMU_ERRMASK) != TOM_PCI_IOMMU_INVALID_ERR && 846 (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) == 0 && 847 (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) == 0))) 848 fatal = 1; 849 else if ((status & PCIM_STATUS_STABORT) != 0) 850 fatal = 1; 851 if ((status & (PCIM_STATUS_PERR | PCIM_STATUS_SERR | 852 PCIM_STATUS_RMABORT | PCIM_STATUS_RTABORT | 853 PCIM_STATUS_MDPERR)) != 0 || 854 (csr & (SCZ_PCI_CTRL_BUS_UNUS | TOM_PCI_CTRL_DTO_ERR | 855 STX_PCI_CTRL_TTO_ERR | STX_PCI_CTRL_RTRY_ERR | 856 SCZ_PCI_CTRL_SBH_ERR | STX_PCI_CTRL_SERR)) != 0 || 857 (afsr & (STX_PCI_AFSR_P_MA | STX_PCI_AFSR_P_TA | 858 STX_PCI_AFSR_P_RTRY | STX_PCI_AFSR_P_PERR | STX_PCI_AFSR_P_TTO | 859 STX_PCI_AFSR_P_UNUS)) != 0) 860 fatal = 1; 861 if (fatal == 0) 862 sc->sc_stats_pci_non_fatal++; 863 864 device_printf(sc->sc_dev, "PCI bus %c error AFAR %#llx AFSR %#llx " 865 "PCI CSR %#llx IOMMU %#llx STATUS %#llx\n", 'A' + sc->sc_half, 866 (unsigned long long)afar, (unsigned long long)afsr, 867 (unsigned long long)csr, (unsigned long long)iommu, 868 (unsigned long long)status); 869 870 /* Clear the error bits that we caught. */ 871 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 872 STX_CS_FUNC, PCIR_STATUS, status, 2); 873 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 874 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 875 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 876 877 mtx_unlock_spin(sc->sc_mtx); 878 879 if (fatal != 0) 880 panic("%s: fatal PCI bus error", 881 device_get_nameunit(sc->sc_dev)); 882 return (FILTER_HANDLED); 883} 884 885static int 886schizo_ue(void *arg) 887{ 888 struct schizo_softc *sc = arg; 889 uint64_t afar, afsr; 890 int i; 891 892 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 893 for (i = 0; i < 1000; i++) 894 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 895 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 896 break; 897 panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 898 device_get_nameunit(sc->sc_dev), (unsigned long long)afar, 899 (unsigned long long)afsr); 900 return (FILTER_HANDLED); 901} 902 903static int 904schizo_ce(void *arg) 905{ 906 struct schizo_softc *sc = arg; 907 uint64_t afar, afsr; 908 int i; 909 910 mtx_lock_spin(sc->sc_mtx); 911 912 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 913 for (i = 0; i < 1000; i++) 914 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 915 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 916 break; 917 sc->sc_stats_dma_ce++; 918 device_printf(sc->sc_dev, 919 "correctable DMA error AFAR %#llx AFSR %#llx\n", 920 (unsigned long long)afar, (unsigned long long)afsr); 921 922 /* Clear the error bits that we caught. */ 923 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 924 925 mtx_unlock_spin(sc->sc_mtx); 926 927 return (FILTER_HANDLED); 928} 929 930static int 931schizo_host_bus(void *arg) 932{ 933 struct schizo_softc *sc = arg; 934 uint64_t errlog; 935 936 errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 937 panic("%s: %s error %#llx", device_get_nameunit(sc->sc_dev), 938 sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 939 (unsigned long long)errlog); 940 return (FILTER_HANDLED); 941} 942 943static int 944schizo_cdma(void *arg) 945{ 946 struct schizo_softc *sc = arg; 947 948 atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE); 949 return (FILTER_HANDLED); 950} 951 952static void 953schizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 954{ 955 956 /* Punch in our copies. */ 957 sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 958 sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 959 sc->sc_is.is_iommu = STX_PCI_IOMMU; 960 sc->sc_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 961 sc->sc_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 962 sc->sc_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 963 sc->sc_is.is_dva = STX_PCI_IOMMU_SVADIAG; 964 sc->sc_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 965 966 iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, tsbsize, 967 dvmabase, 0); 968} 969 970static int 971schizo_maxslots(device_t dev) 972{ 973 struct schizo_softc *sc; 974 975 sc = device_get_softc(dev); 976 if (sc->sc_mode == SCHIZO_MODE_SCZ) 977 return (sc->sc_half == 0 ? 4 : 6); 978 979 /* XXX: is this correct? */ 980 return (PCI_SLOTMAX); 981} 982 983static uint32_t 984schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 985 int width) 986{ 987 struct schizo_softc *sc; 988 bus_space_handle_t bh; 989 u_long offset = 0; 990 uint32_t r, wrd; 991 int i; 992 uint16_t shrt; 993 uint8_t byte; 994 995 sc = device_get_softc(dev); 996 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 997 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 998 return (-1); 999 1000 /* 1001 * The Schizo bridges contain a dupe of their header at 0x80. 1002 */ 1003 if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 1004 slot == STX_CS_DEVICE && func == STX_CS_FUNC && 1005 reg + width > 0x80) 1006 return (0); 1007 1008 offset = STX_CONF_OFF(bus, slot, func, reg); 1009 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1010 switch (width) { 1011 case 1: 1012 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 1013 r = byte; 1014 break; 1015 case 2: 1016 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 1017 r = shrt; 1018 break; 1019 case 4: 1020 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 1021 r = wrd; 1022 break; 1023 default: 1024 panic("%s: bad width", __func__); 1025 /* NOTREACHED */ 1026 } 1027 1028 if (i) { 1029#ifdef SCHIZO_DEBUG 1030 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 1031 __func__, bus, slot, func, reg); 1032#endif 1033 r = -1; 1034 } 1035 return (r); 1036} 1037 1038static void 1039schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1040 u_int reg, uint32_t val, int width) 1041{ 1042 struct schizo_softc *sc; 1043 bus_space_handle_t bh; 1044 u_long offset = 0; 1045 1046 sc = device_get_softc(dev); 1047 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1048 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1049 return; 1050 1051 offset = STX_CONF_OFF(bus, slot, func, reg); 1052 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1053 switch (width) { 1054 case 1: 1055 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1056 break; 1057 case 2: 1058 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1059 break; 1060 case 4: 1061 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1062 break; 1063 default: 1064 panic("%s: bad width", __func__); 1065 /* NOTREACHED */ 1066 } 1067} 1068 1069static int 1070schizo_route_interrupt(device_t bridge, device_t dev, int pin) 1071{ 1072 struct schizo_softc *sc; 1073 struct ofw_pci_register reg; 1074 ofw_pci_intr_t pintr, mintr; 1075 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 1076 1077 sc = device_get_softc(bridge); 1078 pintr = pin; 1079 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1080 ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), 1081 NULL, maskbuf)) 1082 return (mintr); 1083 1084 device_printf(bridge, "could not route pin %d for device %d.%d\n", 1085 pin, pci_get_slot(dev), pci_get_function(dev)); 1086 return (PCI_INVALID_IRQ); 1087} 1088 1089static int 1090schizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1091{ 1092 struct schizo_softc *sc; 1093 1094 sc = device_get_softc(dev); 1095 switch (which) { 1096 case PCIB_IVAR_DOMAIN: 1097 *result = device_get_unit(dev); 1098 return (0); 1099 case PCIB_IVAR_BUS: 1100 *result = sc->sc_pci_secbus; 1101 return (0); 1102 } 1103 return (ENOENT); 1104} 1105 1106static int 1107schizo_dma_sync_stub(void *arg) 1108{ 1109 struct timeval cur, end; 1110 struct schizo_dma_sync *sds = arg; 1111 struct schizo_softc *sc = sds->sds_sc; 1112 uint32_t state; 1113 1114 (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1115 sds->sds_func, PCIR_VENDOR, 2); 1116 for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, 1117 SCHIZO_CDMA_STATE_DONE, SCHIZO_CDMA_STATE_PENDING) == 0;) 1118 ; 1119 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, INTCLR_RECEIVED); 1120 microuptime(&cur); 1121 end.tv_sec = 1; 1122 end.tv_usec = 0; 1123 timevaladd(&end, &cur); 1124 for (; (state = atomic_load_32(&sc->sc_cdma_state)) != 1125 SCHIZO_CDMA_STATE_DONE && timevalcmp(&cur, &end, <=);) 1126 microuptime(&cur); 1127 if (state != SCHIZO_CDMA_STATE_DONE) 1128 panic("%s: DMA does not sync", __func__); 1129 return (sds->sds_handler(sds->sds_arg)); 1130} 1131 1132#define VIS_BLOCKSIZE 64 1133 1134static int 1135ichip_dma_sync_stub(void *arg) 1136{ 1137 static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 1138 struct timeval cur, end; 1139 struct schizo_dma_sync *sds = arg; 1140 struct schizo_softc *sc = sds->sds_sc; 1141 register_t reg, s; 1142 1143 (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1144 sds->sds_func, PCIR_VENDOR, 2); 1145 SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, sds->sds_syncval); 1146 microuptime(&cur); 1147 end.tv_sec = 1; 1148 end.tv_usec = 0; 1149 timevaladd(&end, &cur); 1150 for (; ((reg = SCHIZO_PCI_READ_8(sc, TOMXMS_PCI_DMA_SYNC_PEND)) & 1151 sds->sds_syncval) != 0 && timevalcmp(&cur, &end, <=);) 1152 microuptime(&cur); 1153 if ((reg & sds->sds_syncval) != 0) 1154 panic("%s: DMA does not sync", __func__); 1155 1156 if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1157 s = intr_disable(); 1158 reg = rd(fprs); 1159 wr(fprs, reg | FPRS_FEF, 0); 1160 __asm __volatile("stda %%f0, [%0] %1" 1161 : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 1162 membar(Sync); 1163 wr(fprs, reg, 0); 1164 intr_restore(s); 1165 } 1166 return (sds->sds_handler(sds->sds_arg)); 1167} 1168 1169static void 1170schizo_intr_enable(void *arg) 1171{ 1172 struct intr_vector *iv = arg; 1173 struct schizo_icarg *sica = iv->iv_icarg; 1174 1175 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1176 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1177} 1178 1179static void 1180schizo_intr_disable(void *arg) 1181{ 1182 struct intr_vector *iv = arg; 1183 struct schizo_icarg *sica = iv->iv_icarg; 1184 1185 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1186} 1187 1188static void 1189schizo_intr_assign(void *arg) 1190{ 1191 struct intr_vector *iv = arg; 1192 struct schizo_icarg *sica = iv->iv_icarg; 1193 1194 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1195 SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1196} 1197 1198static void 1199schizo_intr_clear(void *arg) 1200{ 1201 struct intr_vector *iv = arg; 1202 struct schizo_icarg *sica = iv->iv_icarg; 1203 1204 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE); 1205} 1206 1207static int 1208schizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1209 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1210 void **cookiep) 1211{ 1212 devclass_t pci_devclass; 1213 device_t cdev, pdev, pcidev; 1214 struct schizo_dma_sync *sds; 1215 struct schizo_softc *sc; 1216 u_long vec; 1217 int error, found; 1218 1219 sc = device_get_softc(dev); 1220 /* 1221 * Make sure the vector is fully specified. 1222 */ 1223 vec = rman_get_start(ires); 1224 if (INTIGN(vec) != sc->sc_ign) { 1225 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1226 return (EINVAL); 1227 } 1228 1229 if (intr_vectors[vec].iv_ic == &schizo_ic) { 1230 /* 1231 * Ensure we use the right softc in case the interrupt 1232 * is routed to our companion PBM for some odd reason. 1233 */ 1234 sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 1235 sica_sc; 1236 } else if (intr_vectors[vec].iv_ic == NULL) { 1237 /* 1238 * Work around broken firmware which misses entries in 1239 * the ino-bitmap. 1240 */ 1241 error = schizo_intr_register(sc, INTINO(vec)); 1242 if (error != 0) { 1243 device_printf(dev, "could not register interrupt " 1244 "controller for vector 0x%lx (%d)\n", vec, error); 1245 return (error); 1246 } 1247 if (bootverbose) 1248 device_printf(dev, "belatedly registered as " 1249 "interrupt controller for vector 0x%lx\n", vec); 1250 } else { 1251 device_printf(dev, 1252 "invalid interrupt controller for vector 0x%lx\n", vec); 1253 return (EINVAL); 1254 } 1255 1256 /* 1257 * Install a a wrapper for CDMA flushing/syncing for devices 1258 * behind PCI-PCI bridges if possible. 1259 */ 1260 pcidev = NULL; 1261 found = 0; 1262 pci_devclass = devclass_find("pci"); 1263 for (cdev = child; cdev != dev; cdev = pdev) { 1264 pdev = device_get_parent(cdev); 1265 if (pcidev == NULL) { 1266 if (device_get_devclass(pdev) != pci_devclass) 1267 continue; 1268 pcidev = cdev; 1269 continue; 1270 } 1271 if (pci_get_class(cdev) == PCIC_BRIDGE && 1272 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1273 found = 1; 1274 } 1275 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1276 sds = malloc(sizeof(*sds), M_DEVBUF, M_NOWAIT | M_ZERO); 1277 if (sds == NULL) 1278 return (ENOMEM); 1279 if (found != 0 && pcidev != NULL) { 1280 sds->sds_sc = sc; 1281 sds->sds_arg = arg; 1282 sds->sds_ppb = 1283 device_get_parent(device_get_parent(pcidev)); 1284 sds->sds_bus = pci_get_bus(pcidev); 1285 sds->sds_slot = pci_get_slot(pcidev); 1286 sds->sds_func = pci_get_function(pcidev); 1287 sds->sds_syncval = 1ULL << INTINO(vec); 1288 if (bootverbose) 1289 device_printf(dev, "installed DMA sync " 1290 "wrapper for device %d.%d on bus %d\n", 1291 sds->sds_slot, sds->sds_func, 1292 sds->sds_bus); 1293 1294#define DMA_SYNC_STUB \ 1295 (sc->sc_mode == SCHIZO_MODE_SCZ ? schizo_dma_sync_stub : \ 1296 ichip_dma_sync_stub) 1297 1298 if (intr == NULL) { 1299 sds->sds_handler = filt; 1300 error = bus_generic_setup_intr(dev, child, 1301 ires, flags, DMA_SYNC_STUB, intr, sds, 1302 cookiep); 1303 } else { 1304 sds->sds_handler = (driver_filter_t *)intr; 1305 error = bus_generic_setup_intr(dev, child, 1306 ires, flags, filt, (driver_intr_t *) 1307 DMA_SYNC_STUB, sds, cookiep); 1308 } 1309 1310#undef DMA_SYNC_STUB 1311 1312 } else 1313 error = bus_generic_setup_intr(dev, child, ires, 1314 flags, filt, intr, arg, cookiep); 1315 if (error != 0) { 1316 free(sds, M_DEVBUF); 1317 return (error); 1318 } 1319 sds->sds_cookie = *cookiep; 1320 *cookiep = sds; 1321 return (error); 1322 } else if (found != 0) 1323 device_printf(dev, "WARNING: using devices behind PCI-PCI " 1324 "bridges may cause data corruption\n"); 1325 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1326 arg, cookiep)); 1327} 1328 1329static int 1330schizo_teardown_intr(device_t dev, device_t child, struct resource *vec, 1331 void *cookie) 1332{ 1333 struct schizo_dma_sync *sds; 1334 struct schizo_softc *sc; 1335 int error; 1336 1337 sc = device_get_softc(dev); 1338 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1339 sds = cookie; 1340 error = bus_generic_teardown_intr(dev, child, vec, 1341 sds->sds_cookie); 1342 if (error == 0) 1343 free(sds, M_DEVBUF); 1344 return (error); 1345 } 1346 return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1347} 1348 1349static int 1350schizo_describe_intr(device_t dev, device_t child, struct resource *vec, 1351 void *cookie, const char *descr) 1352{ 1353 struct schizo_softc *sc; 1354 1355 sc = device_get_softc(dev); 1356 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) 1357 cookie = ((struct schizo_dma_sync *)cookie)->sds_cookie; 1358 return (bus_generic_describe_intr(dev, child, vec, cookie, descr)); 1359} 1360 1361static struct resource * 1362schizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1363 u_long start, u_long end, u_long count, u_int flags) 1364{ 1365 struct schizo_softc *sc; 1366 struct resource *rv; 1367 struct rman *rm; 1368 bus_space_tag_t bt; 1369 bus_space_handle_t bh; 1370 int needactivate = flags & RF_ACTIVE; 1371 1372 flags &= ~RF_ACTIVE; 1373 1374 sc = device_get_softc(bus); 1375 if (type == SYS_RES_IRQ) { 1376 /* 1377 * XXX: Don't accept blank ranges for now, only single 1378 * interrupts. The other case should not happen with 1379 * the MI PCI code... 1380 * XXX: This may return a resource that is out of the 1381 * range that was specified. Is this correct...? 1382 */ 1383 if (start != end) 1384 panic("%s: XXX: interrupt range", __func__); 1385 start = end = INTMAP_VEC(sc->sc_ign, end); 1386 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, 1387 type, rid, start, end, count, flags)); 1388 } 1389 switch (type) { 1390 case SYS_RES_MEMORY: 1391 rm = &sc->sc_pci_mem_rman; 1392 bt = sc->sc_pci_memt; 1393 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1394 break; 1395 case SYS_RES_IOPORT: 1396 rm = &sc->sc_pci_io_rman; 1397 bt = sc->sc_pci_iot; 1398 bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1399 break; 1400 default: 1401 return (NULL); 1402 /* NOTREACHED */ 1403 } 1404 1405 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1406 if (rv == NULL) 1407 return (NULL); 1408 rman_set_rid(rv, *rid); 1409 bh += rman_get_start(rv); 1410 rman_set_bustag(rv, bt); 1411 rman_set_bushandle(rv, bh); 1412 1413 if (needactivate) { 1414 if (bus_activate_resource(child, type, *rid, rv)) { 1415 rman_release_resource(rv); 1416 return (NULL); 1417 } 1418 } 1419 return (rv); 1420} 1421 1422static int 1423schizo_activate_resource(device_t bus, device_t child, int type, int rid, 1424 struct resource *r) 1425{ 1426 void *p; 1427 int error; 1428 1429 if (type == SYS_RES_IRQ) 1430 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1431 type, rid, r)); 1432 if (type == SYS_RES_MEMORY) { 1433 /* 1434 * Need to memory-map the device space, as some drivers 1435 * depend on the virtual address being set and usable. 1436 */ 1437 error = sparc64_bus_mem_map(rman_get_bustag(r), 1438 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1439 if (error != 0) 1440 return (error); 1441 rman_set_virtual(r, p); 1442 } 1443 return (rman_activate_resource(r)); 1444} 1445 1446static int 1447schizo_deactivate_resource(device_t bus, device_t child, int type, int rid, 1448 struct resource *r) 1449{ 1450 1451 if (type == SYS_RES_IRQ) 1452 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1453 type, rid, r)); 1454 if (type == SYS_RES_MEMORY) { 1455 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1456 rman_set_virtual(r, NULL); 1457 } 1458 return (rman_deactivate_resource(r)); 1459} 1460 1461static int 1462schizo_release_resource(device_t bus, device_t child, int type, int rid, 1463 struct resource *r) 1464{ 1465 int error; 1466 1467 if (type == SYS_RES_IRQ) 1468 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1469 type, rid, r)); 1470 if (rman_get_flags(r) & RF_ACTIVE) { 1471 error = bus_deactivate_resource(child, type, rid, r); 1472 if (error) 1473 return (error); 1474 } 1475 return (rman_release_resource(r)); 1476} 1477 1478static bus_dma_tag_t 1479schizo_get_dma_tag(device_t bus, device_t child) 1480{ 1481 struct schizo_softc *sc; 1482 1483 sc = device_get_softc(bus); 1484 return (sc->sc_pci_dmat); 1485} 1486 1487static phandle_t 1488schizo_get_node(device_t bus, device_t dev) 1489{ 1490 struct schizo_softc *sc; 1491 1492 sc = device_get_softc(bus); 1493 /* We only have one child, the PCI bus, which needs our own node. */ 1494 return (sc->sc_node); 1495} 1496 1497static bus_space_tag_t 1498schizo_alloc_bus_tag(struct schizo_softc *sc, int type) 1499{ 1500 bus_space_tag_t bt; 1501 1502 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1503 M_NOWAIT | M_ZERO); 1504 if (bt == NULL) 1505 panic("%s: out of memory", __func__); 1506 1507 bt->bst_cookie = sc; 1508 bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1509 bt->bst_type = type; 1510 return (bt); 1511} 1512 1513static u_int 1514schizo_get_timecount(struct timecounter *tc) 1515{ 1516 struct schizo_softc *sc; 1517 1518 sc = tc->tc_priv; 1519 return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1520 (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)); 1521} 1522