schizo.c revision 212378
1183423Smarius/*- 2183423Smarius * Copyright (c) 1999, 2000 Matthew R. Green 3183423Smarius * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4183423Smarius * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org> 5183423Smarius * All rights reserved. 6183423Smarius * 7183423Smarius * Redistribution and use in source and binary forms, with or without 8183423Smarius * modification, are permitted provided that the following conditions 9183423Smarius * are met: 10183423Smarius * 1. Redistributions of source code must retain the above copyright 11183423Smarius * notice, this list of conditions and the following disclaimer. 12183423Smarius * 2. Redistributions in binary form must reproduce the above copyright 13183423Smarius * notice, this list of conditions and the following disclaimer in the 14183423Smarius * documentation and/or other materials provided with the distribution. 15183423Smarius * 3. The name of the author may not be used to endorse or promote products 16183423Smarius * derived from this software without specific prior written permission. 17183423Smarius * 18183423Smarius * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19183423Smarius * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20183423Smarius * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21183423Smarius * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22183423Smarius * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23183423Smarius * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24183423Smarius * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25183423Smarius * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26183423Smarius * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27183423Smarius * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28183423Smarius * SUCH DAMAGE. 29183423Smarius * 30183423Smarius * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31183423Smarius * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32183423Smarius */ 33183423Smarius 34183423Smarius#include <sys/cdefs.h> 35183423Smarius__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 212378 2010-09-09 20:26:30Z jhb $"); 36183423Smarius 37183423Smarius/* 38183423Smarius * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to 39183423Smarius * PCI 2.2 bridges 40183423Smarius */ 41183423Smarius 42183423Smarius#include "opt_ofw_pci.h" 43183423Smarius#include "opt_schizo.h" 44183423Smarius 45183423Smarius#include <sys/param.h> 46183423Smarius#include <sys/systm.h> 47183423Smarius#include <sys/bus.h> 48183423Smarius#include <sys/kernel.h> 49183423Smarius#include <sys/lock.h> 50183423Smarius#include <sys/malloc.h> 51183423Smarius#include <sys/module.h> 52183423Smarius#include <sys/mutex.h> 53183423Smarius#include <sys/pcpu.h> 54183423Smarius#include <sys/rman.h> 55208097Smarius#include <sys/sysctl.h> 56185133Smarius#include <sys/time.h> 57183423Smarius#include <sys/timetc.h> 58183423Smarius 59183423Smarius#include <dev/ofw/ofw_bus.h> 60183423Smarius#include <dev/ofw/ofw_pci.h> 61183423Smarius#include <dev/ofw/openfirm.h> 62183423Smarius 63183423Smarius#include <machine/bus.h> 64183423Smarius#include <machine/bus_common.h> 65183423Smarius#include <machine/bus_private.h> 66183423Smarius#include <machine/fsr.h> 67183423Smarius#include <machine/iommureg.h> 68183423Smarius#include <machine/iommuvar.h> 69183423Smarius#include <machine/resource.h> 70183423Smarius 71183423Smarius#include <dev/pci/pcireg.h> 72183423Smarius#include <dev/pci/pcivar.h> 73183423Smarius 74183423Smarius#include <sparc64/pci/ofw_pci.h> 75183423Smarius#include <sparc64/pci/schizoreg.h> 76183423Smarius#include <sparc64/pci/schizovar.h> 77183423Smarius 78183423Smarius#include "pcib_if.h" 79183423Smarius 80183423Smariusstatic const struct schizo_desc *schizo_get_desc(device_t); 81183423Smariusstatic void schizo_set_intr(struct schizo_softc *, u_int, u_int, 82183423Smarius driver_filter_t); 83185133Smariusstatic driver_filter_t schizo_dma_sync_stub; 84185133Smariusstatic driver_filter_t ichip_dma_sync_stub; 85183423Smariusstatic void schizo_intr_enable(void *); 86183423Smariusstatic void schizo_intr_disable(void *); 87183423Smariusstatic void schizo_intr_assign(void *); 88183423Smariusstatic void schizo_intr_clear(void *); 89185133Smariusstatic int schizo_intr_register(struct schizo_softc *sc, u_int ino); 90183423Smariusstatic int schizo_get_intrmap(struct schizo_softc *, u_int, 91183423Smarius bus_addr_t *, bus_addr_t *); 92183423Smariusstatic bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int); 93183423Smariusstatic timecounter_get_t schizo_get_timecount; 94183423Smarius 95183423Smarius/* Interrupt handlers */ 96183423Smariusstatic driver_filter_t schizo_pci_bus; 97183423Smariusstatic driver_filter_t schizo_ue; 98183423Smariusstatic driver_filter_t schizo_ce; 99183423Smariusstatic driver_filter_t schizo_host_bus; 100185133Smariusstatic driver_filter_t schizo_cdma; 101183423Smarius 102183423Smarius/* IOMMU support */ 103183423Smariusstatic void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 104183423Smarius 105183423Smarius/* 106183423Smarius * Methods 107183423Smarius */ 108183423Smariusstatic device_probe_t schizo_probe; 109183423Smariusstatic device_attach_t schizo_attach; 110183423Smariusstatic bus_read_ivar_t schizo_read_ivar; 111183423Smariusstatic bus_setup_intr_t schizo_setup_intr; 112183423Smariusstatic bus_teardown_intr_t schizo_teardown_intr; 113183423Smariusstatic bus_alloc_resource_t schizo_alloc_resource; 114183423Smariusstatic bus_activate_resource_t schizo_activate_resource; 115183423Smariusstatic bus_deactivate_resource_t schizo_deactivate_resource; 116183423Smariusstatic bus_release_resource_t schizo_release_resource; 117200948Smariusstatic bus_describe_intr_t schizo_describe_intr; 118183423Smariusstatic bus_get_dma_tag_t schizo_get_dma_tag; 119183423Smariusstatic pcib_maxslots_t schizo_maxslots; 120183423Smariusstatic pcib_read_config_t schizo_read_config; 121183423Smariusstatic pcib_write_config_t schizo_write_config; 122183423Smariusstatic pcib_route_interrupt_t schizo_route_interrupt; 123183423Smariusstatic ofw_bus_get_node_t schizo_get_node; 124183423Smarius 125183423Smariusstatic device_method_t schizo_methods[] = { 126183423Smarius /* Device interface */ 127183423Smarius DEVMETHOD(device_probe, schizo_probe), 128183423Smarius DEVMETHOD(device_attach, schizo_attach), 129183423Smarius DEVMETHOD(device_shutdown, bus_generic_shutdown), 130183423Smarius DEVMETHOD(device_suspend, bus_generic_suspend), 131183423Smarius DEVMETHOD(device_resume, bus_generic_resume), 132183423Smarius 133183423Smarius /* Bus interface */ 134183423Smarius DEVMETHOD(bus_print_child, bus_generic_print_child), 135183423Smarius DEVMETHOD(bus_read_ivar, schizo_read_ivar), 136183423Smarius DEVMETHOD(bus_setup_intr, schizo_setup_intr), 137183423Smarius DEVMETHOD(bus_teardown_intr, schizo_teardown_intr), 138183423Smarius DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 139183423Smarius DEVMETHOD(bus_activate_resource, schizo_activate_resource), 140183423Smarius DEVMETHOD(bus_deactivate_resource, schizo_deactivate_resource), 141183423Smarius DEVMETHOD(bus_release_resource, schizo_release_resource), 142200948Smarius DEVMETHOD(bus_describe_intr, schizo_describe_intr), 143183423Smarius DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 144183423Smarius 145183423Smarius /* pcib interface */ 146183423Smarius DEVMETHOD(pcib_maxslots, schizo_maxslots), 147183423Smarius DEVMETHOD(pcib_read_config, schizo_read_config), 148183423Smarius DEVMETHOD(pcib_write_config, schizo_write_config), 149183423Smarius DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 150183423Smarius 151183423Smarius /* ofw_bus interface */ 152183423Smarius DEVMETHOD(ofw_bus_get_node, schizo_get_node), 153183423Smarius 154190108Smarius KOBJMETHOD_END 155183423Smarius}; 156183423Smarius 157183423Smariusstatic devclass_t schizo_devclass; 158183423Smarius 159183423SmariusDEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 160183423Smarius sizeof(struct schizo_softc)); 161183423SmariusDRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0); 162183423Smarius 163183423Smariusstatic SLIST_HEAD(, schizo_softc) schizo_softcs = 164183423Smarius SLIST_HEAD_INITIALIZER(schizo_softcs); 165183423Smarius 166183423Smariusstatic const struct intr_controller schizo_ic = { 167183423Smarius schizo_intr_enable, 168183423Smarius schizo_intr_disable, 169183423Smarius schizo_intr_assign, 170183423Smarius schizo_intr_clear 171183423Smarius}; 172183423Smarius 173183423Smariusstruct schizo_icarg { 174183423Smarius struct schizo_softc *sica_sc; 175183423Smarius bus_addr_t sica_map; 176183423Smarius bus_addr_t sica_clr; 177183423Smarius}; 178183423Smarius 179185133Smariusstruct schizo_dma_sync { 180183423Smarius struct schizo_softc *sds_sc; 181183423Smarius driver_filter_t *sds_handler; 182183423Smarius void *sds_arg; 183183423Smarius void *sds_cookie; 184183423Smarius uint64_t sds_syncval; 185185133Smarius device_t sds_ppb; /* farest PCI-PCI bridge */ 186201199Smarius uint8_t sds_bus; /* bus of farest PCI dev. */ 187201199Smarius uint8_t sds_slot; /* slot of farest PCI dev. */ 188201199Smarius uint8_t sds_func; /* func. of farest PCI dev. */ 189183423Smarius}; 190183423Smarius 191183423Smarius#define SCHIZO_PERF_CNT_QLTY 100 192183423Smarius 193206018Smarius#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 194183423Smarius bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 195206018Smarius#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 196183423Smarius bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 197183423Smarius 198206018Smarius#define SCHIZO_PCI_READ_8(sc, offs) \ 199183423Smarius SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 200206018Smarius#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 201183423Smarius SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 202206018Smarius#define SCHIZO_CTRL_READ_8(sc, offs) \ 203183423Smarius SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 204206018Smarius#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 205183423Smarius SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 206206018Smarius#define SCHIZO_PCICFG_READ_8(sc, offs) \ 207183423Smarius SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 208206018Smarius#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 209183423Smarius SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 210206018Smarius#define SCHIZO_ICON_READ_8(sc, offs) \ 211183423Smarius SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 212206018Smarius#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 213183423Smarius SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 214183423Smarius 215183423Smariusstruct schizo_desc { 216183423Smarius const char *sd_string; 217183423Smarius int sd_mode; 218183423Smarius const char *sd_name; 219183423Smarius}; 220183423Smarius 221185133Smariusstatic const struct schizo_desc const schizo_compats[] = { 222183423Smarius { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 223183423Smarius { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 224183423Smarius { NULL, 0, NULL } 225183423Smarius}; 226183423Smarius 227183423Smariusstatic const struct schizo_desc * 228183423Smariusschizo_get_desc(device_t dev) 229183423Smarius{ 230183423Smarius const struct schizo_desc *desc; 231183423Smarius const char *compat; 232183423Smarius 233183423Smarius compat = ofw_bus_get_compat(dev); 234183423Smarius if (compat == NULL) 235183423Smarius return (NULL); 236183423Smarius for (desc = schizo_compats; desc->sd_string != NULL; desc++) 237183423Smarius if (strcmp(desc->sd_string, compat) == 0) 238183423Smarius return (desc); 239183423Smarius return (NULL); 240183423Smarius} 241183423Smarius 242183423Smariusstatic int 243183423Smariusschizo_probe(device_t dev) 244183423Smarius{ 245183423Smarius const char *dtype; 246183423Smarius 247183423Smarius dtype = ofw_bus_get_type(dev); 248197164Smarius if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 249183423Smarius schizo_get_desc(dev) != NULL) { 250183423Smarius device_set_desc(dev, "Sun Host-PCI bridge"); 251183423Smarius return (0); 252183423Smarius } 253183423Smarius return (ENXIO); 254183423Smarius} 255183423Smarius 256183423Smariusstatic int 257183423Smariusschizo_attach(device_t dev) 258183423Smarius{ 259183423Smarius struct ofw_pci_ranges *range; 260183423Smarius const struct schizo_desc *desc; 261183423Smarius struct schizo_softc *asc, *sc, *osc; 262183423Smarius struct timecounter *tc; 263183423Smarius uint64_t ino_bitmap, reg; 264183423Smarius phandle_t node; 265183423Smarius uint32_t prop, prop_array[2]; 266201199Smarius int i, j, mode, rid, tsbsize; 267183423Smarius 268183423Smarius sc = device_get_softc(dev); 269183423Smarius node = ofw_bus_get_node(dev); 270183423Smarius desc = schizo_get_desc(dev); 271183423Smarius mode = desc->sd_mode; 272183423Smarius 273183423Smarius sc->sc_dev = dev; 274183423Smarius sc->sc_node = node; 275183423Smarius sc->sc_mode = mode; 276185133Smarius sc->sc_flags = 0; 277183423Smarius 278183423Smarius /* 279183423Smarius * The Schizo has three register banks: 280183423Smarius * (0) per-PBM PCI configuration and status registers, but for bus B 281183423Smarius * shared with the UPA64s interrupt mapping register banks 282183423Smarius * (1) shared Schizo controller configuration and status registers 283183423Smarius * (2) per-PBM PCI configuration space 284183423Smarius * 285183423Smarius * The Tomatillo has four register banks: 286183423Smarius * (0) per-PBM PCI configuration and status registers 287183423Smarius * (1) per-PBM Tomatillo controller configuration registers, but on 288183423Smarius * machines having the `jbusppm' device shared with its Estar 289183423Smarius * register bank for bus A 290183423Smarius * (2) per-PBM PCI configuration space 291183423Smarius * (3) per-PBM interrupt concentrator registers 292183423Smarius */ 293183423Smarius sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 294183423Smarius 20) & 1; 295201199Smarius for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 296201199Smarius i++) { 297201199Smarius rid = i; 298201199Smarius sc->sc_mem_res[i] = bus_alloc_resource_any(dev, 299183423Smarius SYS_RES_MEMORY, &rid, 300183423Smarius (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 301201199Smarius i == STX_PCI) || i == STX_CTRL)) || 302183423Smarius (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 303201199Smarius i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 304201199Smarius if (sc->sc_mem_res[i] == NULL) 305183423Smarius panic("%s: could not allocate register bank %d", 306201199Smarius __func__, i); 307183423Smarius } 308183423Smarius 309183423Smarius /* 310183423Smarius * Match other Schizos that are already configured against 311183423Smarius * the controller base physical address. This will be the 312183423Smarius * same for a pair of devices that share register space. 313183423Smarius */ 314183423Smarius osc = NULL; 315183423Smarius SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 316183423Smarius if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 317183423Smarius rman_get_start(sc->sc_mem_res[STX_CTRL])) { 318183423Smarius /* Found partner. */ 319183423Smarius osc = asc; 320183423Smarius break; 321183423Smarius } 322183423Smarius } 323183423Smarius if (osc == NULL) { 324183423Smarius sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 325183423Smarius M_NOWAIT | M_ZERO); 326183423Smarius if (sc->sc_mtx == NULL) 327183423Smarius panic("%s: could not malloc mutex", __func__); 328183423Smarius mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 329183423Smarius } else { 330185133Smarius if (sc->sc_mode != SCHIZO_MODE_SCZ) 331185133Smarius panic("%s: no partner expected", __func__); 332183423Smarius if (mtx_initialized(osc->sc_mtx) == 0) 333183423Smarius panic("%s: mutex not initialized", __func__); 334183423Smarius sc->sc_mtx = osc->sc_mtx; 335183423Smarius } 336183423Smarius 337183423Smarius if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 338183423Smarius panic("%s: could not determine IGN", __func__); 339201199Smarius if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == 340201199Smarius -1) 341183423Smarius panic("%s: could not determine version", __func__); 342183423Smarius if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 343183423Smarius prop = 33000000; 344183423Smarius 345183423Smarius device_printf(dev, "%s, version %d, IGN %#x, bus %c, %dMHz\n", 346183423Smarius desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half, 347183423Smarius prop / 1000 / 1000); 348183423Smarius 349183423Smarius /* Set up the PCI interrupt retry timer. */ 350183423Smarius#ifdef SCHIZO_DEBUG 351183423Smarius device_printf(dev, "PCI IRT 0x%016llx\n", (unsigned long long) 352183423Smarius SCHIZO_PCI_READ_8(sc, STX_PCI_INTR_RETRY_TIM)); 353183423Smarius#endif 354183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_INTR_RETRY_TIM, 5); 355183423Smarius 356183423Smarius /* Set up the PCI control register. */ 357183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 358183423Smarius reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 359183423Smarius STX_PCI_CTRL_ERR_IEN | STX_PCI_CTRL_ARB_MASK; 360183423Smarius reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK); 361183423Smarius if (OF_getproplen(node, "no-bus-parking") < 0) 362183423Smarius reg |= STX_PCI_CTRL_ARB_PARK; 363183423Smarius if (mode == SCHIZO_MODE_TOM) { 364183423Smarius reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 365183423Smarius if (sc->sc_ver <= 1) /* revision <= 2.0 */ 366183423Smarius reg |= TOM_PCI_CTRL_DTO_IEN; 367183423Smarius else 368183423Smarius reg |= STX_PCI_CTRL_PTO; 369183423Smarius } 370183423Smarius#ifdef SCHIZO_DEBUG 371183423Smarius device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 372183423Smarius (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL), 373183423Smarius (unsigned long long)reg); 374183423Smarius#endif 375183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, reg); 376183423Smarius 377183423Smarius /* Set up the PCI diagnostic register. */ 378183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 379183423Smarius reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 380183423Smarius STX_PCI_DIAG_INTRSYNC_DIS); 381183423Smarius#ifdef SCHIZO_DEBUG 382183423Smarius device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 383183423Smarius (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG), 384183423Smarius (unsigned long long)reg); 385183423Smarius#endif 386183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg); 387183423Smarius 388183423Smarius /* 389208097Smarius * Enable DMA write parity error interrupts of version >= 7 (i.e. 390208097Smarius * revision >= 2.5) Schizo. 391208097Smarius */ 392208097Smarius if (mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 7) { 393208097Smarius reg = SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD); 394208097Smarius reg |= SX_PCI_CFG_ICD_DMAW_PERR_IEN; 395208097Smarius#ifdef SCHIZO_DEBUG 396208097Smarius device_printf(dev, "PCI CFG/ICD 0x%016llx -> 0x%016llx\n", 397208097Smarius (unsigned long long)SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD), 398208097Smarius (unsigned long long)reg); 399208097Smarius#endif 400208097Smarius SCHIZO_PCI_WRITE_8(sc, SX_PCI_CFG_ICD, reg); 401208097Smarius } 402208097Smarius 403208097Smarius /* 404183423Smarius * On Tomatillo clear the I/O prefetch lengths (workaround for a 405183423Smarius * Jalapeno bug). 406183423Smarius */ 407183423Smarius if (mode == SCHIZO_MODE_TOM) 408183423Smarius SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 409183423Smarius (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 410183423Smarius TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 411183423Smarius 412183423Smarius /* 413183423Smarius * Hunt through all the interrupt mapping regs and register 414186290Smarius * the interrupt controller for our interrupt vectors. We do 415186290Smarius * this early in order to be able to catch stray interrupts. 416186290Smarius * This is complicated by the fact that a pair of Schizo PBMs 417186290Smarius * shares one IGN. 418183423Smarius */ 419201199Smarius i = OF_getprop(node, "ino-bitmap", (void *)prop_array, 420183423Smarius sizeof(prop_array)); 421205254Smarius if (i != -1) 422205254Smarius ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 423205254Smarius else { 424205254Smarius /* 425205254Smarius * If the ino-bitmap property is missing, just provide the 426205254Smarius * default set of interrupts for this controller and let 427205254Smarius * schizo_setup_intr() take care of child interrupts. 428205254Smarius */ 429205254Smarius if (sc->sc_half == 0) 430205254Smarius ino_bitmap = (1ULL << STX_UE_INO) | 431205254Smarius (1ULL << STX_CE_INO) | 432205254Smarius (1ULL << STX_PCIERR_A_INO) | 433205254Smarius (1ULL << STX_BUS_INO); 434205254Smarius else 435205254Smarius ino_bitmap = 1ULL << STX_PCIERR_B_INO; 436205254Smarius } 437201199Smarius for (i = 0; i <= STX_MAX_INO; i++) { 438201199Smarius if ((ino_bitmap & (1ULL << i)) == 0) 439183423Smarius continue; 440201199Smarius if (i == STX_FB0_INO || i == STX_FB1_INO) 441183423Smarius /* Leave for upa(4). */ 442183423Smarius continue; 443201199Smarius j = schizo_intr_register(sc, i); 444201199Smarius if (j != 0) 445186290Smarius device_printf(dev, "could not register interrupt " 446201199Smarius "controller for INO %d (%d)\n", i, j); 447183423Smarius } 448183423Smarius 449183423Smarius /* 450183423Smarius * Setup Safari/JBus performance counter 0 in bus cycle counting 451183423Smarius * mode as timecounter. Unfortunately, this is broken with at 452183423Smarius * least the version 4 Tomatillos found in Fire V120 and Blade 453183423Smarius * 1500, which apparently actually count some different event at 454183423Smarius * ~0.5 and 3MHz respectively instead (also when running in full 455183423Smarius * power mode). Besides, one counter seems to be shared by a 456183423Smarius * "pair" of Tomatillos, too. 457183423Smarius */ 458183423Smarius if (sc->sc_half == 0) { 459183423Smarius SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_PERF, 460183423Smarius (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 461183423Smarius (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 462183423Smarius tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 463183423Smarius if (tc == NULL) 464183423Smarius panic("%s: could not malloc timecounter", __func__); 465183423Smarius tc->tc_get_timecount = schizo_get_timecount; 466183423Smarius tc->tc_poll_pps = NULL; 467183423Smarius tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 468183423Smarius if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 469183423Smarius sizeof(prop)) == -1) 470183423Smarius panic("%s: could not determine clock frequency", 471183423Smarius __func__); 472183423Smarius tc->tc_frequency = prop; 473183423Smarius tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 474183423Smarius if (mode == SCHIZO_MODE_SCZ) 475183423Smarius tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 476183423Smarius else 477183423Smarius tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 478183423Smarius tc->tc_priv = sc; 479183423Smarius tc_init(tc); 480183423Smarius } 481183423Smarius 482190108Smarius /* 483190108Smarius * Set up the IOMMU. Schizo, Tomatillo and XMITS all have 484190108Smarius * one per PBM. Schizo and XMITS additionally have a streaming 485190108Smarius * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's 486190108Smarius * affected by several errata and basically unusable though. 487190108Smarius */ 488201395Smarius sc->sc_is.is_flags = IOMMU_PRESERVE_PROM; 489183423Smarius sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 490190108Smarius sc->sc_is.is_sb[0] = sc->sc_is.is_sb[1] = 0; 491190108Smarius if (OF_getproplen(node, "no-streaming-cache") < 0 && 492190108Smarius !(sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver < 5)) 493183423Smarius sc->sc_is.is_sb[0] = STX_PCI_STRBUF; 494183423Smarius 495183423Smarius#define TSBCASE(x) \ 496183423Smarius case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 497183423Smarius tsbsize = (x); \ 498183423Smarius break; \ 499183423Smarius 500201199Smarius i = OF_getprop(node, "virtual-dma", (void *)prop_array, 501183423Smarius sizeof(prop_array)); 502201199Smarius if (i == -1 || i != sizeof(prop_array)) 503183423Smarius schizo_iommu_init(sc, 7, -1); 504183423Smarius else { 505183423Smarius switch (prop_array[1]) { 506183423Smarius TSBCASE(1); 507183423Smarius TSBCASE(2); 508183423Smarius TSBCASE(3); 509183423Smarius TSBCASE(4); 510183423Smarius TSBCASE(5); 511183423Smarius TSBCASE(6); 512183423Smarius TSBCASE(7); 513183423Smarius TSBCASE(8); 514183423Smarius default: 515183423Smarius panic("%s: unsupported DVMA size 0x%x", 516183423Smarius __func__, prop_array[1]); 517183423Smarius /* NOTREACHED */ 518183423Smarius } 519183423Smarius schizo_iommu_init(sc, tsbsize, prop_array[0]); 520183423Smarius } 521185133Smarius 522183423Smarius#undef TSBCASE 523183423Smarius 524183423Smarius /* Initialize memory and I/O rmans. */ 525183423Smarius sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 526183423Smarius sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 527183423Smarius if (rman_init(&sc->sc_pci_io_rman) != 0 || 528183423Smarius rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 529183423Smarius panic("%s: failed to set up I/O rman", __func__); 530183423Smarius sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 531183423Smarius sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 532183423Smarius if (rman_init(&sc->sc_pci_mem_rman) != 0 || 533183423Smarius rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 534183423Smarius panic("%s: failed to set up memory rman", __func__); 535183423Smarius 536201199Smarius i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range); 537183423Smarius /* 538183423Smarius * Make sure that the expected ranges are present. The 539183423Smarius * OFW_PCI_CS_MEM64 one is not currently used though. 540183423Smarius */ 541201199Smarius if (i != STX_NRANGE) 542183423Smarius panic("%s: unsupported number of ranges", __func__); 543183423Smarius /* 544183423Smarius * Find the addresses of the various bus spaces. 545183423Smarius * There should not be multiple ones of one kind. 546183423Smarius * The physical start addresses of the ranges are the configuration, 547183423Smarius * memory and I/O handles. 548183423Smarius */ 549201199Smarius for (i = 0; i < STX_NRANGE; i++) { 550201199Smarius j = OFW_PCI_RANGE_CS(&range[i]); 551201199Smarius if (sc->sc_pci_bh[j] != 0) 552201199Smarius panic("%s: duplicate range for space %d", 553201199Smarius __func__, j); 554201199Smarius sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]); 555183423Smarius } 556183423Smarius free(range, M_OFWPROP); 557183423Smarius 558183423Smarius /* Register the softc, this is needed for paired Schizos. */ 559183423Smarius SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 560183423Smarius 561183423Smarius /* Allocate our tags. */ 562183423Smarius sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 563183423Smarius sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 564183423Smarius sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 565183423Smarius if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 566183423Smarius sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr, 567183423Smarius 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 568183423Smarius panic("%s: bus_dma_tag_create failed", __func__); 569183423Smarius /* Customize the tag. */ 570183423Smarius sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 571183423Smarius sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 572183423Smarius 573183423Smarius /* 574183423Smarius * Get the bus range from the firmware. 575183423Smarius * NB: Tomatillos don't support PCI bus reenumeration. 576183423Smarius */ 577201199Smarius i = OF_getprop(node, "bus-range", (void *)prop_array, 578183423Smarius sizeof(prop_array)); 579201199Smarius if (i == -1) 580183423Smarius panic("%s: could not get bus-range", __func__); 581201199Smarius if (i != sizeof(prop_array)) 582201199Smarius panic("%s: broken bus-range (%d)", __func__, i); 583201395Smarius sc->sc_pci_secbus = prop_array[0]; 584201395Smarius sc->sc_pci_subbus = prop_array[1]; 585183423Smarius if (bootverbose) 586183423Smarius device_printf(dev, "bus range %u to %u; PCI bus %d\n", 587201395Smarius sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus); 588183423Smarius 589183423Smarius /* Clear any pending PCI error bits. */ 590183423Smarius PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 591183423Smarius PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 592183423Smarius STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 593183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, 594183423Smarius SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 595183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, 596183423Smarius SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 597183423Smarius 598183423Smarius /* 599183423Smarius * Establish handlers for interesting interrupts... 600183423Smarius * Someone at Sun clearly was smoking crack; with Schizos PCI 601183423Smarius * bus error interrupts for one PBM can be routed to the other 602183423Smarius * PBM though we obviously need to use the softc of the former 603183423Smarius * as the argument for the interrupt handler and the softc of 604183423Smarius * the latter as the argument for the interrupt controller. 605183423Smarius */ 606183423Smarius if (sc->sc_half == 0) { 607183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 608183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 609183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 610183423Smarius sica_sc == osc)) 611183423Smarius /* 612183423Smarius * We are the driver for PBM A and either also 613183423Smarius * registered the interrupt controller for us or 614183423Smarius * the driver for PBM B has probed first and 615183423Smarius * registered it for us. 616183423Smarius */ 617183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 618183423Smarius schizo_pci_bus); 619183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 620183423Smarius osc != NULL) 621183423Smarius /* 622183423Smarius * We are the driver for PBM A but registered 623183423Smarius * the interrupt controller for PBM B, i.e. the 624183423Smarius * driver for PBM B attached first but couldn't 625183423Smarius * set up a handler for PBM B. 626183423Smarius */ 627183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 628183423Smarius schizo_pci_bus); 629183423Smarius } else { 630183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 631183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 632183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 633183423Smarius sica_sc == osc)) 634183423Smarius /* 635183423Smarius * We are the driver for PBM B and either also 636183423Smarius * registered the interrupt controller for us or 637183423Smarius * the driver for PBM A has probed first and 638183423Smarius * registered it for us. 639183423Smarius */ 640183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 641183423Smarius schizo_pci_bus); 642183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 643183423Smarius osc != NULL) 644183423Smarius /* 645183423Smarius * We are the driver for PBM B but registered 646183423Smarius * the interrupt controller for PBM A, i.e. the 647183423Smarius * driver for PBM A attached first but couldn't 648183423Smarius * set up a handler for PBM A. 649183423Smarius */ 650183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 651183423Smarius schizo_pci_bus); 652183423Smarius } 653183423Smarius if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 654183423Smarius schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 655183423Smarius if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 656183423Smarius schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 657183423Smarius if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 658183423Smarius schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 659183423Smarius 660183423Smarius /* 661185133Smarius * According to the Schizo Errata I-13, consistent DMA flushing/ 662185133Smarius * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 663201126Smarius * so we can't use it and need to live with the consequences. With 664201126Smarius * Schizo version >= 5, CDMA flushing/syncing is usable but requires 665201126Smarius * the workaround described in Schizo Errata I-23. With Tomatillo 666201126Smarius * and XMITS, CDMA flushing/syncing works as expected, Tomatillo 667201126Smarius * version <= 4 (i.e. revision <= 2.3) bridges additionally require 668201126Smarius * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though. 669185133Smarius */ 670185133Smarius if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 671201199Smarius sc->sc_mode == SCHIZO_MODE_TOM || 672201199Smarius sc->sc_mode == SCHIZO_MODE_XMS) { 673185133Smarius sc->sc_flags |= SCHIZO_FLAGS_CDMA; 674185133Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ) { 675185133Smarius sc->sc_cdma_state = SCHIZO_CDMA_STATE_DONE; 676201126Smarius /* 677201126Smarius * Some firmware versions include the CDMA interrupt 678201126Smarius * at RID 4 but most don't. With the latter we add 679201126Smarius * it ourselves at the spare RID 5. 680201126Smarius */ 681201199Smarius i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ, 682201126Smarius 4)); 683201199Smarius if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) { 684201199Smarius (void)schizo_get_intrmap(sc, i, NULL, 685201126Smarius &sc->sc_cdma_clr); 686201199Smarius schizo_set_intr(sc, 4, i, schizo_cdma); 687201126Smarius } else { 688201199Smarius i = STX_CDMA_A_INO + sc->sc_half; 689201126Smarius if (bus_set_resource(dev, SYS_RES_IRQ, 5, 690201199Smarius INTMAP_VEC(sc->sc_ign, i), 1) != 0) 691201126Smarius panic("%s: failed to add CDMA " 692201126Smarius "interrupt", __func__); 693201199Smarius j = schizo_intr_register(sc, i); 694201199Smarius if (j != 0) 695201126Smarius panic("%s: could not register " 696201126Smarius "interrupt controller for CDMA " 697201199Smarius "(%d)", __func__, j); 698201199Smarius (void)schizo_get_intrmap(sc, i, NULL, 699201126Smarius &sc->sc_cdma_clr); 700201199Smarius schizo_set_intr(sc, 5, i, schizo_cdma); 701201126Smarius } 702185133Smarius } 703185133Smarius if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 704185133Smarius sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 705185133Smarius } 706185133Smarius 707185133Smarius /* 708183423Smarius * Set the latency timer register as this isn't always done by the 709183423Smarius * firmware. 710183423Smarius */ 711183423Smarius PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 712183423Smarius PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 713183423Smarius 714183423Smarius ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 715183423Smarius 716208097Smarius#define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \ 717208097Smarius SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \ 718208097Smarius SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, \ 719208097Smarius (name), CTLFLAG_RD, (arg), 0, (desc)) 720208097Smarius 721208097Smarius SCHIZO_SYSCTL_ADD_UINT("dma_ce", &sc->sc_stats_dma_ce, 722208097Smarius "DMA correctable errors"); 723208097Smarius SCHIZO_SYSCTL_ADD_UINT("pci_non_fatal", &sc->sc_stats_pci_non_fatal, 724208097Smarius "PCI bus non-fatal errors"); 725208097Smarius 726208097Smarius#undef SCHIZO_SYSCTL_ADD_UINT 727208097Smarius 728183423Smarius device_add_child(dev, "pci", -1); 729183423Smarius return (bus_generic_attach(dev)); 730183423Smarius} 731183423Smarius 732183423Smariusstatic void 733183423Smariusschizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 734183423Smarius driver_filter_t handler) 735183423Smarius{ 736183423Smarius u_long vec; 737183423Smarius int rid; 738183423Smarius 739183423Smarius rid = index; 740201199Smarius sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 741201199Smarius SYS_RES_IRQ, &rid, RF_ACTIVE); 742183423Smarius if (sc->sc_irq_res[index] == NULL || 743201199Smarius INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino || 744201199Smarius INTIGN(vec) != sc->sc_ign || 745183423Smarius intr_vectors[vec].iv_ic != &schizo_ic || 746185133Smarius bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 747185133Smarius INTR_TYPE_MISC | INTR_FAST, handler, NULL, sc, 748185133Smarius &sc->sc_ihand[index]) != 0) 749183423Smarius panic("%s: failed to set up interrupt %d", __func__, index); 750183423Smarius} 751183423Smarius 752183423Smariusstatic int 753185133Smariusschizo_intr_register(struct schizo_softc *sc, u_int ino) 754185133Smarius{ 755185133Smarius struct schizo_icarg *sica; 756185133Smarius bus_addr_t intrclr, intrmap; 757185133Smarius int error; 758185133Smarius 759185133Smarius if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 760185133Smarius return (ENXIO); 761185133Smarius sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 762185133Smarius if (sica == NULL) 763185133Smarius return (ENOMEM); 764185133Smarius sica->sica_sc = sc; 765185133Smarius sica->sica_map = intrmap; 766185133Smarius sica->sica_clr = intrclr; 767185133Smarius#ifdef SCHIZO_DEBUG 768185133Smarius device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 769185133Smarius ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 770185133Smarius (u_long)intrclr); 771185133Smarius#endif 772185133Smarius error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 773185133Smarius &schizo_ic, sica)); 774185133Smarius if (error != 0) 775185133Smarius free(sica, M_DEVBUF); 776185133Smarius return (error); 777185133Smarius} 778185133Smarius 779185133Smariusstatic int 780201199Smariusschizo_get_intrmap(struct schizo_softc *sc, u_int ino, 781201199Smarius bus_addr_t *intrmapptr, bus_addr_t *intrclrptr) 782183423Smarius{ 783183423Smarius bus_addr_t intrclr, intrmap; 784183423Smarius uint64_t mr; 785183423Smarius 786183423Smarius /* 787183423Smarius * XXX we only look for INOs rather than INRs since the firmware 788183423Smarius * may not provide the IGN and the IGN is constant for all devices 789183423Smarius * on that PCI controller. 790183423Smarius */ 791183423Smarius 792183423Smarius if (ino > STX_MAX_INO) { 793183423Smarius device_printf(sc->sc_dev, "out of range INO %d requested\n", 794183423Smarius ino); 795183423Smarius return (0); 796183423Smarius } 797183423Smarius 798183423Smarius intrmap = STX_PCI_IMAP_BASE + (ino << 3); 799183423Smarius intrclr = STX_PCI_ICLR_BASE + (ino << 3); 800183423Smarius mr = SCHIZO_PCI_READ_8(sc, intrmap); 801183423Smarius if (INTINO(mr) != ino) { 802183423Smarius device_printf(sc->sc_dev, 803183423Smarius "interrupt map entry does not match INO (%d != %d)\n", 804183423Smarius (int)INTINO(mr), ino); 805183423Smarius return (0); 806183423Smarius } 807183423Smarius 808183423Smarius if (intrmapptr != NULL) 809183423Smarius *intrmapptr = intrmap; 810183423Smarius if (intrclrptr != NULL) 811183423Smarius *intrclrptr = intrclr; 812183423Smarius return (1); 813183423Smarius} 814183423Smarius 815183423Smarius/* 816183423Smarius * Interrupt handlers 817183423Smarius */ 818183423Smariusstatic int 819183423Smariusschizo_pci_bus(void *arg) 820183423Smarius{ 821183423Smarius struct schizo_softc *sc = arg; 822183423Smarius uint64_t afar, afsr, csr, iommu; 823183423Smarius uint32_t status; 824208097Smarius u_int fatal; 825183423Smarius 826208097Smarius fatal = 0; 827208097Smarius 828208097Smarius mtx_lock_spin(sc->sc_mtx); 829208097Smarius 830183423Smarius afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 831183423Smarius afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 832183423Smarius csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 833183423Smarius iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 834183423Smarius status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 835183423Smarius STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 836183423Smarius 837208097Smarius /* 838208097Smarius * IOMMU errors are only fatal on Tomatillo and there also only if 839208097Smarius * target abort was not signaled. 840208097Smarius */ 841208097Smarius if ((csr & STX_PCI_CTRL_MMU_ERR) != 0 && 842208097Smarius (iommu & TOM_PCI_IOMMU_ERR) != 0 && 843208097Smarius ((status & PCIM_STATUS_STABORT) == 0 || 844208097Smarius ((iommu & TOM_PCI_IOMMU_ERRMASK) != TOM_PCI_IOMMU_INVALID_ERR && 845208097Smarius (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) == 0 && 846208097Smarius (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) == 0))) 847208097Smarius fatal = 1; 848208097Smarius else if ((status & PCIM_STATUS_STABORT) != 0) 849208097Smarius fatal = 1; 850208097Smarius if ((status & (PCIM_STATUS_PERR | PCIM_STATUS_SERR | 851208097Smarius PCIM_STATUS_RMABORT | PCIM_STATUS_RTABORT | 852212378Sjhb PCIM_STATUS_MDPERR)) != 0 || 853208097Smarius (csr & (SCZ_PCI_CTRL_BUS_UNUS | TOM_PCI_CTRL_DTO_ERR | 854208097Smarius STX_PCI_CTRL_TTO_ERR | STX_PCI_CTRL_RTRY_ERR | 855208097Smarius SCZ_PCI_CTRL_SBH_ERR | STX_PCI_CTRL_SERR)) != 0 || 856208097Smarius (afsr & (STX_PCI_AFSR_P_MA | STX_PCI_AFSR_P_TA | 857208097Smarius STX_PCI_AFSR_P_RTRY | STX_PCI_AFSR_P_PERR | STX_PCI_AFSR_P_TTO | 858208097Smarius STX_PCI_AFSR_P_UNUS)) != 0) 859208097Smarius fatal = 1; 860208097Smarius if (fatal == 0) 861208097Smarius sc->sc_stats_pci_non_fatal++; 862183423Smarius 863208097Smarius device_printf(sc->sc_dev, "PCI bus %c error AFAR %#llx AFSR %#llx " 864208097Smarius "PCI CSR %#llx IOMMU %#llx STATUS %#llx\n", 'A' + sc->sc_half, 865208097Smarius (unsigned long long)afar, (unsigned long long)afsr, 866208097Smarius (unsigned long long)csr, (unsigned long long)iommu, 867208097Smarius (unsigned long long)status); 868183423Smarius 869183423Smarius /* Clear the error bits that we caught. */ 870183423Smarius PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 871183423Smarius STX_CS_FUNC, PCIR_STATUS, status, 2); 872183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 873183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 874208097Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 875208097Smarius 876208097Smarius mtx_unlock_spin(sc->sc_mtx); 877208097Smarius 878208097Smarius if (fatal != 0) 879208097Smarius panic("%s: fatal PCI bus error", 880208097Smarius device_get_nameunit(sc->sc_dev)); 881183423Smarius return (FILTER_HANDLED); 882183423Smarius} 883183423Smarius 884183423Smariusstatic int 885183423Smariusschizo_ue(void *arg) 886183423Smarius{ 887183423Smarius struct schizo_softc *sc = arg; 888183423Smarius uint64_t afar, afsr; 889183423Smarius int i; 890183423Smarius 891183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 892183423Smarius for (i = 0; i < 1000; i++) 893183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 894183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 895183423Smarius break; 896183423Smarius panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 897206020Smarius device_get_nameunit(sc->sc_dev), (unsigned long long)afar, 898183423Smarius (unsigned long long)afsr); 899183423Smarius return (FILTER_HANDLED); 900183423Smarius} 901183423Smarius 902183423Smariusstatic int 903183423Smariusschizo_ce(void *arg) 904183423Smarius{ 905183423Smarius struct schizo_softc *sc = arg; 906183423Smarius uint64_t afar, afsr; 907183423Smarius int i; 908183423Smarius 909183423Smarius mtx_lock_spin(sc->sc_mtx); 910208097Smarius 911183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 912183423Smarius for (i = 0; i < 1000; i++) 913183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 914183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 915183423Smarius break; 916208097Smarius sc->sc_stats_dma_ce++; 917183423Smarius device_printf(sc->sc_dev, 918183423Smarius "correctable DMA error AFAR %#llx AFSR %#llx\n", 919183423Smarius (unsigned long long)afar, (unsigned long long)afsr); 920208097Smarius 921183423Smarius /* Clear the error bits that we caught. */ 922183423Smarius SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 923208097Smarius 924183423Smarius mtx_unlock_spin(sc->sc_mtx); 925208097Smarius 926183423Smarius return (FILTER_HANDLED); 927183423Smarius} 928183423Smarius 929183423Smariusstatic int 930183423Smariusschizo_host_bus(void *arg) 931183423Smarius{ 932183423Smarius struct schizo_softc *sc = arg; 933183423Smarius uint64_t errlog; 934183423Smarius 935183423Smarius errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 936206020Smarius panic("%s: %s error %#llx", device_get_nameunit(sc->sc_dev), 937183423Smarius sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 938183423Smarius (unsigned long long)errlog); 939183423Smarius return (FILTER_HANDLED); 940183423Smarius} 941183423Smarius 942185133Smariusstatic int 943185133Smariusschizo_cdma(void *arg) 944185133Smarius{ 945185133Smarius struct schizo_softc *sc = arg; 946185133Smarius 947185133Smarius atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE); 948185133Smarius return (FILTER_HANDLED); 949185133Smarius} 950185133Smarius 951183423Smariusstatic void 952183423Smariusschizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 953183423Smarius{ 954183423Smarius 955183423Smarius /* Punch in our copies. */ 956183423Smarius sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 957183423Smarius sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 958183423Smarius sc->sc_is.is_iommu = STX_PCI_IOMMU; 959183423Smarius sc->sc_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 960183423Smarius sc->sc_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 961183423Smarius sc->sc_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 962183423Smarius sc->sc_is.is_dva = STX_PCI_IOMMU_SVADIAG; 963183423Smarius sc->sc_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 964183423Smarius 965183423Smarius iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, tsbsize, 966183423Smarius dvmabase, 0); 967183423Smarius} 968183423Smarius 969183423Smariusstatic int 970183423Smariusschizo_maxslots(device_t dev) 971183423Smarius{ 972183423Smarius struct schizo_softc *sc; 973183423Smarius 974183423Smarius sc = device_get_softc(dev); 975183423Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ) 976183423Smarius return (sc->sc_half == 0 ? 4 : 6); 977183423Smarius 978183423Smarius /* XXX: is this correct? */ 979183423Smarius return (PCI_SLOTMAX); 980183423Smarius} 981183423Smarius 982183423Smariusstatic uint32_t 983183423Smariusschizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 984183423Smarius int width) 985183423Smarius{ 986183423Smarius struct schizo_softc *sc; 987183423Smarius bus_space_handle_t bh; 988183423Smarius u_long offset = 0; 989183423Smarius uint32_t r, wrd; 990183423Smarius int i; 991183423Smarius uint16_t shrt; 992183423Smarius uint8_t byte; 993183423Smarius 994183423Smarius sc = device_get_softc(dev); 995201395Smarius if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 996201395Smarius slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 997201395Smarius return (-1); 998183423Smarius 999183423Smarius /* 1000183423Smarius * The Schizo bridges contain a dupe of their header at 0x80. 1001183423Smarius */ 1002183423Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 1003183423Smarius slot == STX_CS_DEVICE && func == STX_CS_FUNC && 1004183423Smarius reg + width > 0x80) 1005183423Smarius return (0); 1006183423Smarius 1007183423Smarius offset = STX_CONF_OFF(bus, slot, func, reg); 1008183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1009183423Smarius switch (width) { 1010183423Smarius case 1: 1011183423Smarius i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 1012183423Smarius r = byte; 1013183423Smarius break; 1014183423Smarius case 2: 1015183423Smarius i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 1016183423Smarius r = shrt; 1017183423Smarius break; 1018183423Smarius case 4: 1019183423Smarius i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 1020183423Smarius r = wrd; 1021183423Smarius break; 1022183423Smarius default: 1023183423Smarius panic("%s: bad width", __func__); 1024183423Smarius /* NOTREACHED */ 1025183423Smarius } 1026183423Smarius 1027183423Smarius if (i) { 1028183423Smarius#ifdef SCHIZO_DEBUG 1029183423Smarius printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 1030183423Smarius __func__, bus, slot, func, reg); 1031183423Smarius#endif 1032183423Smarius r = -1; 1033183423Smarius } 1034183423Smarius return (r); 1035183423Smarius} 1036183423Smarius 1037183423Smariusstatic void 1038201199Smariusschizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1039201199Smarius u_int reg, uint32_t val, int width) 1040183423Smarius{ 1041183423Smarius struct schizo_softc *sc; 1042183423Smarius bus_space_handle_t bh; 1043183423Smarius u_long offset = 0; 1044183423Smarius 1045183423Smarius sc = device_get_softc(dev); 1046201395Smarius if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1047201395Smarius slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1048201395Smarius return; 1049201395Smarius 1050183423Smarius offset = STX_CONF_OFF(bus, slot, func, reg); 1051183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1052183423Smarius switch (width) { 1053183423Smarius case 1: 1054183423Smarius bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1055183423Smarius break; 1056183423Smarius case 2: 1057183423Smarius bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1058183423Smarius break; 1059183423Smarius case 4: 1060183423Smarius bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1061183423Smarius break; 1062183423Smarius default: 1063183423Smarius panic("%s: bad width", __func__); 1064183423Smarius /* NOTREACHED */ 1065183423Smarius } 1066183423Smarius} 1067183423Smarius 1068183423Smariusstatic int 1069183423Smariusschizo_route_interrupt(device_t bridge, device_t dev, int pin) 1070183423Smarius{ 1071183423Smarius struct schizo_softc *sc; 1072183423Smarius struct ofw_pci_register reg; 1073183423Smarius ofw_pci_intr_t pintr, mintr; 1074183423Smarius uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 1075183423Smarius 1076183423Smarius sc = device_get_softc(bridge); 1077183423Smarius pintr = pin; 1078201199Smarius if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1079201199Smarius ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), 1080209298Snwhitehorn NULL, maskbuf)) 1081183423Smarius return (mintr); 1082183423Smarius 1083183423Smarius device_printf(bridge, "could not route pin %d for device %d.%d\n", 1084183423Smarius pin, pci_get_slot(dev), pci_get_function(dev)); 1085183423Smarius return (PCI_INVALID_IRQ); 1086183423Smarius} 1087183423Smarius 1088183423Smariusstatic int 1089183423Smariusschizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1090183423Smarius{ 1091183423Smarius struct schizo_softc *sc; 1092183423Smarius 1093183423Smarius sc = device_get_softc(dev); 1094183423Smarius switch (which) { 1095183423Smarius case PCIB_IVAR_DOMAIN: 1096183423Smarius *result = device_get_unit(dev); 1097183423Smarius return (0); 1098183423Smarius case PCIB_IVAR_BUS: 1099183423Smarius *result = sc->sc_pci_secbus; 1100183423Smarius return (0); 1101183423Smarius } 1102183423Smarius return (ENOENT); 1103183423Smarius} 1104183423Smarius 1105185133Smariusstatic int 1106185133Smariusschizo_dma_sync_stub(void *arg) 1107185133Smarius{ 1108185133Smarius struct timeval cur, end; 1109185133Smarius struct schizo_dma_sync *sds = arg; 1110185133Smarius struct schizo_softc *sc = sds->sds_sc; 1111185133Smarius uint32_t state; 1112185133Smarius 1113185133Smarius (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1114185133Smarius sds->sds_func, PCIR_VENDOR, 2); 1115201199Smarius for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, 1116201199Smarius SCHIZO_CDMA_STATE_DONE, SCHIZO_CDMA_STATE_PENDING) == 0;) 1117185133Smarius ; 1118206018Smarius SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, INTCLR_RECEIVED); 1119185133Smarius microuptime(&cur); 1120185133Smarius end.tv_sec = 1; 1121185133Smarius end.tv_usec = 0; 1122185133Smarius timevaladd(&end, &cur); 1123185133Smarius for (; (state = atomic_load_32(&sc->sc_cdma_state)) != 1124185133Smarius SCHIZO_CDMA_STATE_DONE && timevalcmp(&cur, &end, <=);) 1125185133Smarius microuptime(&cur); 1126185133Smarius if (state != SCHIZO_CDMA_STATE_DONE) 1127185133Smarius panic("%s: DMA does not sync", __func__); 1128185133Smarius return (sds->sds_handler(sds->sds_arg)); 1129185133Smarius} 1130185133Smarius 1131183423Smarius#define VIS_BLOCKSIZE 64 1132183423Smarius 1133183423Smariusstatic int 1134185133Smariusichip_dma_sync_stub(void *arg) 1135183423Smarius{ 1136183423Smarius static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 1137185133Smarius struct timeval cur, end; 1138185133Smarius struct schizo_dma_sync *sds = arg; 1139183423Smarius struct schizo_softc *sc = sds->sds_sc; 1140184428Smarius register_t reg, s; 1141183423Smarius 1142185133Smarius (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1143185133Smarius sds->sds_func, PCIR_VENDOR, 2); 1144184428Smarius SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, sds->sds_syncval); 1145185133Smarius microuptime(&cur); 1146185133Smarius end.tv_sec = 1; 1147185133Smarius end.tv_usec = 0; 1148185133Smarius timevaladd(&end, &cur); 1149185133Smarius for (; ((reg = SCHIZO_PCI_READ_8(sc, TOMXMS_PCI_DMA_SYNC_PEND)) & 1150185133Smarius sds->sds_syncval) != 0 && timevalcmp(&cur, &end, <=);) 1151185133Smarius microuptime(&cur); 1152185133Smarius if ((reg & sds->sds_syncval) != 0) 1153185133Smarius panic("%s: DMA does not sync", __func__); 1154183423Smarius 1155185133Smarius if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1156184428Smarius s = intr_disable(); 1157183423Smarius reg = rd(fprs); 1158183423Smarius wr(fprs, reg | FPRS_FEF, 0); 1159184428Smarius __asm __volatile("stda %%f0, [%0] %1" 1160183423Smarius : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 1161184428Smarius membar(Sync); 1162183423Smarius wr(fprs, reg, 0); 1163184428Smarius intr_restore(s); 1164183423Smarius } 1165183423Smarius return (sds->sds_handler(sds->sds_arg)); 1166183423Smarius} 1167183423Smarius 1168183423Smariusstatic void 1169183423Smariusschizo_intr_enable(void *arg) 1170183423Smarius{ 1171183423Smarius struct intr_vector *iv = arg; 1172183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1173183423Smarius 1174183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1175183423Smarius INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1176183423Smarius} 1177183423Smarius 1178183423Smariusstatic void 1179183423Smariusschizo_intr_disable(void *arg) 1180183423Smarius{ 1181183423Smarius struct intr_vector *iv = arg; 1182183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1183183423Smarius 1184183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1185183423Smarius} 1186183423Smarius 1187183423Smariusstatic void 1188183423Smariusschizo_intr_assign(void *arg) 1189183423Smarius{ 1190183423Smarius struct intr_vector *iv = arg; 1191183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1192183423Smarius 1193183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1194183423Smarius SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1195183423Smarius} 1196183423Smarius 1197183423Smariusstatic void 1198183423Smariusschizo_intr_clear(void *arg) 1199183423Smarius{ 1200183423Smarius struct intr_vector *iv = arg; 1201183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1202183423Smarius 1203206018Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE); 1204183423Smarius} 1205183423Smarius 1206183423Smariusstatic int 1207183423Smariusschizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1208183423Smarius int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1209183423Smarius void **cookiep) 1210183423Smarius{ 1211185133Smarius devclass_t pci_devclass; 1212185133Smarius device_t cdev, pdev, pcidev; 1213185133Smarius struct schizo_dma_sync *sds; 1214183423Smarius struct schizo_softc *sc; 1215183423Smarius u_long vec; 1216185133Smarius int error, found; 1217183423Smarius 1218183423Smarius sc = device_get_softc(dev); 1219183423Smarius /* 1220186290Smarius * Make sure the vector is fully specified. 1221183423Smarius */ 1222183423Smarius vec = rman_get_start(ires); 1223186290Smarius if (INTIGN(vec) != sc->sc_ign) { 1224183423Smarius device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1225183423Smarius return (EINVAL); 1226183423Smarius } 1227183423Smarius 1228186290Smarius if (intr_vectors[vec].iv_ic == &schizo_ic) { 1229186290Smarius /* 1230186290Smarius * Ensure we use the right softc in case the interrupt 1231186290Smarius * is routed to our companion PBM for some odd reason. 1232186290Smarius */ 1233186290Smarius sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 1234186290Smarius sica_sc; 1235186290Smarius } else if (intr_vectors[vec].iv_ic == NULL) { 1236186290Smarius /* 1237186290Smarius * Work around broken firmware which misses entries in 1238186290Smarius * the ino-bitmap. 1239186290Smarius */ 1240186290Smarius error = schizo_intr_register(sc, INTINO(vec)); 1241186290Smarius if (error != 0) { 1242186290Smarius device_printf(dev, "could not register interrupt " 1243186290Smarius "controller for vector 0x%lx (%d)\n", vec, error); 1244186290Smarius return (error); 1245186290Smarius } 1246190108Smarius if (bootverbose) 1247190108Smarius device_printf(dev, "belatedly registered as " 1248190108Smarius "interrupt controller for vector 0x%lx\n", vec); 1249186290Smarius } else { 1250186290Smarius device_printf(dev, 1251186290Smarius "invalid interrupt controller for vector 0x%lx\n", vec); 1252186290Smarius return (EINVAL); 1253186290Smarius } 1254186290Smarius 1255183423Smarius /* 1256185133Smarius * Install a a wrapper for CDMA flushing/syncing for devices 1257185133Smarius * behind PCI-PCI bridges if possible. 1258183423Smarius */ 1259185133Smarius pcidev = NULL; 1260185133Smarius found = 0; 1261185133Smarius pci_devclass = devclass_find("pci"); 1262185133Smarius for (cdev = child; cdev != dev; cdev = pdev) { 1263185133Smarius pdev = device_get_parent(cdev); 1264185133Smarius if (pcidev == NULL) { 1265185133Smarius if (device_get_devclass(pdev) != pci_devclass) 1266185133Smarius continue; 1267185133Smarius pcidev = cdev; 1268185133Smarius continue; 1269185133Smarius } 1270185133Smarius if (pci_get_class(cdev) == PCIC_BRIDGE && 1271185133Smarius pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1272185133Smarius found = 1; 1273185133Smarius } 1274185133Smarius if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1275183423Smarius sds = malloc(sizeof(*sds), M_DEVBUF, M_NOWAIT | M_ZERO); 1276183423Smarius if (sds == NULL) 1277183423Smarius return (ENOMEM); 1278185133Smarius if (found != 0 && pcidev != NULL) { 1279185133Smarius sds->sds_sc = sc; 1280185133Smarius sds->sds_arg = arg; 1281185133Smarius sds->sds_ppb = 1282185133Smarius device_get_parent(device_get_parent(pcidev)); 1283185133Smarius sds->sds_bus = pci_get_bus(pcidev); 1284185133Smarius sds->sds_slot = pci_get_slot(pcidev); 1285185133Smarius sds->sds_func = pci_get_function(pcidev); 1286185133Smarius sds->sds_syncval = 1ULL << INTINO(vec); 1287185133Smarius if (bootverbose) 1288185133Smarius device_printf(dev, "installed DMA sync " 1289185133Smarius "wrapper for device %d.%d on bus %d\n", 1290185133Smarius sds->sds_slot, sds->sds_func, 1291185133Smarius sds->sds_bus); 1292185133Smarius 1293185133Smarius#define DMA_SYNC_STUB \ 1294185133Smarius (sc->sc_mode == SCHIZO_MODE_SCZ ? schizo_dma_sync_stub : \ 1295185133Smarius ichip_dma_sync_stub) 1296185133Smarius 1297185133Smarius if (intr == NULL) { 1298185133Smarius sds->sds_handler = filt; 1299185133Smarius error = bus_generic_setup_intr(dev, child, 1300185133Smarius ires, flags, DMA_SYNC_STUB, intr, sds, 1301185133Smarius cookiep); 1302185133Smarius } else { 1303185133Smarius sds->sds_handler = (driver_filter_t *)intr; 1304185133Smarius error = bus_generic_setup_intr(dev, child, 1305185133Smarius ires, flags, filt, (driver_intr_t *) 1306185133Smarius DMA_SYNC_STUB, sds, cookiep); 1307185133Smarius } 1308185133Smarius 1309185133Smarius#undef DMA_SYNC_STUB 1310185133Smarius 1311185133Smarius } else 1312183423Smarius error = bus_generic_setup_intr(dev, child, ires, 1313185133Smarius flags, filt, intr, arg, cookiep); 1314183423Smarius if (error != 0) { 1315183423Smarius free(sds, M_DEVBUF); 1316183423Smarius return (error); 1317183423Smarius } 1318183423Smarius sds->sds_cookie = *cookiep; 1319183423Smarius *cookiep = sds; 1320183423Smarius return (error); 1321185133Smarius } else if (found != 0) 1322185133Smarius device_printf(dev, "WARNING: using devices behind PCI-PCI " 1323186290Smarius "bridges may cause data corruption\n"); 1324183423Smarius return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1325183423Smarius arg, cookiep)); 1326183423Smarius} 1327183423Smarius 1328183423Smariusstatic int 1329183423Smariusschizo_teardown_intr(device_t dev, device_t child, struct resource *vec, 1330183423Smarius void *cookie) 1331183423Smarius{ 1332185133Smarius struct schizo_dma_sync *sds; 1333183423Smarius struct schizo_softc *sc; 1334183423Smarius int error; 1335183423Smarius 1336183423Smarius sc = device_get_softc(dev); 1337185133Smarius if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1338183423Smarius sds = cookie; 1339183423Smarius error = bus_generic_teardown_intr(dev, child, vec, 1340183423Smarius sds->sds_cookie); 1341183423Smarius if (error == 0) 1342183423Smarius free(sds, M_DEVBUF); 1343183423Smarius return (error); 1344183423Smarius } 1345183423Smarius return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1346183423Smarius} 1347183423Smarius 1348200948Smariusstatic int 1349200948Smariusschizo_describe_intr(device_t dev, device_t child, struct resource *vec, 1350200948Smarius void *cookie, const char *descr) 1351200948Smarius{ 1352200948Smarius struct schizo_softc *sc; 1353200948Smarius 1354200948Smarius sc = device_get_softc(dev); 1355200948Smarius if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) 1356200948Smarius cookie = ((struct schizo_dma_sync *)cookie)->sds_cookie; 1357200948Smarius return (bus_generic_describe_intr(dev, child, vec, cookie, descr)); 1358200948Smarius} 1359200948Smarius 1360183423Smariusstatic struct resource * 1361183423Smariusschizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1362183423Smarius u_long start, u_long end, u_long count, u_int flags) 1363183423Smarius{ 1364183423Smarius struct schizo_softc *sc; 1365183423Smarius struct resource *rv; 1366183423Smarius struct rman *rm; 1367183423Smarius bus_space_tag_t bt; 1368183423Smarius bus_space_handle_t bh; 1369183423Smarius int needactivate = flags & RF_ACTIVE; 1370183423Smarius 1371183423Smarius flags &= ~RF_ACTIVE; 1372183423Smarius 1373183423Smarius sc = device_get_softc(bus); 1374183423Smarius if (type == SYS_RES_IRQ) { 1375183423Smarius /* 1376183423Smarius * XXX: Don't accept blank ranges for now, only single 1377183423Smarius * interrupts. The other case should not happen with 1378183423Smarius * the MI PCI code... 1379183423Smarius * XXX: This may return a resource that is out of the 1380183423Smarius * range that was specified. Is this correct...? 1381183423Smarius */ 1382183423Smarius if (start != end) 1383183423Smarius panic("%s: XXX: interrupt range", __func__); 1384183423Smarius start = end = INTMAP_VEC(sc->sc_ign, end); 1385201199Smarius return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, 1386201199Smarius type, rid, start, end, count, flags)); 1387183423Smarius } 1388183423Smarius switch (type) { 1389183423Smarius case SYS_RES_MEMORY: 1390183423Smarius rm = &sc->sc_pci_mem_rman; 1391183423Smarius bt = sc->sc_pci_memt; 1392183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1393183423Smarius break; 1394183423Smarius case SYS_RES_IOPORT: 1395183423Smarius rm = &sc->sc_pci_io_rman; 1396183423Smarius bt = sc->sc_pci_iot; 1397183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1398183423Smarius break; 1399183423Smarius default: 1400183423Smarius return (NULL); 1401183423Smarius /* NOTREACHED */ 1402183423Smarius } 1403183423Smarius 1404183423Smarius rv = rman_reserve_resource(rm, start, end, count, flags, child); 1405183423Smarius if (rv == NULL) 1406183423Smarius return (NULL); 1407183423Smarius rman_set_rid(rv, *rid); 1408183423Smarius bh += rman_get_start(rv); 1409183423Smarius rman_set_bustag(rv, bt); 1410183423Smarius rman_set_bushandle(rv, bh); 1411183423Smarius 1412183423Smarius if (needactivate) { 1413183423Smarius if (bus_activate_resource(child, type, *rid, rv)) { 1414183423Smarius rman_release_resource(rv); 1415183423Smarius return (NULL); 1416183423Smarius } 1417183423Smarius } 1418183423Smarius return (rv); 1419183423Smarius} 1420183423Smarius 1421183423Smariusstatic int 1422183423Smariusschizo_activate_resource(device_t bus, device_t child, int type, int rid, 1423183423Smarius struct resource *r) 1424183423Smarius{ 1425183423Smarius void *p; 1426183423Smarius int error; 1427183423Smarius 1428183423Smarius if (type == SYS_RES_IRQ) 1429183423Smarius return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1430183423Smarius type, rid, r)); 1431183423Smarius if (type == SYS_RES_MEMORY) { 1432183423Smarius /* 1433185133Smarius * Need to memory-map the device space, as some drivers 1434185133Smarius * depend on the virtual address being set and usable. 1435183423Smarius */ 1436183423Smarius error = sparc64_bus_mem_map(rman_get_bustag(r), 1437183423Smarius rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1438183423Smarius if (error != 0) 1439183423Smarius return (error); 1440183423Smarius rman_set_virtual(r, p); 1441183423Smarius } 1442183423Smarius return (rman_activate_resource(r)); 1443183423Smarius} 1444183423Smarius 1445183423Smariusstatic int 1446183423Smariusschizo_deactivate_resource(device_t bus, device_t child, int type, int rid, 1447183423Smarius struct resource *r) 1448183423Smarius{ 1449183423Smarius 1450183423Smarius if (type == SYS_RES_IRQ) 1451183423Smarius return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1452183423Smarius type, rid, r)); 1453183423Smarius if (type == SYS_RES_MEMORY) { 1454183423Smarius sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1455183423Smarius rman_set_virtual(r, NULL); 1456183423Smarius } 1457183423Smarius return (rman_deactivate_resource(r)); 1458183423Smarius} 1459183423Smarius 1460183423Smariusstatic int 1461183423Smariusschizo_release_resource(device_t bus, device_t child, int type, int rid, 1462183423Smarius struct resource *r) 1463183423Smarius{ 1464183423Smarius int error; 1465183423Smarius 1466183423Smarius if (type == SYS_RES_IRQ) 1467183423Smarius return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1468183423Smarius type, rid, r)); 1469183423Smarius if (rman_get_flags(r) & RF_ACTIVE) { 1470183423Smarius error = bus_deactivate_resource(child, type, rid, r); 1471183423Smarius if (error) 1472183423Smarius return (error); 1473183423Smarius } 1474183423Smarius return (rman_release_resource(r)); 1475183423Smarius} 1476183423Smarius 1477183423Smariusstatic bus_dma_tag_t 1478183423Smariusschizo_get_dma_tag(device_t bus, device_t child) 1479183423Smarius{ 1480183423Smarius struct schizo_softc *sc; 1481183423Smarius 1482183423Smarius sc = device_get_softc(bus); 1483183423Smarius return (sc->sc_pci_dmat); 1484183423Smarius} 1485183423Smarius 1486183423Smariusstatic phandle_t 1487183423Smariusschizo_get_node(device_t bus, device_t dev) 1488183423Smarius{ 1489183423Smarius struct schizo_softc *sc; 1490183423Smarius 1491183423Smarius sc = device_get_softc(bus); 1492183423Smarius /* We only have one child, the PCI bus, which needs our own node. */ 1493183423Smarius return (sc->sc_node); 1494183423Smarius} 1495183423Smarius 1496183423Smariusstatic bus_space_tag_t 1497183423Smariusschizo_alloc_bus_tag(struct schizo_softc *sc, int type) 1498183423Smarius{ 1499183423Smarius bus_space_tag_t bt; 1500183423Smarius 1501201199Smarius bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1502183423Smarius M_NOWAIT | M_ZERO); 1503183423Smarius if (bt == NULL) 1504183423Smarius panic("%s: out of memory", __func__); 1505183423Smarius 1506183423Smarius bt->bst_cookie = sc; 1507183423Smarius bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1508183423Smarius bt->bst_type = type; 1509183423Smarius return (bt); 1510183423Smarius} 1511183423Smarius 1512183423Smariusstatic u_int 1513183423Smariusschizo_get_timecount(struct timecounter *tc) 1514183423Smarius{ 1515183423Smarius struct schizo_softc *sc; 1516183423Smarius 1517183423Smarius sc = tc->tc_priv; 1518183423Smarius return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1519183423Smarius (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)); 1520183423Smarius} 1521