schizo.c revision 206018
1183423Smarius/*- 2183423Smarius * Copyright (c) 1999, 2000 Matthew R. Green 3183423Smarius * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4183423Smarius * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org> 5183423Smarius * All rights reserved. 6183423Smarius * 7183423Smarius * Redistribution and use in source and binary forms, with or without 8183423Smarius * modification, are permitted provided that the following conditions 9183423Smarius * are met: 10183423Smarius * 1. Redistributions of source code must retain the above copyright 11183423Smarius * notice, this list of conditions and the following disclaimer. 12183423Smarius * 2. Redistributions in binary form must reproduce the above copyright 13183423Smarius * notice, this list of conditions and the following disclaimer in the 14183423Smarius * documentation and/or other materials provided with the distribution. 15183423Smarius * 3. The name of the author may not be used to endorse or promote products 16183423Smarius * derived from this software without specific prior written permission. 17183423Smarius * 18183423Smarius * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19183423Smarius * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20183423Smarius * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21183423Smarius * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22183423Smarius * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23183423Smarius * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24183423Smarius * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25183423Smarius * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26183423Smarius * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27183423Smarius * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28183423Smarius * SUCH DAMAGE. 29183423Smarius * 30183423Smarius * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31183423Smarius * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32183423Smarius */ 33183423Smarius 34183423Smarius#include <sys/cdefs.h> 35183423Smarius__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 206018 2010-03-31 22:19:00Z marius $"); 36183423Smarius 37183423Smarius/* 38183423Smarius * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to 39183423Smarius * PCI 2.2 bridges 40183423Smarius */ 41183423Smarius 42183423Smarius#include "opt_ofw_pci.h" 43183423Smarius#include "opt_schizo.h" 44183423Smarius 45183423Smarius#include <sys/param.h> 46183423Smarius#include <sys/systm.h> 47183423Smarius#include <sys/bus.h> 48183423Smarius#include <sys/kernel.h> 49183423Smarius#include <sys/lock.h> 50183423Smarius#include <sys/malloc.h> 51183423Smarius#include <sys/module.h> 52183423Smarius#include <sys/mutex.h> 53183423Smarius#include <sys/pcpu.h> 54183423Smarius#include <sys/rman.h> 55185133Smarius#include <sys/time.h> 56183423Smarius#include <sys/timetc.h> 57183423Smarius 58183423Smarius#include <dev/ofw/ofw_bus.h> 59183423Smarius#include <dev/ofw/ofw_pci.h> 60183423Smarius#include <dev/ofw/openfirm.h> 61183423Smarius 62183423Smarius#include <machine/bus.h> 63183423Smarius#include <machine/bus_common.h> 64183423Smarius#include <machine/bus_private.h> 65183423Smarius#include <machine/fsr.h> 66183423Smarius#include <machine/iommureg.h> 67183423Smarius#include <machine/iommuvar.h> 68183423Smarius#include <machine/resource.h> 69183423Smarius 70183423Smarius#include <dev/pci/pcireg.h> 71183423Smarius#include <dev/pci/pcivar.h> 72183423Smarius 73183423Smarius#include <sparc64/pci/ofw_pci.h> 74183423Smarius#include <sparc64/pci/schizoreg.h> 75183423Smarius#include <sparc64/pci/schizovar.h> 76183423Smarius 77183423Smarius#include "pcib_if.h" 78183423Smarius 79183423Smariusstatic const struct schizo_desc *schizo_get_desc(device_t); 80183423Smariusstatic void schizo_set_intr(struct schizo_softc *, u_int, u_int, 81183423Smarius driver_filter_t); 82185133Smariusstatic driver_filter_t schizo_dma_sync_stub; 83185133Smariusstatic driver_filter_t ichip_dma_sync_stub; 84183423Smariusstatic void schizo_intr_enable(void *); 85183423Smariusstatic void schizo_intr_disable(void *); 86183423Smariusstatic void schizo_intr_assign(void *); 87183423Smariusstatic void schizo_intr_clear(void *); 88185133Smariusstatic int schizo_intr_register(struct schizo_softc *sc, u_int ino); 89183423Smariusstatic int schizo_get_intrmap(struct schizo_softc *, u_int, 90183423Smarius bus_addr_t *, bus_addr_t *); 91183423Smariusstatic bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int); 92183423Smariusstatic timecounter_get_t schizo_get_timecount; 93183423Smarius 94183423Smarius/* Interrupt handlers */ 95183423Smariusstatic driver_filter_t schizo_pci_bus; 96183423Smariusstatic driver_filter_t schizo_ue; 97183423Smariusstatic driver_filter_t schizo_ce; 98183423Smariusstatic driver_filter_t schizo_host_bus; 99185133Smariusstatic driver_filter_t schizo_cdma; 100183423Smarius 101183423Smarius/* IOMMU support */ 102183423Smariusstatic void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 103183423Smarius 104183423Smarius/* 105183423Smarius * Methods 106183423Smarius */ 107183423Smariusstatic device_probe_t schizo_probe; 108183423Smariusstatic device_attach_t schizo_attach; 109183423Smariusstatic bus_read_ivar_t schizo_read_ivar; 110183423Smariusstatic bus_setup_intr_t schizo_setup_intr; 111183423Smariusstatic bus_teardown_intr_t schizo_teardown_intr; 112183423Smariusstatic bus_alloc_resource_t schizo_alloc_resource; 113183423Smariusstatic bus_activate_resource_t schizo_activate_resource; 114183423Smariusstatic bus_deactivate_resource_t schizo_deactivate_resource; 115183423Smariusstatic bus_release_resource_t schizo_release_resource; 116200948Smariusstatic bus_describe_intr_t schizo_describe_intr; 117183423Smariusstatic bus_get_dma_tag_t schizo_get_dma_tag; 118183423Smariusstatic pcib_maxslots_t schizo_maxslots; 119183423Smariusstatic pcib_read_config_t schizo_read_config; 120183423Smariusstatic pcib_write_config_t schizo_write_config; 121183423Smariusstatic pcib_route_interrupt_t schizo_route_interrupt; 122183423Smariusstatic ofw_bus_get_node_t schizo_get_node; 123183423Smarius 124183423Smariusstatic device_method_t schizo_methods[] = { 125183423Smarius /* Device interface */ 126183423Smarius DEVMETHOD(device_probe, schizo_probe), 127183423Smarius DEVMETHOD(device_attach, schizo_attach), 128183423Smarius DEVMETHOD(device_shutdown, bus_generic_shutdown), 129183423Smarius DEVMETHOD(device_suspend, bus_generic_suspend), 130183423Smarius DEVMETHOD(device_resume, bus_generic_resume), 131183423Smarius 132183423Smarius /* Bus interface */ 133183423Smarius DEVMETHOD(bus_print_child, bus_generic_print_child), 134183423Smarius DEVMETHOD(bus_read_ivar, schizo_read_ivar), 135183423Smarius DEVMETHOD(bus_setup_intr, schizo_setup_intr), 136183423Smarius DEVMETHOD(bus_teardown_intr, schizo_teardown_intr), 137183423Smarius DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 138183423Smarius DEVMETHOD(bus_activate_resource, schizo_activate_resource), 139183423Smarius DEVMETHOD(bus_deactivate_resource, schizo_deactivate_resource), 140183423Smarius DEVMETHOD(bus_release_resource, schizo_release_resource), 141200948Smarius DEVMETHOD(bus_describe_intr, schizo_describe_intr), 142183423Smarius DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 143183423Smarius 144183423Smarius /* pcib interface */ 145183423Smarius DEVMETHOD(pcib_maxslots, schizo_maxslots), 146183423Smarius DEVMETHOD(pcib_read_config, schizo_read_config), 147183423Smarius DEVMETHOD(pcib_write_config, schizo_write_config), 148183423Smarius DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 149183423Smarius 150183423Smarius /* ofw_bus interface */ 151183423Smarius DEVMETHOD(ofw_bus_get_node, schizo_get_node), 152183423Smarius 153190108Smarius KOBJMETHOD_END 154183423Smarius}; 155183423Smarius 156183423Smariusstatic devclass_t schizo_devclass; 157183423Smarius 158183423SmariusDEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 159183423Smarius sizeof(struct schizo_softc)); 160183423SmariusDRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0); 161183423Smarius 162183423Smariusstatic SLIST_HEAD(, schizo_softc) schizo_softcs = 163183423Smarius SLIST_HEAD_INITIALIZER(schizo_softcs); 164183423Smarius 165183423Smariusstatic const struct intr_controller schizo_ic = { 166183423Smarius schizo_intr_enable, 167183423Smarius schizo_intr_disable, 168183423Smarius schizo_intr_assign, 169183423Smarius schizo_intr_clear 170183423Smarius}; 171183423Smarius 172183423Smariusstruct schizo_icarg { 173183423Smarius struct schizo_softc *sica_sc; 174183423Smarius bus_addr_t sica_map; 175183423Smarius bus_addr_t sica_clr; 176183423Smarius}; 177183423Smarius 178185133Smariusstruct schizo_dma_sync { 179183423Smarius struct schizo_softc *sds_sc; 180183423Smarius driver_filter_t *sds_handler; 181183423Smarius void *sds_arg; 182183423Smarius void *sds_cookie; 183183423Smarius uint64_t sds_syncval; 184185133Smarius device_t sds_ppb; /* farest PCI-PCI bridge */ 185201199Smarius uint8_t sds_bus; /* bus of farest PCI dev. */ 186201199Smarius uint8_t sds_slot; /* slot of farest PCI dev. */ 187201199Smarius uint8_t sds_func; /* func. of farest PCI dev. */ 188183423Smarius}; 189183423Smarius 190183423Smarius#define SCHIZO_PERF_CNT_QLTY 100 191183423Smarius 192206018Smarius#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 193183423Smarius bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 194206018Smarius#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 195183423Smarius bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 196183423Smarius 197206018Smarius#define SCHIZO_PCI_READ_8(sc, offs) \ 198183423Smarius SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 199206018Smarius#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 200183423Smarius SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 201206018Smarius#define SCHIZO_CTRL_READ_8(sc, offs) \ 202183423Smarius SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 203206018Smarius#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 204183423Smarius SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 205206018Smarius#define SCHIZO_PCICFG_READ_8(sc, offs) \ 206183423Smarius SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 207206018Smarius#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 208183423Smarius SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 209206018Smarius#define SCHIZO_ICON_READ_8(sc, offs) \ 210183423Smarius SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 211206018Smarius#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 212183423Smarius SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 213183423Smarius 214183423Smariusstruct schizo_desc { 215183423Smarius const char *sd_string; 216183423Smarius int sd_mode; 217183423Smarius const char *sd_name; 218183423Smarius}; 219183423Smarius 220185133Smariusstatic const struct schizo_desc const schizo_compats[] = { 221183423Smarius { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 222183423Smarius { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 223183423Smarius { NULL, 0, NULL } 224183423Smarius}; 225183423Smarius 226183423Smariusstatic const struct schizo_desc * 227183423Smariusschizo_get_desc(device_t dev) 228183423Smarius{ 229183423Smarius const struct schizo_desc *desc; 230183423Smarius const char *compat; 231183423Smarius 232183423Smarius compat = ofw_bus_get_compat(dev); 233183423Smarius if (compat == NULL) 234183423Smarius return (NULL); 235183423Smarius for (desc = schizo_compats; desc->sd_string != NULL; desc++) 236183423Smarius if (strcmp(desc->sd_string, compat) == 0) 237183423Smarius return (desc); 238183423Smarius return (NULL); 239183423Smarius} 240183423Smarius 241183423Smariusstatic int 242183423Smariusschizo_probe(device_t dev) 243183423Smarius{ 244183423Smarius const char *dtype; 245183423Smarius 246183423Smarius dtype = ofw_bus_get_type(dev); 247197164Smarius if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 248183423Smarius schizo_get_desc(dev) != NULL) { 249183423Smarius device_set_desc(dev, "Sun Host-PCI bridge"); 250183423Smarius return (0); 251183423Smarius } 252183423Smarius return (ENXIO); 253183423Smarius} 254183423Smarius 255183423Smariusstatic int 256183423Smariusschizo_attach(device_t dev) 257183423Smarius{ 258183423Smarius struct ofw_pci_ranges *range; 259183423Smarius const struct schizo_desc *desc; 260183423Smarius struct schizo_softc *asc, *sc, *osc; 261183423Smarius struct timecounter *tc; 262183423Smarius uint64_t ino_bitmap, reg; 263183423Smarius phandle_t node; 264183423Smarius uint32_t prop, prop_array[2]; 265201199Smarius int i, j, mode, rid, tsbsize; 266183423Smarius 267183423Smarius sc = device_get_softc(dev); 268183423Smarius node = ofw_bus_get_node(dev); 269183423Smarius desc = schizo_get_desc(dev); 270183423Smarius mode = desc->sd_mode; 271183423Smarius 272183423Smarius sc->sc_dev = dev; 273183423Smarius sc->sc_node = node; 274183423Smarius sc->sc_mode = mode; 275185133Smarius sc->sc_flags = 0; 276183423Smarius 277183423Smarius /* 278183423Smarius * The Schizo has three register banks: 279183423Smarius * (0) per-PBM PCI configuration and status registers, but for bus B 280183423Smarius * shared with the UPA64s interrupt mapping register banks 281183423Smarius * (1) shared Schizo controller configuration and status registers 282183423Smarius * (2) per-PBM PCI configuration space 283183423Smarius * 284183423Smarius * The Tomatillo has four register banks: 285183423Smarius * (0) per-PBM PCI configuration and status registers 286183423Smarius * (1) per-PBM Tomatillo controller configuration registers, but on 287183423Smarius * machines having the `jbusppm' device shared with its Estar 288183423Smarius * register bank for bus A 289183423Smarius * (2) per-PBM PCI configuration space 290183423Smarius * (3) per-PBM interrupt concentrator registers 291183423Smarius */ 292183423Smarius sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 293183423Smarius 20) & 1; 294201199Smarius for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 295201199Smarius i++) { 296201199Smarius rid = i; 297201199Smarius sc->sc_mem_res[i] = bus_alloc_resource_any(dev, 298183423Smarius SYS_RES_MEMORY, &rid, 299183423Smarius (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 300201199Smarius i == STX_PCI) || i == STX_CTRL)) || 301183423Smarius (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 302201199Smarius i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 303201199Smarius if (sc->sc_mem_res[i] == NULL) 304183423Smarius panic("%s: could not allocate register bank %d", 305201199Smarius __func__, i); 306183423Smarius } 307183423Smarius 308183423Smarius /* 309183423Smarius * Match other Schizos that are already configured against 310183423Smarius * the controller base physical address. This will be the 311183423Smarius * same for a pair of devices that share register space. 312183423Smarius */ 313183423Smarius osc = NULL; 314183423Smarius SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 315183423Smarius if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 316183423Smarius rman_get_start(sc->sc_mem_res[STX_CTRL])) { 317183423Smarius /* Found partner. */ 318183423Smarius osc = asc; 319183423Smarius break; 320183423Smarius } 321183423Smarius } 322183423Smarius if (osc == NULL) { 323183423Smarius sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 324183423Smarius M_NOWAIT | M_ZERO); 325183423Smarius if (sc->sc_mtx == NULL) 326183423Smarius panic("%s: could not malloc mutex", __func__); 327183423Smarius mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 328183423Smarius } else { 329185133Smarius if (sc->sc_mode != SCHIZO_MODE_SCZ) 330185133Smarius panic("%s: no partner expected", __func__); 331183423Smarius if (mtx_initialized(osc->sc_mtx) == 0) 332183423Smarius panic("%s: mutex not initialized", __func__); 333183423Smarius sc->sc_mtx = osc->sc_mtx; 334183423Smarius } 335183423Smarius 336183423Smarius if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 337183423Smarius panic("%s: could not determine IGN", __func__); 338201199Smarius if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == 339201199Smarius -1) 340183423Smarius panic("%s: could not determine version", __func__); 341183423Smarius if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 342183423Smarius prop = 33000000; 343183423Smarius 344183423Smarius device_printf(dev, "%s, version %d, IGN %#x, bus %c, %dMHz\n", 345183423Smarius desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half, 346183423Smarius prop / 1000 / 1000); 347183423Smarius 348183423Smarius /* Set up the PCI interrupt retry timer. */ 349183423Smarius#ifdef SCHIZO_DEBUG 350183423Smarius device_printf(dev, "PCI IRT 0x%016llx\n", (unsigned long long) 351183423Smarius SCHIZO_PCI_READ_8(sc, STX_PCI_INTR_RETRY_TIM)); 352183423Smarius#endif 353183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_INTR_RETRY_TIM, 5); 354183423Smarius 355183423Smarius /* Set up the PCI control register. */ 356183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 357183423Smarius reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 358183423Smarius STX_PCI_CTRL_ERR_IEN | STX_PCI_CTRL_ARB_MASK; 359183423Smarius reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK); 360183423Smarius if (OF_getproplen(node, "no-bus-parking") < 0) 361183423Smarius reg |= STX_PCI_CTRL_ARB_PARK; 362183423Smarius if (mode == SCHIZO_MODE_TOM) { 363183423Smarius reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 364183423Smarius if (sc->sc_ver <= 1) /* revision <= 2.0 */ 365183423Smarius reg |= TOM_PCI_CTRL_DTO_IEN; 366183423Smarius else 367183423Smarius reg |= STX_PCI_CTRL_PTO; 368183423Smarius } 369183423Smarius#ifdef SCHIZO_DEBUG 370183423Smarius device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 371183423Smarius (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL), 372183423Smarius (unsigned long long)reg); 373183423Smarius#endif 374183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, reg); 375183423Smarius 376183423Smarius /* Set up the PCI diagnostic register. */ 377183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 378183423Smarius reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 379183423Smarius STX_PCI_DIAG_INTRSYNC_DIS); 380183423Smarius#ifdef SCHIZO_DEBUG 381183423Smarius device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 382183423Smarius (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG), 383183423Smarius (unsigned long long)reg); 384183423Smarius#endif 385183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg); 386183423Smarius 387183423Smarius /* 388183423Smarius * On Tomatillo clear the I/O prefetch lengths (workaround for a 389183423Smarius * Jalapeno bug). 390183423Smarius */ 391183423Smarius if (mode == SCHIZO_MODE_TOM) 392183423Smarius SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 393183423Smarius (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 394183423Smarius TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 395183423Smarius 396183423Smarius /* 397183423Smarius * Hunt through all the interrupt mapping regs and register 398186290Smarius * the interrupt controller for our interrupt vectors. We do 399186290Smarius * this early in order to be able to catch stray interrupts. 400186290Smarius * This is complicated by the fact that a pair of Schizo PBMs 401186290Smarius * shares one IGN. 402183423Smarius */ 403201199Smarius i = OF_getprop(node, "ino-bitmap", (void *)prop_array, 404183423Smarius sizeof(prop_array)); 405205254Smarius if (i != -1) 406205254Smarius ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 407205254Smarius else { 408205254Smarius /* 409205254Smarius * If the ino-bitmap property is missing, just provide the 410205254Smarius * default set of interrupts for this controller and let 411205254Smarius * schizo_setup_intr() take care of child interrupts. 412205254Smarius */ 413205254Smarius if (sc->sc_half == 0) 414205254Smarius ino_bitmap = (1ULL << STX_UE_INO) | 415205254Smarius (1ULL << STX_CE_INO) | 416205254Smarius (1ULL << STX_PCIERR_A_INO) | 417205254Smarius (1ULL << STX_BUS_INO); 418205254Smarius else 419205254Smarius ino_bitmap = 1ULL << STX_PCIERR_B_INO; 420205254Smarius } 421201199Smarius for (i = 0; i <= STX_MAX_INO; i++) { 422201199Smarius if ((ino_bitmap & (1ULL << i)) == 0) 423183423Smarius continue; 424201199Smarius if (i == STX_FB0_INO || i == STX_FB1_INO) 425183423Smarius /* Leave for upa(4). */ 426183423Smarius continue; 427201199Smarius j = schizo_intr_register(sc, i); 428201199Smarius if (j != 0) 429186290Smarius device_printf(dev, "could not register interrupt " 430201199Smarius "controller for INO %d (%d)\n", i, j); 431183423Smarius } 432183423Smarius 433183423Smarius /* 434183423Smarius * Setup Safari/JBus performance counter 0 in bus cycle counting 435183423Smarius * mode as timecounter. Unfortunately, this is broken with at 436183423Smarius * least the version 4 Tomatillos found in Fire V120 and Blade 437183423Smarius * 1500, which apparently actually count some different event at 438183423Smarius * ~0.5 and 3MHz respectively instead (also when running in full 439183423Smarius * power mode). Besides, one counter seems to be shared by a 440183423Smarius * "pair" of Tomatillos, too. 441183423Smarius */ 442183423Smarius if (sc->sc_half == 0) { 443183423Smarius SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_PERF, 444183423Smarius (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 445183423Smarius (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 446183423Smarius tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 447183423Smarius if (tc == NULL) 448183423Smarius panic("%s: could not malloc timecounter", __func__); 449183423Smarius tc->tc_get_timecount = schizo_get_timecount; 450183423Smarius tc->tc_poll_pps = NULL; 451183423Smarius tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 452183423Smarius if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 453183423Smarius sizeof(prop)) == -1) 454183423Smarius panic("%s: could not determine clock frequency", 455183423Smarius __func__); 456183423Smarius tc->tc_frequency = prop; 457183423Smarius tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 458183423Smarius if (mode == SCHIZO_MODE_SCZ) 459183423Smarius tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 460183423Smarius else 461183423Smarius tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 462183423Smarius tc->tc_priv = sc; 463183423Smarius tc_init(tc); 464183423Smarius } 465183423Smarius 466190108Smarius /* 467190108Smarius * Set up the IOMMU. Schizo, Tomatillo and XMITS all have 468190108Smarius * one per PBM. Schizo and XMITS additionally have a streaming 469190108Smarius * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's 470190108Smarius * affected by several errata and basically unusable though. 471190108Smarius */ 472201395Smarius sc->sc_is.is_flags = IOMMU_PRESERVE_PROM; 473183423Smarius sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 474190108Smarius sc->sc_is.is_sb[0] = sc->sc_is.is_sb[1] = 0; 475190108Smarius if (OF_getproplen(node, "no-streaming-cache") < 0 && 476190108Smarius !(sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver < 5)) 477183423Smarius sc->sc_is.is_sb[0] = STX_PCI_STRBUF; 478183423Smarius 479183423Smarius#define TSBCASE(x) \ 480183423Smarius case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 481183423Smarius tsbsize = (x); \ 482183423Smarius break; \ 483183423Smarius 484201199Smarius i = OF_getprop(node, "virtual-dma", (void *)prop_array, 485183423Smarius sizeof(prop_array)); 486201199Smarius if (i == -1 || i != sizeof(prop_array)) 487183423Smarius schizo_iommu_init(sc, 7, -1); 488183423Smarius else { 489183423Smarius switch (prop_array[1]) { 490183423Smarius TSBCASE(1); 491183423Smarius TSBCASE(2); 492183423Smarius TSBCASE(3); 493183423Smarius TSBCASE(4); 494183423Smarius TSBCASE(5); 495183423Smarius TSBCASE(6); 496183423Smarius TSBCASE(7); 497183423Smarius TSBCASE(8); 498183423Smarius default: 499183423Smarius panic("%s: unsupported DVMA size 0x%x", 500183423Smarius __func__, prop_array[1]); 501183423Smarius /* NOTREACHED */ 502183423Smarius } 503183423Smarius schizo_iommu_init(sc, tsbsize, prop_array[0]); 504183423Smarius } 505185133Smarius 506183423Smarius#undef TSBCASE 507183423Smarius 508183423Smarius /* Initialize memory and I/O rmans. */ 509183423Smarius sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 510183423Smarius sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 511183423Smarius if (rman_init(&sc->sc_pci_io_rman) != 0 || 512183423Smarius rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 513183423Smarius panic("%s: failed to set up I/O rman", __func__); 514183423Smarius sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 515183423Smarius sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 516183423Smarius if (rman_init(&sc->sc_pci_mem_rman) != 0 || 517183423Smarius rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 518183423Smarius panic("%s: failed to set up memory rman", __func__); 519183423Smarius 520201199Smarius i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range); 521183423Smarius /* 522183423Smarius * Make sure that the expected ranges are present. The 523183423Smarius * OFW_PCI_CS_MEM64 one is not currently used though. 524183423Smarius */ 525201199Smarius if (i != STX_NRANGE) 526183423Smarius panic("%s: unsupported number of ranges", __func__); 527183423Smarius /* 528183423Smarius * Find the addresses of the various bus spaces. 529183423Smarius * There should not be multiple ones of one kind. 530183423Smarius * The physical start addresses of the ranges are the configuration, 531183423Smarius * memory and I/O handles. 532183423Smarius */ 533201199Smarius for (i = 0; i < STX_NRANGE; i++) { 534201199Smarius j = OFW_PCI_RANGE_CS(&range[i]); 535201199Smarius if (sc->sc_pci_bh[j] != 0) 536201199Smarius panic("%s: duplicate range for space %d", 537201199Smarius __func__, j); 538201199Smarius sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]); 539183423Smarius } 540183423Smarius free(range, M_OFWPROP); 541183423Smarius 542183423Smarius /* Register the softc, this is needed for paired Schizos. */ 543183423Smarius SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 544183423Smarius 545183423Smarius /* Allocate our tags. */ 546183423Smarius sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 547183423Smarius sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 548183423Smarius sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 549183423Smarius if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 550183423Smarius sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr, 551183423Smarius 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 552183423Smarius panic("%s: bus_dma_tag_create failed", __func__); 553183423Smarius /* Customize the tag. */ 554183423Smarius sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 555183423Smarius sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 556183423Smarius 557183423Smarius /* 558183423Smarius * Get the bus range from the firmware. 559183423Smarius * NB: Tomatillos don't support PCI bus reenumeration. 560183423Smarius */ 561201199Smarius i = OF_getprop(node, "bus-range", (void *)prop_array, 562183423Smarius sizeof(prop_array)); 563201199Smarius if (i == -1) 564183423Smarius panic("%s: could not get bus-range", __func__); 565201199Smarius if (i != sizeof(prop_array)) 566201199Smarius panic("%s: broken bus-range (%d)", __func__, i); 567201395Smarius sc->sc_pci_secbus = prop_array[0]; 568201395Smarius sc->sc_pci_subbus = prop_array[1]; 569183423Smarius if (bootverbose) 570183423Smarius device_printf(dev, "bus range %u to %u; PCI bus %d\n", 571201395Smarius sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus); 572183423Smarius 573183423Smarius /* Clear any pending PCI error bits. */ 574183423Smarius PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 575183423Smarius PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 576183423Smarius STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 577183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, 578183423Smarius SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 579183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, 580183423Smarius SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 581183423Smarius 582183423Smarius /* 583183423Smarius * Establish handlers for interesting interrupts... 584183423Smarius * Someone at Sun clearly was smoking crack; with Schizos PCI 585183423Smarius * bus error interrupts for one PBM can be routed to the other 586183423Smarius * PBM though we obviously need to use the softc of the former 587183423Smarius * as the argument for the interrupt handler and the softc of 588183423Smarius * the latter as the argument for the interrupt controller. 589183423Smarius */ 590183423Smarius if (sc->sc_half == 0) { 591183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 592183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 593183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 594183423Smarius sica_sc == osc)) 595183423Smarius /* 596183423Smarius * We are the driver for PBM A and either also 597183423Smarius * registered the interrupt controller for us or 598183423Smarius * the driver for PBM B has probed first and 599183423Smarius * registered it for us. 600183423Smarius */ 601183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 602183423Smarius schizo_pci_bus); 603183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 604183423Smarius osc != NULL) 605183423Smarius /* 606183423Smarius * We are the driver for PBM A but registered 607183423Smarius * the interrupt controller for PBM B, i.e. the 608183423Smarius * driver for PBM B attached first but couldn't 609183423Smarius * set up a handler for PBM B. 610183423Smarius */ 611183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 612183423Smarius schizo_pci_bus); 613183423Smarius } else { 614183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 615183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 616183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 617183423Smarius sica_sc == osc)) 618183423Smarius /* 619183423Smarius * We are the driver for PBM B and either also 620183423Smarius * registered the interrupt controller for us or 621183423Smarius * the driver for PBM A has probed first and 622183423Smarius * registered it for us. 623183423Smarius */ 624183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 625183423Smarius schizo_pci_bus); 626183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 627183423Smarius osc != NULL) 628183423Smarius /* 629183423Smarius * We are the driver for PBM B but registered 630183423Smarius * the interrupt controller for PBM A, i.e. the 631183423Smarius * driver for PBM A attached first but couldn't 632183423Smarius * set up a handler for PBM A. 633183423Smarius */ 634183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 635183423Smarius schizo_pci_bus); 636183423Smarius } 637183423Smarius if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 638183423Smarius schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 639183423Smarius if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 640183423Smarius schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 641183423Smarius if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 642183423Smarius schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 643183423Smarius 644183423Smarius /* 645185133Smarius * According to the Schizo Errata I-13, consistent DMA flushing/ 646185133Smarius * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 647201126Smarius * so we can't use it and need to live with the consequences. With 648201126Smarius * Schizo version >= 5, CDMA flushing/syncing is usable but requires 649201126Smarius * the workaround described in Schizo Errata I-23. With Tomatillo 650201126Smarius * and XMITS, CDMA flushing/syncing works as expected, Tomatillo 651201126Smarius * version <= 4 (i.e. revision <= 2.3) bridges additionally require 652201126Smarius * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though. 653185133Smarius */ 654185133Smarius if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 655201199Smarius sc->sc_mode == SCHIZO_MODE_TOM || 656201199Smarius sc->sc_mode == SCHIZO_MODE_XMS) { 657185133Smarius sc->sc_flags |= SCHIZO_FLAGS_CDMA; 658185133Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ) { 659185133Smarius sc->sc_cdma_state = SCHIZO_CDMA_STATE_DONE; 660201126Smarius /* 661201126Smarius * Some firmware versions include the CDMA interrupt 662201126Smarius * at RID 4 but most don't. With the latter we add 663201126Smarius * it ourselves at the spare RID 5. 664201126Smarius */ 665201199Smarius i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ, 666201126Smarius 4)); 667201199Smarius if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) { 668201199Smarius (void)schizo_get_intrmap(sc, i, NULL, 669201126Smarius &sc->sc_cdma_clr); 670201199Smarius schizo_set_intr(sc, 4, i, schizo_cdma); 671201126Smarius } else { 672201199Smarius i = STX_CDMA_A_INO + sc->sc_half; 673201126Smarius if (bus_set_resource(dev, SYS_RES_IRQ, 5, 674201199Smarius INTMAP_VEC(sc->sc_ign, i), 1) != 0) 675201126Smarius panic("%s: failed to add CDMA " 676201126Smarius "interrupt", __func__); 677201199Smarius j = schizo_intr_register(sc, i); 678201199Smarius if (j != 0) 679201126Smarius panic("%s: could not register " 680201126Smarius "interrupt controller for CDMA " 681201199Smarius "(%d)", __func__, j); 682201199Smarius (void)schizo_get_intrmap(sc, i, NULL, 683201126Smarius &sc->sc_cdma_clr); 684201199Smarius schizo_set_intr(sc, 5, i, schizo_cdma); 685201126Smarius } 686185133Smarius } 687185133Smarius if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 688185133Smarius sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 689185133Smarius } 690185133Smarius 691185133Smarius /* 692183423Smarius * Set the latency timer register as this isn't always done by the 693183423Smarius * firmware. 694183423Smarius */ 695183423Smarius PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 696183423Smarius PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 697183423Smarius 698183423Smarius ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 699183423Smarius 700205254Smarius /* 701205254Smarius * At least when booting Fire V890 from disk a Schizo comes up with 702205254Smarius * a PCI bus error residing which triggers as soon as we register 703205254Smarius * schizo_pci_bus() even when clearing it from all involved registers 704205254Smarius * beforehand (but is quiet once it has fired). Thus we make PCI bus 705205254Smarius * errors non-fatal until we actually touch the bus. 706205254Smarius */ 707205254Smarius sc->sc_flags |= SCHIZO_FLAGS_ARMED; 708183423Smarius device_add_child(dev, "pci", -1); 709183423Smarius return (bus_generic_attach(dev)); 710183423Smarius} 711183423Smarius 712183423Smariusstatic void 713183423Smariusschizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 714183423Smarius driver_filter_t handler) 715183423Smarius{ 716183423Smarius u_long vec; 717183423Smarius int rid; 718183423Smarius 719183423Smarius rid = index; 720201199Smarius sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 721201199Smarius SYS_RES_IRQ, &rid, RF_ACTIVE); 722183423Smarius if (sc->sc_irq_res[index] == NULL || 723201199Smarius INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino || 724201199Smarius INTIGN(vec) != sc->sc_ign || 725183423Smarius intr_vectors[vec].iv_ic != &schizo_ic || 726185133Smarius bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 727185133Smarius INTR_TYPE_MISC | INTR_FAST, handler, NULL, sc, 728185133Smarius &sc->sc_ihand[index]) != 0) 729183423Smarius panic("%s: failed to set up interrupt %d", __func__, index); 730183423Smarius} 731183423Smarius 732183423Smariusstatic int 733185133Smariusschizo_intr_register(struct schizo_softc *sc, u_int ino) 734185133Smarius{ 735185133Smarius struct schizo_icarg *sica; 736185133Smarius bus_addr_t intrclr, intrmap; 737185133Smarius int error; 738185133Smarius 739185133Smarius if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 740185133Smarius return (ENXIO); 741185133Smarius sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 742185133Smarius if (sica == NULL) 743185133Smarius return (ENOMEM); 744185133Smarius sica->sica_sc = sc; 745185133Smarius sica->sica_map = intrmap; 746185133Smarius sica->sica_clr = intrclr; 747185133Smarius#ifdef SCHIZO_DEBUG 748185133Smarius device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 749185133Smarius ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 750185133Smarius (u_long)intrclr); 751185133Smarius#endif 752185133Smarius error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 753185133Smarius &schizo_ic, sica)); 754185133Smarius if (error != 0) 755185133Smarius free(sica, M_DEVBUF); 756185133Smarius return (error); 757185133Smarius} 758185133Smarius 759185133Smariusstatic int 760201199Smariusschizo_get_intrmap(struct schizo_softc *sc, u_int ino, 761201199Smarius bus_addr_t *intrmapptr, bus_addr_t *intrclrptr) 762183423Smarius{ 763183423Smarius bus_addr_t intrclr, intrmap; 764183423Smarius uint64_t mr; 765183423Smarius 766183423Smarius /* 767183423Smarius * XXX we only look for INOs rather than INRs since the firmware 768183423Smarius * may not provide the IGN and the IGN is constant for all devices 769183423Smarius * on that PCI controller. 770183423Smarius */ 771183423Smarius 772183423Smarius if (ino > STX_MAX_INO) { 773183423Smarius device_printf(sc->sc_dev, "out of range INO %d requested\n", 774183423Smarius ino); 775183423Smarius return (0); 776183423Smarius } 777183423Smarius 778183423Smarius intrmap = STX_PCI_IMAP_BASE + (ino << 3); 779183423Smarius intrclr = STX_PCI_ICLR_BASE + (ino << 3); 780183423Smarius mr = SCHIZO_PCI_READ_8(sc, intrmap); 781183423Smarius if (INTINO(mr) != ino) { 782183423Smarius device_printf(sc->sc_dev, 783183423Smarius "interrupt map entry does not match INO (%d != %d)\n", 784183423Smarius (int)INTINO(mr), ino); 785183423Smarius return (0); 786183423Smarius } 787183423Smarius 788183423Smarius if (intrmapptr != NULL) 789183423Smarius *intrmapptr = intrmap; 790183423Smarius if (intrclrptr != NULL) 791183423Smarius *intrclrptr = intrclr; 792183423Smarius return (1); 793183423Smarius} 794183423Smarius 795183423Smarius/* 796183423Smarius * Interrupt handlers 797183423Smarius */ 798183423Smariusstatic int 799183423Smariusschizo_pci_bus(void *arg) 800183423Smarius{ 801183423Smarius struct schizo_softc *sc = arg; 802183423Smarius uint64_t afar, afsr, csr, iommu; 803183423Smarius uint32_t status; 804183423Smarius 805183423Smarius afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 806183423Smarius afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 807183423Smarius csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 808183423Smarius iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 809183423Smarius status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 810183423Smarius STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 811205254Smarius if ((sc->sc_flags & SCHIZO_FLAGS_ARMED) == 0) 812205254Smarius goto clear_error; 813183423Smarius if ((csr & STX_PCI_CTRL_MMU_ERR) != 0) { 814183423Smarius if ((iommu & TOM_PCI_IOMMU_ERR) == 0) 815183423Smarius goto clear_error; 816183423Smarius 817183423Smarius /* These are non-fatal if target abort was signaled. */ 818183423Smarius if ((status & PCIM_STATUS_STABORT) != 0 && 819183423Smarius ((iommu & TOM_PCI_IOMMU_ERRMASK) == 820183423Smarius TOM_PCI_IOMMU_INVALID_ERR || 821183423Smarius (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) != 0 || 822183423Smarius (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) != 0)) { 823183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 824183423Smarius goto clear_error; 825183423Smarius } 826183423Smarius } 827183423Smarius 828183423Smarius panic("%s: PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 829183423Smarius "IOMMU %#llx STATUS %#llx", device_get_name(sc->sc_dev), 830183423Smarius 'A' + sc->sc_half, (unsigned long long)afar, 831183423Smarius (unsigned long long)afsr, (unsigned long long)csr, 832183423Smarius (unsigned long long)iommu, (unsigned long long)status); 833183423Smarius 834183423Smarius clear_error: 835183423Smarius if (bootverbose) 836183423Smarius device_printf(sc->sc_dev, 837183423Smarius "PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 838183423Smarius "STATUS %#llx", 'A' + sc->sc_half, 839183423Smarius (unsigned long long)afar, (unsigned long long)afsr, 840183423Smarius (unsigned long long)csr, (unsigned long long)status); 841183423Smarius /* Clear the error bits that we caught. */ 842183423Smarius PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 843183423Smarius STX_CS_FUNC, PCIR_STATUS, status, 2); 844183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 845183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 846183423Smarius return (FILTER_HANDLED); 847183423Smarius} 848183423Smarius 849183423Smariusstatic int 850183423Smariusschizo_ue(void *arg) 851183423Smarius{ 852183423Smarius struct schizo_softc *sc = arg; 853183423Smarius uint64_t afar, afsr; 854183423Smarius int i; 855183423Smarius 856183423Smarius mtx_lock_spin(sc->sc_mtx); 857183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 858183423Smarius for (i = 0; i < 1000; i++) 859183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 860183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 861183423Smarius break; 862183423Smarius mtx_unlock_spin(sc->sc_mtx); 863183423Smarius panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 864183423Smarius device_get_name(sc->sc_dev), (unsigned long long)afar, 865183423Smarius (unsigned long long)afsr); 866183423Smarius return (FILTER_HANDLED); 867183423Smarius} 868183423Smarius 869183423Smariusstatic int 870183423Smariusschizo_ce(void *arg) 871183423Smarius{ 872183423Smarius struct schizo_softc *sc = arg; 873183423Smarius uint64_t afar, afsr; 874183423Smarius int i; 875183423Smarius 876183423Smarius mtx_lock_spin(sc->sc_mtx); 877183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 878183423Smarius for (i = 0; i < 1000; i++) 879183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 880183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 881183423Smarius break; 882183423Smarius device_printf(sc->sc_dev, 883183423Smarius "correctable DMA error AFAR %#llx AFSR %#llx\n", 884183423Smarius (unsigned long long)afar, (unsigned long long)afsr); 885183423Smarius /* Clear the error bits that we caught. */ 886183423Smarius SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 887183423Smarius mtx_unlock_spin(sc->sc_mtx); 888183423Smarius return (FILTER_HANDLED); 889183423Smarius} 890183423Smarius 891183423Smariusstatic int 892183423Smariusschizo_host_bus(void *arg) 893183423Smarius{ 894183423Smarius struct schizo_softc *sc = arg; 895183423Smarius uint64_t errlog; 896183423Smarius 897183423Smarius errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 898183423Smarius panic("%s: %s error %#llx", device_get_name(sc->sc_dev), 899183423Smarius sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 900183423Smarius (unsigned long long)errlog); 901183423Smarius return (FILTER_HANDLED); 902183423Smarius} 903183423Smarius 904185133Smariusstatic int 905185133Smariusschizo_cdma(void *arg) 906185133Smarius{ 907185133Smarius struct schizo_softc *sc = arg; 908185133Smarius 909185133Smarius atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE); 910185133Smarius return (FILTER_HANDLED); 911185133Smarius} 912185133Smarius 913183423Smariusstatic void 914183423Smariusschizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 915183423Smarius{ 916183423Smarius 917183423Smarius /* Punch in our copies. */ 918183423Smarius sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 919183423Smarius sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 920183423Smarius sc->sc_is.is_iommu = STX_PCI_IOMMU; 921183423Smarius sc->sc_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 922183423Smarius sc->sc_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 923183423Smarius sc->sc_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 924183423Smarius sc->sc_is.is_dva = STX_PCI_IOMMU_SVADIAG; 925183423Smarius sc->sc_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 926183423Smarius 927183423Smarius iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, tsbsize, 928183423Smarius dvmabase, 0); 929183423Smarius} 930183423Smarius 931183423Smariusstatic int 932183423Smariusschizo_maxslots(device_t dev) 933183423Smarius{ 934183423Smarius struct schizo_softc *sc; 935183423Smarius 936183423Smarius sc = device_get_softc(dev); 937183423Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ) 938183423Smarius return (sc->sc_half == 0 ? 4 : 6); 939183423Smarius 940183423Smarius /* XXX: is this correct? */ 941183423Smarius return (PCI_SLOTMAX); 942183423Smarius} 943183423Smarius 944183423Smariusstatic uint32_t 945183423Smariusschizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 946183423Smarius int width) 947183423Smarius{ 948183423Smarius struct schizo_softc *sc; 949183423Smarius bus_space_handle_t bh; 950183423Smarius u_long offset = 0; 951183423Smarius uint32_t r, wrd; 952183423Smarius int i; 953183423Smarius uint16_t shrt; 954183423Smarius uint8_t byte; 955183423Smarius 956183423Smarius sc = device_get_softc(dev); 957201395Smarius if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 958201395Smarius slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 959201395Smarius return (-1); 960183423Smarius 961183423Smarius /* 962183423Smarius * The Schizo bridges contain a dupe of their header at 0x80. 963183423Smarius */ 964183423Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 965183423Smarius slot == STX_CS_DEVICE && func == STX_CS_FUNC && 966183423Smarius reg + width > 0x80) 967183423Smarius return (0); 968183423Smarius 969183423Smarius offset = STX_CONF_OFF(bus, slot, func, reg); 970183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 971183423Smarius switch (width) { 972183423Smarius case 1: 973183423Smarius i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 974183423Smarius r = byte; 975183423Smarius break; 976183423Smarius case 2: 977183423Smarius i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 978183423Smarius r = shrt; 979183423Smarius break; 980183423Smarius case 4: 981183423Smarius i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 982183423Smarius r = wrd; 983183423Smarius break; 984183423Smarius default: 985183423Smarius panic("%s: bad width", __func__); 986183423Smarius /* NOTREACHED */ 987183423Smarius } 988183423Smarius 989183423Smarius if (i) { 990183423Smarius#ifdef SCHIZO_DEBUG 991183423Smarius printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 992183423Smarius __func__, bus, slot, func, reg); 993183423Smarius#endif 994183423Smarius r = -1; 995183423Smarius } 996183423Smarius return (r); 997183423Smarius} 998183423Smarius 999183423Smariusstatic void 1000201199Smariusschizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1001201199Smarius u_int reg, uint32_t val, int width) 1002183423Smarius{ 1003183423Smarius struct schizo_softc *sc; 1004183423Smarius bus_space_handle_t bh; 1005183423Smarius u_long offset = 0; 1006183423Smarius 1007183423Smarius sc = device_get_softc(dev); 1008201395Smarius if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus || 1009201395Smarius slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX) 1010201395Smarius return; 1011201395Smarius 1012183423Smarius offset = STX_CONF_OFF(bus, slot, func, reg); 1013183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1014183423Smarius switch (width) { 1015183423Smarius case 1: 1016183423Smarius bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1017183423Smarius break; 1018183423Smarius case 2: 1019183423Smarius bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1020183423Smarius break; 1021183423Smarius case 4: 1022183423Smarius bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1023183423Smarius break; 1024183423Smarius default: 1025183423Smarius panic("%s: bad width", __func__); 1026183423Smarius /* NOTREACHED */ 1027183423Smarius } 1028183423Smarius} 1029183423Smarius 1030183423Smariusstatic int 1031183423Smariusschizo_route_interrupt(device_t bridge, device_t dev, int pin) 1032183423Smarius{ 1033183423Smarius struct schizo_softc *sc; 1034183423Smarius struct ofw_pci_register reg; 1035183423Smarius ofw_pci_intr_t pintr, mintr; 1036183423Smarius uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 1037183423Smarius 1038183423Smarius sc = device_get_softc(bridge); 1039183423Smarius pintr = pin; 1040201199Smarius if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1041201199Smarius ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), 1042201199Smarius maskbuf)) 1043183423Smarius return (mintr); 1044183423Smarius 1045183423Smarius device_printf(bridge, "could not route pin %d for device %d.%d\n", 1046183423Smarius pin, pci_get_slot(dev), pci_get_function(dev)); 1047183423Smarius return (PCI_INVALID_IRQ); 1048183423Smarius} 1049183423Smarius 1050183423Smariusstatic int 1051183423Smariusschizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1052183423Smarius{ 1053183423Smarius struct schizo_softc *sc; 1054183423Smarius 1055183423Smarius sc = device_get_softc(dev); 1056183423Smarius switch (which) { 1057183423Smarius case PCIB_IVAR_DOMAIN: 1058183423Smarius *result = device_get_unit(dev); 1059183423Smarius return (0); 1060183423Smarius case PCIB_IVAR_BUS: 1061183423Smarius *result = sc->sc_pci_secbus; 1062183423Smarius return (0); 1063183423Smarius } 1064183423Smarius return (ENOENT); 1065183423Smarius} 1066183423Smarius 1067185133Smariusstatic int 1068185133Smariusschizo_dma_sync_stub(void *arg) 1069185133Smarius{ 1070185133Smarius struct timeval cur, end; 1071185133Smarius struct schizo_dma_sync *sds = arg; 1072185133Smarius struct schizo_softc *sc = sds->sds_sc; 1073185133Smarius uint32_t state; 1074185133Smarius 1075185133Smarius (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1076185133Smarius sds->sds_func, PCIR_VENDOR, 2); 1077201199Smarius for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, 1078201199Smarius SCHIZO_CDMA_STATE_DONE, SCHIZO_CDMA_STATE_PENDING) == 0;) 1079185133Smarius ; 1080206018Smarius SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, INTCLR_RECEIVED); 1081185133Smarius microuptime(&cur); 1082185133Smarius end.tv_sec = 1; 1083185133Smarius end.tv_usec = 0; 1084185133Smarius timevaladd(&end, &cur); 1085185133Smarius for (; (state = atomic_load_32(&sc->sc_cdma_state)) != 1086185133Smarius SCHIZO_CDMA_STATE_DONE && timevalcmp(&cur, &end, <=);) 1087185133Smarius microuptime(&cur); 1088185133Smarius if (state != SCHIZO_CDMA_STATE_DONE) 1089185133Smarius panic("%s: DMA does not sync", __func__); 1090185133Smarius return (sds->sds_handler(sds->sds_arg)); 1091185133Smarius} 1092185133Smarius 1093183423Smarius#define VIS_BLOCKSIZE 64 1094183423Smarius 1095183423Smariusstatic int 1096185133Smariusichip_dma_sync_stub(void *arg) 1097183423Smarius{ 1098183423Smarius static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 1099185133Smarius struct timeval cur, end; 1100185133Smarius struct schizo_dma_sync *sds = arg; 1101183423Smarius struct schizo_softc *sc = sds->sds_sc; 1102184428Smarius register_t reg, s; 1103183423Smarius 1104185133Smarius (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1105185133Smarius sds->sds_func, PCIR_VENDOR, 2); 1106184428Smarius SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, sds->sds_syncval); 1107185133Smarius microuptime(&cur); 1108185133Smarius end.tv_sec = 1; 1109185133Smarius end.tv_usec = 0; 1110185133Smarius timevaladd(&end, &cur); 1111185133Smarius for (; ((reg = SCHIZO_PCI_READ_8(sc, TOMXMS_PCI_DMA_SYNC_PEND)) & 1112185133Smarius sds->sds_syncval) != 0 && timevalcmp(&cur, &end, <=);) 1113185133Smarius microuptime(&cur); 1114185133Smarius if ((reg & sds->sds_syncval) != 0) 1115185133Smarius panic("%s: DMA does not sync", __func__); 1116183423Smarius 1117185133Smarius if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1118184428Smarius s = intr_disable(); 1119183423Smarius reg = rd(fprs); 1120183423Smarius wr(fprs, reg | FPRS_FEF, 0); 1121184428Smarius __asm __volatile("stda %%f0, [%0] %1" 1122183423Smarius : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 1123184428Smarius membar(Sync); 1124183423Smarius wr(fprs, reg, 0); 1125184428Smarius intr_restore(s); 1126183423Smarius } 1127183423Smarius return (sds->sds_handler(sds->sds_arg)); 1128183423Smarius} 1129183423Smarius 1130183423Smariusstatic void 1131183423Smariusschizo_intr_enable(void *arg) 1132183423Smarius{ 1133183423Smarius struct intr_vector *iv = arg; 1134183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1135183423Smarius 1136183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1137183423Smarius INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1138183423Smarius} 1139183423Smarius 1140183423Smariusstatic void 1141183423Smariusschizo_intr_disable(void *arg) 1142183423Smarius{ 1143183423Smarius struct intr_vector *iv = arg; 1144183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1145183423Smarius 1146183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1147183423Smarius} 1148183423Smarius 1149183423Smariusstatic void 1150183423Smariusschizo_intr_assign(void *arg) 1151183423Smarius{ 1152183423Smarius struct intr_vector *iv = arg; 1153183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1154183423Smarius 1155183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1156183423Smarius SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1157183423Smarius} 1158183423Smarius 1159183423Smariusstatic void 1160183423Smariusschizo_intr_clear(void *arg) 1161183423Smarius{ 1162183423Smarius struct intr_vector *iv = arg; 1163183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1164183423Smarius 1165206018Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE); 1166183423Smarius} 1167183423Smarius 1168183423Smariusstatic int 1169183423Smariusschizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1170183423Smarius int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1171183423Smarius void **cookiep) 1172183423Smarius{ 1173185133Smarius devclass_t pci_devclass; 1174185133Smarius device_t cdev, pdev, pcidev; 1175185133Smarius struct schizo_dma_sync *sds; 1176183423Smarius struct schizo_softc *sc; 1177183423Smarius u_long vec; 1178185133Smarius int error, found; 1179183423Smarius 1180183423Smarius sc = device_get_softc(dev); 1181183423Smarius /* 1182186290Smarius * Make sure the vector is fully specified. 1183183423Smarius */ 1184183423Smarius vec = rman_get_start(ires); 1185186290Smarius if (INTIGN(vec) != sc->sc_ign) { 1186183423Smarius device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1187183423Smarius return (EINVAL); 1188183423Smarius } 1189183423Smarius 1190186290Smarius if (intr_vectors[vec].iv_ic == &schizo_ic) { 1191186290Smarius /* 1192186290Smarius * Ensure we use the right softc in case the interrupt 1193186290Smarius * is routed to our companion PBM for some odd reason. 1194186290Smarius */ 1195186290Smarius sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 1196186290Smarius sica_sc; 1197186290Smarius } else if (intr_vectors[vec].iv_ic == NULL) { 1198186290Smarius /* 1199186290Smarius * Work around broken firmware which misses entries in 1200186290Smarius * the ino-bitmap. 1201186290Smarius */ 1202186290Smarius error = schizo_intr_register(sc, INTINO(vec)); 1203186290Smarius if (error != 0) { 1204186290Smarius device_printf(dev, "could not register interrupt " 1205186290Smarius "controller for vector 0x%lx (%d)\n", vec, error); 1206186290Smarius return (error); 1207186290Smarius } 1208190108Smarius if (bootverbose) 1209190108Smarius device_printf(dev, "belatedly registered as " 1210190108Smarius "interrupt controller for vector 0x%lx\n", vec); 1211186290Smarius } else { 1212186290Smarius device_printf(dev, 1213186290Smarius "invalid interrupt controller for vector 0x%lx\n", vec); 1214186290Smarius return (EINVAL); 1215186290Smarius } 1216186290Smarius 1217183423Smarius /* 1218185133Smarius * Install a a wrapper for CDMA flushing/syncing for devices 1219185133Smarius * behind PCI-PCI bridges if possible. 1220183423Smarius */ 1221185133Smarius pcidev = NULL; 1222185133Smarius found = 0; 1223185133Smarius pci_devclass = devclass_find("pci"); 1224185133Smarius for (cdev = child; cdev != dev; cdev = pdev) { 1225185133Smarius pdev = device_get_parent(cdev); 1226185133Smarius if (pcidev == NULL) { 1227185133Smarius if (device_get_devclass(pdev) != pci_devclass) 1228185133Smarius continue; 1229185133Smarius pcidev = cdev; 1230185133Smarius continue; 1231185133Smarius } 1232185133Smarius if (pci_get_class(cdev) == PCIC_BRIDGE && 1233185133Smarius pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1234185133Smarius found = 1; 1235185133Smarius } 1236185133Smarius if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1237183423Smarius sds = malloc(sizeof(*sds), M_DEVBUF, M_NOWAIT | M_ZERO); 1238183423Smarius if (sds == NULL) 1239183423Smarius return (ENOMEM); 1240185133Smarius if (found != 0 && pcidev != NULL) { 1241185133Smarius sds->sds_sc = sc; 1242185133Smarius sds->sds_arg = arg; 1243185133Smarius sds->sds_ppb = 1244185133Smarius device_get_parent(device_get_parent(pcidev)); 1245185133Smarius sds->sds_bus = pci_get_bus(pcidev); 1246185133Smarius sds->sds_slot = pci_get_slot(pcidev); 1247185133Smarius sds->sds_func = pci_get_function(pcidev); 1248185133Smarius sds->sds_syncval = 1ULL << INTINO(vec); 1249185133Smarius if (bootverbose) 1250185133Smarius device_printf(dev, "installed DMA sync " 1251185133Smarius "wrapper for device %d.%d on bus %d\n", 1252185133Smarius sds->sds_slot, sds->sds_func, 1253185133Smarius sds->sds_bus); 1254185133Smarius 1255185133Smarius#define DMA_SYNC_STUB \ 1256185133Smarius (sc->sc_mode == SCHIZO_MODE_SCZ ? schizo_dma_sync_stub : \ 1257185133Smarius ichip_dma_sync_stub) 1258185133Smarius 1259185133Smarius if (intr == NULL) { 1260185133Smarius sds->sds_handler = filt; 1261185133Smarius error = bus_generic_setup_intr(dev, child, 1262185133Smarius ires, flags, DMA_SYNC_STUB, intr, sds, 1263185133Smarius cookiep); 1264185133Smarius } else { 1265185133Smarius sds->sds_handler = (driver_filter_t *)intr; 1266185133Smarius error = bus_generic_setup_intr(dev, child, 1267185133Smarius ires, flags, filt, (driver_intr_t *) 1268185133Smarius DMA_SYNC_STUB, sds, cookiep); 1269185133Smarius } 1270185133Smarius 1271185133Smarius#undef DMA_SYNC_STUB 1272185133Smarius 1273185133Smarius } else 1274183423Smarius error = bus_generic_setup_intr(dev, child, ires, 1275185133Smarius flags, filt, intr, arg, cookiep); 1276183423Smarius if (error != 0) { 1277183423Smarius free(sds, M_DEVBUF); 1278183423Smarius return (error); 1279183423Smarius } 1280183423Smarius sds->sds_cookie = *cookiep; 1281183423Smarius *cookiep = sds; 1282183423Smarius return (error); 1283185133Smarius } else if (found != 0) 1284185133Smarius device_printf(dev, "WARNING: using devices behind PCI-PCI " 1285186290Smarius "bridges may cause data corruption\n"); 1286183423Smarius return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1287183423Smarius arg, cookiep)); 1288183423Smarius} 1289183423Smarius 1290183423Smariusstatic int 1291183423Smariusschizo_teardown_intr(device_t dev, device_t child, struct resource *vec, 1292183423Smarius void *cookie) 1293183423Smarius{ 1294185133Smarius struct schizo_dma_sync *sds; 1295183423Smarius struct schizo_softc *sc; 1296183423Smarius int error; 1297183423Smarius 1298183423Smarius sc = device_get_softc(dev); 1299185133Smarius if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1300183423Smarius sds = cookie; 1301183423Smarius error = bus_generic_teardown_intr(dev, child, vec, 1302183423Smarius sds->sds_cookie); 1303183423Smarius if (error == 0) 1304183423Smarius free(sds, M_DEVBUF); 1305183423Smarius return (error); 1306183423Smarius } 1307183423Smarius return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1308183423Smarius} 1309183423Smarius 1310200948Smariusstatic int 1311200948Smariusschizo_describe_intr(device_t dev, device_t child, struct resource *vec, 1312200948Smarius void *cookie, const char *descr) 1313200948Smarius{ 1314200948Smarius struct schizo_softc *sc; 1315200948Smarius 1316200948Smarius sc = device_get_softc(dev); 1317200948Smarius if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) 1318200948Smarius cookie = ((struct schizo_dma_sync *)cookie)->sds_cookie; 1319200948Smarius return (bus_generic_describe_intr(dev, child, vec, cookie, descr)); 1320200948Smarius} 1321200948Smarius 1322183423Smariusstatic struct resource * 1323183423Smariusschizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1324183423Smarius u_long start, u_long end, u_long count, u_int flags) 1325183423Smarius{ 1326183423Smarius struct schizo_softc *sc; 1327183423Smarius struct resource *rv; 1328183423Smarius struct rman *rm; 1329183423Smarius bus_space_tag_t bt; 1330183423Smarius bus_space_handle_t bh; 1331183423Smarius int needactivate = flags & RF_ACTIVE; 1332183423Smarius 1333183423Smarius flags &= ~RF_ACTIVE; 1334183423Smarius 1335183423Smarius sc = device_get_softc(bus); 1336183423Smarius if (type == SYS_RES_IRQ) { 1337183423Smarius /* 1338183423Smarius * XXX: Don't accept blank ranges for now, only single 1339183423Smarius * interrupts. The other case should not happen with 1340183423Smarius * the MI PCI code... 1341183423Smarius * XXX: This may return a resource that is out of the 1342183423Smarius * range that was specified. Is this correct...? 1343183423Smarius */ 1344183423Smarius if (start != end) 1345183423Smarius panic("%s: XXX: interrupt range", __func__); 1346183423Smarius start = end = INTMAP_VEC(sc->sc_ign, end); 1347201199Smarius return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, 1348201199Smarius type, rid, start, end, count, flags)); 1349183423Smarius } 1350183423Smarius switch (type) { 1351183423Smarius case SYS_RES_MEMORY: 1352183423Smarius rm = &sc->sc_pci_mem_rman; 1353183423Smarius bt = sc->sc_pci_memt; 1354183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1355183423Smarius break; 1356183423Smarius case SYS_RES_IOPORT: 1357183423Smarius rm = &sc->sc_pci_io_rman; 1358183423Smarius bt = sc->sc_pci_iot; 1359183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1360183423Smarius break; 1361183423Smarius default: 1362183423Smarius return (NULL); 1363183423Smarius /* NOTREACHED */ 1364183423Smarius } 1365183423Smarius 1366183423Smarius rv = rman_reserve_resource(rm, start, end, count, flags, child); 1367183423Smarius if (rv == NULL) 1368183423Smarius return (NULL); 1369183423Smarius rman_set_rid(rv, *rid); 1370183423Smarius bh += rman_get_start(rv); 1371183423Smarius rman_set_bustag(rv, bt); 1372183423Smarius rman_set_bushandle(rv, bh); 1373183423Smarius 1374183423Smarius if (needactivate) { 1375183423Smarius if (bus_activate_resource(child, type, *rid, rv)) { 1376183423Smarius rman_release_resource(rv); 1377183423Smarius return (NULL); 1378183423Smarius } 1379183423Smarius } 1380183423Smarius return (rv); 1381183423Smarius} 1382183423Smarius 1383183423Smariusstatic int 1384183423Smariusschizo_activate_resource(device_t bus, device_t child, int type, int rid, 1385183423Smarius struct resource *r) 1386183423Smarius{ 1387183423Smarius void *p; 1388183423Smarius int error; 1389183423Smarius 1390183423Smarius if (type == SYS_RES_IRQ) 1391183423Smarius return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1392183423Smarius type, rid, r)); 1393183423Smarius if (type == SYS_RES_MEMORY) { 1394183423Smarius /* 1395185133Smarius * Need to memory-map the device space, as some drivers 1396185133Smarius * depend on the virtual address being set and usable. 1397183423Smarius */ 1398183423Smarius error = sparc64_bus_mem_map(rman_get_bustag(r), 1399183423Smarius rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1400183423Smarius if (error != 0) 1401183423Smarius return (error); 1402183423Smarius rman_set_virtual(r, p); 1403183423Smarius } 1404183423Smarius return (rman_activate_resource(r)); 1405183423Smarius} 1406183423Smarius 1407183423Smariusstatic int 1408183423Smariusschizo_deactivate_resource(device_t bus, device_t child, int type, int rid, 1409183423Smarius struct resource *r) 1410183423Smarius{ 1411183423Smarius 1412183423Smarius if (type == SYS_RES_IRQ) 1413183423Smarius return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1414183423Smarius type, rid, r)); 1415183423Smarius if (type == SYS_RES_MEMORY) { 1416183423Smarius sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1417183423Smarius rman_set_virtual(r, NULL); 1418183423Smarius } 1419183423Smarius return (rman_deactivate_resource(r)); 1420183423Smarius} 1421183423Smarius 1422183423Smariusstatic int 1423183423Smariusschizo_release_resource(device_t bus, device_t child, int type, int rid, 1424183423Smarius struct resource *r) 1425183423Smarius{ 1426183423Smarius int error; 1427183423Smarius 1428183423Smarius if (type == SYS_RES_IRQ) 1429183423Smarius return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1430183423Smarius type, rid, r)); 1431183423Smarius if (rman_get_flags(r) & RF_ACTIVE) { 1432183423Smarius error = bus_deactivate_resource(child, type, rid, r); 1433183423Smarius if (error) 1434183423Smarius return (error); 1435183423Smarius } 1436183423Smarius return (rman_release_resource(r)); 1437183423Smarius} 1438183423Smarius 1439183423Smariusstatic bus_dma_tag_t 1440183423Smariusschizo_get_dma_tag(device_t bus, device_t child) 1441183423Smarius{ 1442183423Smarius struct schizo_softc *sc; 1443183423Smarius 1444183423Smarius sc = device_get_softc(bus); 1445183423Smarius return (sc->sc_pci_dmat); 1446183423Smarius} 1447183423Smarius 1448183423Smariusstatic phandle_t 1449183423Smariusschizo_get_node(device_t bus, device_t dev) 1450183423Smarius{ 1451183423Smarius struct schizo_softc *sc; 1452183423Smarius 1453183423Smarius sc = device_get_softc(bus); 1454183423Smarius /* We only have one child, the PCI bus, which needs our own node. */ 1455183423Smarius return (sc->sc_node); 1456183423Smarius} 1457183423Smarius 1458183423Smariusstatic bus_space_tag_t 1459183423Smariusschizo_alloc_bus_tag(struct schizo_softc *sc, int type) 1460183423Smarius{ 1461183423Smarius bus_space_tag_t bt; 1462183423Smarius 1463201199Smarius bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1464183423Smarius M_NOWAIT | M_ZERO); 1465183423Smarius if (bt == NULL) 1466183423Smarius panic("%s: out of memory", __func__); 1467183423Smarius 1468183423Smarius bt->bst_cookie = sc; 1469183423Smarius bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1470183423Smarius bt->bst_type = type; 1471183423Smarius return (bt); 1472183423Smarius} 1473183423Smarius 1474183423Smariusstatic u_int 1475183423Smariusschizo_get_timecount(struct timecounter *tc) 1476183423Smarius{ 1477183423Smarius struct schizo_softc *sc; 1478183423Smarius 1479183423Smarius sc = tc->tc_priv; 1480183423Smarius return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1481183423Smarius (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)); 1482183423Smarius} 1483