schizo.c revision 197164
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 197164 2009-09-13 14:47:31Z marius $"); 36 37/* 38 * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to 39 * PCI 2.2 bridges 40 */ 41 42#include "opt_ofw_pci.h" 43#include "opt_schizo.h" 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48#include <sys/kernel.h> 49#include <sys/lock.h> 50#include <sys/malloc.h> 51#include <sys/module.h> 52#include <sys/mutex.h> 53#include <sys/pcpu.h> 54#include <sys/rman.h> 55#include <sys/time.h> 56#include <sys/timetc.h> 57 58#include <dev/ofw/ofw_bus.h> 59#include <dev/ofw/ofw_pci.h> 60#include <dev/ofw/openfirm.h> 61 62#include <machine/bus.h> 63#include <machine/bus_common.h> 64#include <machine/bus_private.h> 65#include <machine/fsr.h> 66#include <machine/iommureg.h> 67#include <machine/iommuvar.h> 68#include <machine/resource.h> 69 70#include <dev/pci/pcireg.h> 71#include <dev/pci/pcivar.h> 72 73#include <sparc64/pci/ofw_pci.h> 74#include <sparc64/pci/schizoreg.h> 75#include <sparc64/pci/schizovar.h> 76 77#include "pcib_if.h" 78 79static const struct schizo_desc *schizo_get_desc(device_t); 80static void schizo_set_intr(struct schizo_softc *, u_int, u_int, 81 driver_filter_t); 82static driver_filter_t schizo_dma_sync_stub; 83static driver_filter_t ichip_dma_sync_stub; 84static void schizo_intr_enable(void *); 85static void schizo_intr_disable(void *); 86static void schizo_intr_assign(void *); 87static void schizo_intr_clear(void *); 88static int schizo_intr_register(struct schizo_softc *sc, u_int ino); 89static int schizo_get_intrmap(struct schizo_softc *, u_int, 90 bus_addr_t *, bus_addr_t *); 91static bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int); 92static timecounter_get_t schizo_get_timecount; 93 94/* Interrupt handlers */ 95static driver_filter_t schizo_pci_bus; 96static driver_filter_t schizo_ue; 97static driver_filter_t schizo_ce; 98static driver_filter_t schizo_host_bus; 99static driver_filter_t schizo_cdma; 100 101/* IOMMU support */ 102static void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 103 104/* 105 * Methods 106 */ 107static device_probe_t schizo_probe; 108static device_attach_t schizo_attach; 109static bus_read_ivar_t schizo_read_ivar; 110static bus_setup_intr_t schizo_setup_intr; 111static bus_teardown_intr_t schizo_teardown_intr; 112static bus_alloc_resource_t schizo_alloc_resource; 113static bus_activate_resource_t schizo_activate_resource; 114static bus_deactivate_resource_t schizo_deactivate_resource; 115static bus_release_resource_t schizo_release_resource; 116static bus_get_dma_tag_t schizo_get_dma_tag; 117static pcib_maxslots_t schizo_maxslots; 118static pcib_read_config_t schizo_read_config; 119static pcib_write_config_t schizo_write_config; 120static pcib_route_interrupt_t schizo_route_interrupt; 121static ofw_bus_get_node_t schizo_get_node; 122 123static device_method_t schizo_methods[] = { 124 /* Device interface */ 125 DEVMETHOD(device_probe, schizo_probe), 126 DEVMETHOD(device_attach, schizo_attach), 127 DEVMETHOD(device_shutdown, bus_generic_shutdown), 128 DEVMETHOD(device_suspend, bus_generic_suspend), 129 DEVMETHOD(device_resume, bus_generic_resume), 130 131 /* Bus interface */ 132 DEVMETHOD(bus_print_child, bus_generic_print_child), 133 DEVMETHOD(bus_read_ivar, schizo_read_ivar), 134 DEVMETHOD(bus_setup_intr, schizo_setup_intr), 135 DEVMETHOD(bus_teardown_intr, schizo_teardown_intr), 136 DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 137 DEVMETHOD(bus_activate_resource, schizo_activate_resource), 138 DEVMETHOD(bus_deactivate_resource, schizo_deactivate_resource), 139 DEVMETHOD(bus_release_resource, schizo_release_resource), 140 DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 141 142 /* pcib interface */ 143 DEVMETHOD(pcib_maxslots, schizo_maxslots), 144 DEVMETHOD(pcib_read_config, schizo_read_config), 145 DEVMETHOD(pcib_write_config, schizo_write_config), 146 DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 147 148 /* ofw_bus interface */ 149 DEVMETHOD(ofw_bus_get_node, schizo_get_node), 150 151 KOBJMETHOD_END 152}; 153 154static devclass_t schizo_devclass; 155 156DEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 157 sizeof(struct schizo_softc)); 158DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0); 159 160static SLIST_HEAD(, schizo_softc) schizo_softcs = 161 SLIST_HEAD_INITIALIZER(schizo_softcs); 162 163static const struct intr_controller schizo_ic = { 164 schizo_intr_enable, 165 schizo_intr_disable, 166 schizo_intr_assign, 167 schizo_intr_clear 168}; 169 170struct schizo_icarg { 171 struct schizo_softc *sica_sc; 172 bus_addr_t sica_map; 173 bus_addr_t sica_clr; 174}; 175 176struct schizo_dma_sync { 177 struct schizo_softc *sds_sc; 178 driver_filter_t *sds_handler; 179 void *sds_arg; 180 void *sds_cookie; 181 uint64_t sds_syncval; 182 device_t sds_ppb; /* farest PCI-PCI bridge */ 183 uint8_t sds_bus; /* bus of farest PCI device */ 184 uint8_t sds_slot; /* slot of farest PCI device */ 185 uint8_t sds_func; /* func. of farest PCI device */ 186}; 187 188#define SCHIZO_PERF_CNT_QLTY 100 189 190#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 191 bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 192#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 193 bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 194 195#define SCHIZO_PCI_READ_8(sc, offs) \ 196 SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 197#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 198 SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 199#define SCHIZO_CTRL_READ_8(sc, offs) \ 200 SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 201#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 202 SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 203#define SCHIZO_PCICFG_READ_8(sc, offs) \ 204 SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 205#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 206 SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 207#define SCHIZO_ICON_READ_8(sc, offs) \ 208 SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 209#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 210 SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 211 212struct schizo_desc { 213 const char *sd_string; 214 int sd_mode; 215 const char *sd_name; 216}; 217 218static const struct schizo_desc const schizo_compats[] = { 219 { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 220 { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 221 { NULL, 0, NULL } 222}; 223 224static const struct schizo_desc * 225schizo_get_desc(device_t dev) 226{ 227 const struct schizo_desc *desc; 228 const char *compat; 229 230 compat = ofw_bus_get_compat(dev); 231 if (compat == NULL) 232 return (NULL); 233 for (desc = schizo_compats; desc->sd_string != NULL; desc++) 234 if (strcmp(desc->sd_string, compat) == 0) 235 return (desc); 236 return (NULL); 237} 238 239static int 240schizo_probe(device_t dev) 241{ 242 const char *dtype; 243 244 dtype = ofw_bus_get_type(dev); 245 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 246 schizo_get_desc(dev) != NULL) { 247 device_set_desc(dev, "Sun Host-PCI bridge"); 248 return (0); 249 } 250 return (ENXIO); 251} 252 253static int 254schizo_attach(device_t dev) 255{ 256 struct ofw_pci_ranges *range; 257 const struct schizo_desc *desc; 258 struct schizo_softc *asc, *sc, *osc; 259 struct timecounter *tc; 260 uint64_t ino_bitmap, reg; 261 phandle_t node; 262 uint32_t prop, prop_array[2]; 263 int i, mode, n, nrange, rid, tsbsize; 264 265 sc = device_get_softc(dev); 266 node = ofw_bus_get_node(dev); 267 desc = schizo_get_desc(dev); 268 mode = desc->sd_mode; 269 270 sc->sc_dev = dev; 271 sc->sc_node = node; 272 sc->sc_mode = mode; 273 sc->sc_flags = 0; 274 275 /* 276 * The Schizo has three register banks: 277 * (0) per-PBM PCI configuration and status registers, but for bus B 278 * shared with the UPA64s interrupt mapping register banks 279 * (1) shared Schizo controller configuration and status registers 280 * (2) per-PBM PCI configuration space 281 * 282 * The Tomatillo has four register banks: 283 * (0) per-PBM PCI configuration and status registers 284 * (1) per-PBM Tomatillo controller configuration registers, but on 285 * machines having the `jbusppm' device shared with its Estar 286 * register bank for bus A 287 * (2) per-PBM PCI configuration space 288 * (3) per-PBM interrupt concentrator registers 289 */ 290 sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 291 20) & 1; 292 for (n = 0; n < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 293 n++) { 294 rid = n; 295 sc->sc_mem_res[n] = bus_alloc_resource_any(dev, 296 SYS_RES_MEMORY, &rid, 297 (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 298 n == STX_PCI) || n == STX_CTRL)) || 299 (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 300 n == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 301 if (sc->sc_mem_res[n] == NULL) 302 panic("%s: could not allocate register bank %d", 303 __func__, n); 304 } 305 306 /* 307 * Match other Schizos that are already configured against 308 * the controller base physical address. This will be the 309 * same for a pair of devices that share register space. 310 */ 311 osc = NULL; 312 SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 313 if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 314 rman_get_start(sc->sc_mem_res[STX_CTRL])) { 315 /* Found partner. */ 316 osc = asc; 317 break; 318 } 319 } 320 if (osc == NULL) { 321 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 322 M_NOWAIT | M_ZERO); 323 if (sc->sc_mtx == NULL) 324 panic("%s: could not malloc mutex", __func__); 325 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 326 } else { 327 if (sc->sc_mode != SCHIZO_MODE_SCZ) 328 panic("%s: no partner expected", __func__); 329 if (mtx_initialized(osc->sc_mtx) == 0) 330 panic("%s: mutex not initialized", __func__); 331 sc->sc_mtx = osc->sc_mtx; 332 } 333 334 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 335 panic("%s: could not determine IGN", __func__); 336 if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == -1) 337 panic("%s: could not determine version", __func__); 338 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 339 prop = 33000000; 340 341 device_printf(dev, "%s, version %d, IGN %#x, bus %c, %dMHz\n", 342 desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half, 343 prop / 1000 / 1000); 344 345 /* Set up the PCI interrupt retry timer. */ 346#ifdef SCHIZO_DEBUG 347 device_printf(dev, "PCI IRT 0x%016llx\n", (unsigned long long) 348 SCHIZO_PCI_READ_8(sc, STX_PCI_INTR_RETRY_TIM)); 349#endif 350 SCHIZO_PCI_WRITE_8(sc, STX_PCI_INTR_RETRY_TIM, 5); 351 352 /* Set up the PCI control register. */ 353 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 354 reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 355 STX_PCI_CTRL_ERR_IEN | STX_PCI_CTRL_ARB_MASK; 356 reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK); 357 if (OF_getproplen(node, "no-bus-parking") < 0) 358 reg |= STX_PCI_CTRL_ARB_PARK; 359 if (mode == SCHIZO_MODE_TOM) { 360 reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 361 if (sc->sc_ver <= 1) /* revision <= 2.0 */ 362 reg |= TOM_PCI_CTRL_DTO_IEN; 363 else 364 reg |= STX_PCI_CTRL_PTO; 365 } 366#ifdef SCHIZO_DEBUG 367 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 368 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL), 369 (unsigned long long)reg); 370#endif 371 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, reg); 372 373 /* Set up the PCI diagnostic register. */ 374 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 375 reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 376 STX_PCI_DIAG_INTRSYNC_DIS); 377#ifdef SCHIZO_DEBUG 378 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 379 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG), 380 (unsigned long long)reg); 381#endif 382 SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg); 383 384 /* 385 * On Tomatillo clear the I/O prefetch lengths (workaround for a 386 * Jalapeno bug). 387 */ 388 if (mode == SCHIZO_MODE_TOM) 389 SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 390 (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 391 TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 392 393 /* 394 * Hunt through all the interrupt mapping regs and register 395 * the interrupt controller for our interrupt vectors. We do 396 * this early in order to be able to catch stray interrupts. 397 * This is complicated by the fact that a pair of Schizo PBMs 398 * shares one IGN. 399 */ 400 n = OF_getprop(node, "ino-bitmap", (void *)prop_array, 401 sizeof(prop_array)); 402 if (n == -1) 403 panic("%s: could not get ino-bitmap", __func__); 404 ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 405 for (n = 0; n <= STX_MAX_INO; n++) { 406 if ((ino_bitmap & (1ULL << n)) == 0) 407 continue; 408 if (n == STX_FB0_INO || n == STX_FB1_INO) 409 /* Leave for upa(4). */ 410 continue; 411 i = schizo_intr_register(sc, n); 412 if (i != 0) 413 device_printf(dev, "could not register interrupt " 414 "controller for INO %d (%d)\n", n, i); 415 } 416 417 /* 418 * Setup Safari/JBus performance counter 0 in bus cycle counting 419 * mode as timecounter. Unfortunately, this is broken with at 420 * least the version 4 Tomatillos found in Fire V120 and Blade 421 * 1500, which apparently actually count some different event at 422 * ~0.5 and 3MHz respectively instead (also when running in full 423 * power mode). Besides, one counter seems to be shared by a 424 * "pair" of Tomatillos, too. 425 */ 426 if (sc->sc_half == 0) { 427 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_PERF, 428 (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 429 (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 430 tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 431 if (tc == NULL) 432 panic("%s: could not malloc timecounter", __func__); 433 tc->tc_get_timecount = schizo_get_timecount; 434 tc->tc_poll_pps = NULL; 435 tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 436 if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 437 sizeof(prop)) == -1) 438 panic("%s: could not determine clock frequency", 439 __func__); 440 tc->tc_frequency = prop; 441 tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 442 if (mode == SCHIZO_MODE_SCZ) 443 tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 444 else 445 tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 446 tc->tc_priv = sc; 447 tc_init(tc); 448 } 449 450 /* 451 * Set up the IOMMU. Schizo, Tomatillo and XMITS all have 452 * one per PBM. Schizo and XMITS additionally have a streaming 453 * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's 454 * affected by several errata and basically unusable though. 455 */ 456 sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 457 sc->sc_is.is_sb[0] = sc->sc_is.is_sb[1] = 0; 458 if (OF_getproplen(node, "no-streaming-cache") < 0 && 459 !(sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver < 5)) 460 sc->sc_is.is_sb[0] = STX_PCI_STRBUF; 461 462#define TSBCASE(x) \ 463 case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 464 tsbsize = (x); \ 465 break; \ 466 467 n = OF_getprop(node, "virtual-dma", (void *)prop_array, 468 sizeof(prop_array)); 469 if (n == -1 || n != sizeof(prop_array)) 470 schizo_iommu_init(sc, 7, -1); 471 else { 472 switch (prop_array[1]) { 473 TSBCASE(1); 474 TSBCASE(2); 475 TSBCASE(3); 476 TSBCASE(4); 477 TSBCASE(5); 478 TSBCASE(6); 479 TSBCASE(7); 480 TSBCASE(8); 481 default: 482 panic("%s: unsupported DVMA size 0x%x", 483 __func__, prop_array[1]); 484 /* NOTREACHED */ 485 } 486 schizo_iommu_init(sc, tsbsize, prop_array[0]); 487 } 488 489#undef TSBCASE 490 491 /* Initialize memory and I/O rmans. */ 492 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 493 sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 494 if (rman_init(&sc->sc_pci_io_rman) != 0 || 495 rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 496 panic("%s: failed to set up I/O rman", __func__); 497 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 498 sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 499 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 500 rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 501 panic("%s: failed to set up memory rman", __func__); 502 503 nrange = OF_getprop_alloc(node, "ranges", sizeof(*range), 504 (void **)&range); 505 /* 506 * Make sure that the expected ranges are present. The 507 * OFW_PCI_CS_MEM64 one is not currently used though. 508 */ 509 if (nrange != STX_NRANGE) 510 panic("%s: unsupported number of ranges", __func__); 511 /* 512 * Find the addresses of the various bus spaces. 513 * There should not be multiple ones of one kind. 514 * The physical start addresses of the ranges are the configuration, 515 * memory and I/O handles. 516 */ 517 for (n = 0; n < STX_NRANGE; n++) { 518 i = OFW_PCI_RANGE_CS(&range[n]); 519 if (sc->sc_pci_bh[i] != 0) 520 panic("%s: duplicate range for space %d", __func__, i); 521 sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]); 522 } 523 free(range, M_OFWPROP); 524 525 /* Register the softc, this is needed for paired Schizos. */ 526 SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 527 528 /* Allocate our tags. */ 529 sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 530 sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 531 sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 532 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 533 sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr, 534 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 535 panic("%s: bus_dma_tag_create failed", __func__); 536 /* Customize the tag. */ 537 sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 538 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 539 540 /* 541 * Get the bus range from the firmware. 542 * NB: Tomatillos don't support PCI bus reenumeration. 543 */ 544 n = OF_getprop(node, "bus-range", (void *)prop_array, 545 sizeof(prop_array)); 546 if (n == -1) 547 panic("%s: could not get bus-range", __func__); 548 if (n != sizeof(prop_array)) 549 panic("%s: broken bus-range (%d)", __func__, n); 550 if (bootverbose) 551 device_printf(dev, "bus range %u to %u; PCI bus %d\n", 552 prop_array[0], prop_array[1], prop_array[0]); 553 sc->sc_pci_secbus = prop_array[0]; 554 555 /* Clear any pending PCI error bits. */ 556 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 557 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 558 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 559 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, 560 SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 561 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, 562 SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 563 564 /* 565 * Establish handlers for interesting interrupts... 566 * Someone at Sun clearly was smoking crack; with Schizos PCI 567 * bus error interrupts for one PBM can be routed to the other 568 * PBM though we obviously need to use the softc of the former 569 * as the argument for the interrupt handler and the softc of 570 * the latter as the argument for the interrupt controller. 571 */ 572 if (sc->sc_half == 0) { 573 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 574 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 575 INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 576 sica_sc == osc)) 577 /* 578 * We are the driver for PBM A and either also 579 * registered the interrupt controller for us or 580 * the driver for PBM B has probed first and 581 * registered it for us. 582 */ 583 schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 584 schizo_pci_bus); 585 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 586 osc != NULL) 587 /* 588 * We are the driver for PBM A but registered 589 * the interrupt controller for PBM B, i.e. the 590 * driver for PBM B attached first but couldn't 591 * set up a handler for PBM B. 592 */ 593 schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 594 schizo_pci_bus); 595 } else { 596 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 597 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 598 INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 599 sica_sc == osc)) 600 /* 601 * We are the driver for PBM B and either also 602 * registered the interrupt controller for us or 603 * the driver for PBM A has probed first and 604 * registered it for us. 605 */ 606 schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 607 schizo_pci_bus); 608 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 609 osc != NULL) 610 /* 611 * We are the driver for PBM B but registered 612 * the interrupt controller for PBM A, i.e. the 613 * driver for PBM A attached first but couldn't 614 * set up a handler for PBM A. 615 */ 616 schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 617 schizo_pci_bus); 618 } 619 if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 620 schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 621 if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 622 schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 623 if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 624 schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 625 626 /* 627 * According to the Schizo Errata I-13, consistent DMA flushing/ 628 * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 629 * so we can't use it and need to live with the consequences. 630 * With Schizo version >= 5, CDMA flushing/syncing is usable 631 * but requires the the workaround described in Schizo Errata 632 * I-23. With Tomatillo and XMITS, CDMA flushing/syncing works 633 * as expected, Tomatillo version <= 4 (i.e. revision <= 2.3) 634 * bridges additionally require a block store after a write to 635 * TOMXMS_PCI_DMA_SYNC_PEND though. 636 */ 637 if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 638 sc->sc_mode == SCHIZO_MODE_TOM || sc->sc_mode == SCHIZO_MODE_XMS) { 639 sc->sc_flags |= SCHIZO_FLAGS_CDMA; 640 if (sc->sc_mode == SCHIZO_MODE_SCZ) { 641 n = STX_CDMA_A_INO + sc->sc_half; 642 if (bus_set_resource(dev, SYS_RES_IRQ, 5, 643 INTMAP_VEC(sc->sc_ign, n), 1) != 0) 644 panic("%s: failed to add CDMA interrupt", 645 __func__); 646 i = schizo_intr_register(sc, n); 647 if (i != 0) 648 panic("%s: could not register interrupt " 649 "controller for CDMA (%d)", __func__, i); 650 (void)schizo_get_intrmap(sc, n, NULL, 651 &sc->sc_cdma_clr); 652 sc->sc_cdma_state = SCHIZO_CDMA_STATE_DONE; 653 schizo_set_intr(sc, 5, n, schizo_cdma); 654 } 655 if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 656 sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 657 } 658 659 /* 660 * Set the latency timer register as this isn't always done by the 661 * firmware. 662 */ 663 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 664 PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 665 666 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 667 668 device_add_child(dev, "pci", -1); 669 return (bus_generic_attach(dev)); 670} 671 672static void 673schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 674 driver_filter_t handler) 675{ 676 u_long vec; 677 int rid; 678 679 rid = index; 680 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ, 681 &rid, RF_ACTIVE); 682 if (sc->sc_irq_res[index] == NULL || 683 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign || 684 INTINO(vec) != ino || 685 intr_vectors[vec].iv_ic != &schizo_ic || 686 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 687 INTR_TYPE_MISC | INTR_FAST, handler, NULL, sc, 688 &sc->sc_ihand[index]) != 0) 689 panic("%s: failed to set up interrupt %d", __func__, index); 690} 691 692static int 693schizo_intr_register(struct schizo_softc *sc, u_int ino) 694{ 695 struct schizo_icarg *sica; 696 bus_addr_t intrclr, intrmap; 697 int error; 698 699 if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 700 return (ENXIO); 701 sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 702 if (sica == NULL) 703 return (ENOMEM); 704 sica->sica_sc = sc; 705 sica->sica_map = intrmap; 706 sica->sica_clr = intrclr; 707#ifdef SCHIZO_DEBUG 708 device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 709 ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 710 (u_long)intrclr); 711#endif 712 error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 713 &schizo_ic, sica)); 714 if (error != 0) 715 free(sica, M_DEVBUF); 716 return (error); 717} 718 719static int 720schizo_get_intrmap(struct schizo_softc *sc, u_int ino, bus_addr_t *intrmapptr, 721 bus_addr_t *intrclrptr) 722{ 723 bus_addr_t intrclr, intrmap; 724 uint64_t mr; 725 726 /* 727 * XXX we only look for INOs rather than INRs since the firmware 728 * may not provide the IGN and the IGN is constant for all devices 729 * on that PCI controller. 730 */ 731 732 if (ino > STX_MAX_INO) { 733 device_printf(sc->sc_dev, "out of range INO %d requested\n", 734 ino); 735 return (0); 736 } 737 738 intrmap = STX_PCI_IMAP_BASE + (ino << 3); 739 intrclr = STX_PCI_ICLR_BASE + (ino << 3); 740 mr = SCHIZO_PCI_READ_8(sc, intrmap); 741 if (INTINO(mr) != ino) { 742 device_printf(sc->sc_dev, 743 "interrupt map entry does not match INO (%d != %d)\n", 744 (int)INTINO(mr), ino); 745 return (0); 746 } 747 748 if (intrmapptr != NULL) 749 *intrmapptr = intrmap; 750 if (intrclrptr != NULL) 751 *intrclrptr = intrclr; 752 return (1); 753} 754 755/* 756 * Interrupt handlers 757 */ 758static int 759schizo_pci_bus(void *arg) 760{ 761 struct schizo_softc *sc = arg; 762 uint64_t afar, afsr, csr, iommu; 763 uint32_t status; 764 765 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 766 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 767 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 768 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 769 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 770 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 771 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0) { 772 if ((iommu & TOM_PCI_IOMMU_ERR) == 0) 773 goto clear_error; 774 775 /* These are non-fatal if target abort was signaled. */ 776 if ((status & PCIM_STATUS_STABORT) != 0 && 777 ((iommu & TOM_PCI_IOMMU_ERRMASK) == 778 TOM_PCI_IOMMU_INVALID_ERR || 779 (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) != 0 || 780 (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) != 0)) { 781 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 782 goto clear_error; 783 } 784 } 785 786 panic("%s: PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 787 "IOMMU %#llx STATUS %#llx", device_get_name(sc->sc_dev), 788 'A' + sc->sc_half, (unsigned long long)afar, 789 (unsigned long long)afsr, (unsigned long long)csr, 790 (unsigned long long)iommu, (unsigned long long)status); 791 792 clear_error: 793 if (bootverbose) 794 device_printf(sc->sc_dev, 795 "PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 796 "STATUS %#llx", 'A' + sc->sc_half, 797 (unsigned long long)afar, (unsigned long long)afsr, 798 (unsigned long long)csr, (unsigned long long)status); 799 /* Clear the error bits that we caught. */ 800 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 801 STX_CS_FUNC, PCIR_STATUS, status, 2); 802 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 803 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 804 return (FILTER_HANDLED); 805} 806 807static int 808schizo_ue(void *arg) 809{ 810 struct schizo_softc *sc = arg; 811 uint64_t afar, afsr; 812 int i; 813 814 mtx_lock_spin(sc->sc_mtx); 815 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 816 for (i = 0; i < 1000; i++) 817 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 818 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 819 break; 820 mtx_unlock_spin(sc->sc_mtx); 821 panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 822 device_get_name(sc->sc_dev), (unsigned long long)afar, 823 (unsigned long long)afsr); 824 return (FILTER_HANDLED); 825} 826 827static int 828schizo_ce(void *arg) 829{ 830 struct schizo_softc *sc = arg; 831 uint64_t afar, afsr; 832 int i; 833 834 mtx_lock_spin(sc->sc_mtx); 835 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 836 for (i = 0; i < 1000; i++) 837 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 838 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 839 break; 840 device_printf(sc->sc_dev, 841 "correctable DMA error AFAR %#llx AFSR %#llx\n", 842 (unsigned long long)afar, (unsigned long long)afsr); 843 /* Clear the error bits that we caught. */ 844 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 845 mtx_unlock_spin(sc->sc_mtx); 846 return (FILTER_HANDLED); 847} 848 849static int 850schizo_host_bus(void *arg) 851{ 852 struct schizo_softc *sc = arg; 853 uint64_t errlog; 854 855 errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 856 panic("%s: %s error %#llx", device_get_name(sc->sc_dev), 857 sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 858 (unsigned long long)errlog); 859 return (FILTER_HANDLED); 860} 861 862static int 863schizo_cdma(void *arg) 864{ 865 struct schizo_softc *sc = arg; 866 867 atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE); 868 return (FILTER_HANDLED); 869} 870 871static void 872schizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 873{ 874 875 /* Punch in our copies. */ 876 sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 877 sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 878 sc->sc_is.is_iommu = STX_PCI_IOMMU; 879 sc->sc_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 880 sc->sc_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 881 sc->sc_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 882 sc->sc_is.is_dva = STX_PCI_IOMMU_SVADIAG; 883 sc->sc_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 884 885 iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, tsbsize, 886 dvmabase, 0); 887} 888 889static int 890schizo_maxslots(device_t dev) 891{ 892 struct schizo_softc *sc; 893 894 sc = device_get_softc(dev); 895 if (sc->sc_mode == SCHIZO_MODE_SCZ) 896 return (sc->sc_half == 0 ? 4 : 6); 897 898 /* XXX: is this correct? */ 899 return (PCI_SLOTMAX); 900} 901 902static uint32_t 903schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 904 int width) 905{ 906 struct schizo_softc *sc; 907 bus_space_handle_t bh; 908 u_long offset = 0; 909 uint32_t r, wrd; 910 int i; 911 uint16_t shrt; 912 uint8_t byte; 913 914 sc = device_get_softc(dev); 915 916 /* 917 * The Schizo bridges contain a dupe of their header at 0x80. 918 */ 919 if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 920 slot == STX_CS_DEVICE && func == STX_CS_FUNC && 921 reg + width > 0x80) 922 return (0); 923 924 offset = STX_CONF_OFF(bus, slot, func, reg); 925 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 926 switch (width) { 927 case 1: 928 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 929 r = byte; 930 break; 931 case 2: 932 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 933 r = shrt; 934 break; 935 case 4: 936 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 937 r = wrd; 938 break; 939 default: 940 panic("%s: bad width", __func__); 941 /* NOTREACHED */ 942 } 943 944 if (i) { 945#ifdef SCHIZO_DEBUG 946 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 947 __func__, bus, slot, func, reg); 948#endif 949 r = -1; 950 } 951 return (r); 952} 953 954static void 955schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 956 uint32_t val, int width) 957{ 958 struct schizo_softc *sc; 959 bus_space_handle_t bh; 960 u_long offset = 0; 961 962 sc = device_get_softc(dev); 963 offset = STX_CONF_OFF(bus, slot, func, reg); 964 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 965 switch (width) { 966 case 1: 967 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 968 break; 969 case 2: 970 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 971 break; 972 case 4: 973 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 974 break; 975 default: 976 panic("%s: bad width", __func__); 977 /* NOTREACHED */ 978 } 979} 980 981static int 982schizo_route_interrupt(device_t bridge, device_t dev, int pin) 983{ 984 struct schizo_softc *sc; 985 struct ofw_pci_register reg; 986 ofw_pci_intr_t pintr, mintr; 987 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 988 989 sc = device_get_softc(bridge); 990 pintr = pin; 991 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 992 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 993 return (mintr); 994 995 device_printf(bridge, "could not route pin %d for device %d.%d\n", 996 pin, pci_get_slot(dev), pci_get_function(dev)); 997 return (PCI_INVALID_IRQ); 998} 999 1000static int 1001schizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1002{ 1003 struct schizo_softc *sc; 1004 1005 sc = device_get_softc(dev); 1006 switch (which) { 1007 case PCIB_IVAR_DOMAIN: 1008 *result = device_get_unit(dev); 1009 return (0); 1010 case PCIB_IVAR_BUS: 1011 *result = sc->sc_pci_secbus; 1012 return (0); 1013 } 1014 return (ENOENT); 1015} 1016 1017static int 1018schizo_dma_sync_stub(void *arg) 1019{ 1020 struct timeval cur, end; 1021 struct schizo_dma_sync *sds = arg; 1022 struct schizo_softc *sc = sds->sds_sc; 1023 uint32_t state; 1024 1025 (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1026 sds->sds_func, PCIR_VENDOR, 2); 1027 for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE, 1028 SCHIZO_CDMA_STATE_PENDING) == 0;) 1029 ; 1030 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, 1); 1031 microuptime(&cur); 1032 end.tv_sec = 1; 1033 end.tv_usec = 0; 1034 timevaladd(&end, &cur); 1035 for (; (state = atomic_load_32(&sc->sc_cdma_state)) != 1036 SCHIZO_CDMA_STATE_DONE && timevalcmp(&cur, &end, <=);) 1037 microuptime(&cur); 1038 if (state != SCHIZO_CDMA_STATE_DONE) 1039 panic("%s: DMA does not sync", __func__); 1040 return (sds->sds_handler(sds->sds_arg)); 1041} 1042 1043#define VIS_BLOCKSIZE 64 1044 1045static int 1046ichip_dma_sync_stub(void *arg) 1047{ 1048 static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 1049 struct timeval cur, end; 1050 struct schizo_dma_sync *sds = arg; 1051 struct schizo_softc *sc = sds->sds_sc; 1052 register_t reg, s; 1053 1054 (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot, 1055 sds->sds_func, PCIR_VENDOR, 2); 1056 SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, sds->sds_syncval); 1057 microuptime(&cur); 1058 end.tv_sec = 1; 1059 end.tv_usec = 0; 1060 timevaladd(&end, &cur); 1061 for (; ((reg = SCHIZO_PCI_READ_8(sc, TOMXMS_PCI_DMA_SYNC_PEND)) & 1062 sds->sds_syncval) != 0 && timevalcmp(&cur, &end, <=);) 1063 microuptime(&cur); 1064 if ((reg & sds->sds_syncval) != 0) 1065 panic("%s: DMA does not sync", __func__); 1066 1067 if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1068 s = intr_disable(); 1069 reg = rd(fprs); 1070 wr(fprs, reg | FPRS_FEF, 0); 1071 __asm __volatile("stda %%f0, [%0] %1" 1072 : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 1073 membar(Sync); 1074 wr(fprs, reg, 0); 1075 intr_restore(s); 1076 } 1077 return (sds->sds_handler(sds->sds_arg)); 1078} 1079 1080static void 1081schizo_intr_enable(void *arg) 1082{ 1083 struct intr_vector *iv = arg; 1084 struct schizo_icarg *sica = iv->iv_icarg; 1085 1086 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1087 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1088} 1089 1090static void 1091schizo_intr_disable(void *arg) 1092{ 1093 struct intr_vector *iv = arg; 1094 struct schizo_icarg *sica = iv->iv_icarg; 1095 1096 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1097} 1098 1099static void 1100schizo_intr_assign(void *arg) 1101{ 1102 struct intr_vector *iv = arg; 1103 struct schizo_icarg *sica = iv->iv_icarg; 1104 1105 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1106 SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1107} 1108 1109static void 1110schizo_intr_clear(void *arg) 1111{ 1112 struct intr_vector *iv = arg; 1113 struct schizo_icarg *sica = iv->iv_icarg; 1114 1115 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, 0); 1116} 1117 1118static int 1119schizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1120 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1121 void **cookiep) 1122{ 1123 devclass_t pci_devclass; 1124 device_t cdev, pdev, pcidev; 1125 struct schizo_dma_sync *sds; 1126 struct schizo_softc *sc; 1127 u_long vec; 1128 int error, found; 1129 1130 sc = device_get_softc(dev); 1131 /* 1132 * Make sure the vector is fully specified. 1133 */ 1134 vec = rman_get_start(ires); 1135 if (INTIGN(vec) != sc->sc_ign) { 1136 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1137 return (EINVAL); 1138 } 1139 1140 if (intr_vectors[vec].iv_ic == &schizo_ic) { 1141 /* 1142 * Ensure we use the right softc in case the interrupt 1143 * is routed to our companion PBM for some odd reason. 1144 */ 1145 sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 1146 sica_sc; 1147 } else if (intr_vectors[vec].iv_ic == NULL) { 1148 /* 1149 * Work around broken firmware which misses entries in 1150 * the ino-bitmap. 1151 */ 1152 error = schizo_intr_register(sc, INTINO(vec)); 1153 if (error != 0) { 1154 device_printf(dev, "could not register interrupt " 1155 "controller for vector 0x%lx (%d)\n", vec, error); 1156 return (error); 1157 } 1158 if (bootverbose) 1159 device_printf(dev, "belatedly registered as " 1160 "interrupt controller for vector 0x%lx\n", vec); 1161 } else { 1162 device_printf(dev, 1163 "invalid interrupt controller for vector 0x%lx\n", vec); 1164 return (EINVAL); 1165 } 1166 1167 /* 1168 * Install a a wrapper for CDMA flushing/syncing for devices 1169 * behind PCI-PCI bridges if possible. 1170 */ 1171 pcidev = NULL; 1172 found = 0; 1173 pci_devclass = devclass_find("pci"); 1174 for (cdev = child; cdev != dev; cdev = pdev) { 1175 pdev = device_get_parent(cdev); 1176 if (pcidev == NULL) { 1177 if (device_get_devclass(pdev) != pci_devclass) 1178 continue; 1179 pcidev = cdev; 1180 continue; 1181 } 1182 if (pci_get_class(cdev) == PCIC_BRIDGE && 1183 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1184 found = 1; 1185 } 1186 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1187 sds = malloc(sizeof(*sds), M_DEVBUF, M_NOWAIT | M_ZERO); 1188 if (sds == NULL) 1189 return (ENOMEM); 1190 if (found != 0 && pcidev != NULL) { 1191 sds->sds_sc = sc; 1192 sds->sds_arg = arg; 1193 sds->sds_ppb = 1194 device_get_parent(device_get_parent(pcidev)); 1195 sds->sds_bus = pci_get_bus(pcidev); 1196 sds->sds_slot = pci_get_slot(pcidev); 1197 sds->sds_func = pci_get_function(pcidev); 1198 sds->sds_syncval = 1ULL << INTINO(vec); 1199 if (bootverbose) 1200 device_printf(dev, "installed DMA sync " 1201 "wrapper for device %d.%d on bus %d\n", 1202 sds->sds_slot, sds->sds_func, 1203 sds->sds_bus); 1204 1205#define DMA_SYNC_STUB \ 1206 (sc->sc_mode == SCHIZO_MODE_SCZ ? schizo_dma_sync_stub : \ 1207 ichip_dma_sync_stub) 1208 1209 if (intr == NULL) { 1210 sds->sds_handler = filt; 1211 error = bus_generic_setup_intr(dev, child, 1212 ires, flags, DMA_SYNC_STUB, intr, sds, 1213 cookiep); 1214 } else { 1215 sds->sds_handler = (driver_filter_t *)intr; 1216 error = bus_generic_setup_intr(dev, child, 1217 ires, flags, filt, (driver_intr_t *) 1218 DMA_SYNC_STUB, sds, cookiep); 1219 } 1220 1221#undef DMA_SYNC_STUB 1222 1223 } else 1224 error = bus_generic_setup_intr(dev, child, ires, 1225 flags, filt, intr, arg, cookiep); 1226 if (error != 0) { 1227 free(sds, M_DEVBUF); 1228 return (error); 1229 } 1230 sds->sds_cookie = *cookiep; 1231 *cookiep = sds; 1232 return (error); 1233 } else if (found != 0) 1234 device_printf(dev, "WARNING: using devices behind PCI-PCI " 1235 "bridges may cause data corruption\n"); 1236 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1237 arg, cookiep)); 1238} 1239 1240static int 1241schizo_teardown_intr(device_t dev, device_t child, struct resource *vec, 1242 void *cookie) 1243{ 1244 struct schizo_dma_sync *sds; 1245 struct schizo_softc *sc; 1246 int error; 1247 1248 sc = device_get_softc(dev); 1249 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) { 1250 sds = cookie; 1251 error = bus_generic_teardown_intr(dev, child, vec, 1252 sds->sds_cookie); 1253 if (error == 0) 1254 free(sds, M_DEVBUF); 1255 return (error); 1256 } 1257 return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1258} 1259 1260static struct resource * 1261schizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1262 u_long start, u_long end, u_long count, u_int flags) 1263{ 1264 struct schizo_softc *sc; 1265 struct resource *rv; 1266 struct rman *rm; 1267 bus_space_tag_t bt; 1268 bus_space_handle_t bh; 1269 int needactivate = flags & RF_ACTIVE; 1270 1271 flags &= ~RF_ACTIVE; 1272 1273 sc = device_get_softc(bus); 1274 if (type == SYS_RES_IRQ) { 1275 /* 1276 * XXX: Don't accept blank ranges for now, only single 1277 * interrupts. The other case should not happen with 1278 * the MI PCI code... 1279 * XXX: This may return a resource that is out of the 1280 * range that was specified. Is this correct...? 1281 */ 1282 if (start != end) 1283 panic("%s: XXX: interrupt range", __func__); 1284 start = end = INTMAP_VEC(sc->sc_ign, end); 1285 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1286 rid, start, end, count, flags)); 1287 } 1288 switch (type) { 1289 case SYS_RES_MEMORY: 1290 rm = &sc->sc_pci_mem_rman; 1291 bt = sc->sc_pci_memt; 1292 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1293 break; 1294 case SYS_RES_IOPORT: 1295 rm = &sc->sc_pci_io_rman; 1296 bt = sc->sc_pci_iot; 1297 bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1298 break; 1299 default: 1300 return (NULL); 1301 /* NOTREACHED */ 1302 } 1303 1304 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1305 if (rv == NULL) 1306 return (NULL); 1307 rman_set_rid(rv, *rid); 1308 bh += rman_get_start(rv); 1309 rman_set_bustag(rv, bt); 1310 rman_set_bushandle(rv, bh); 1311 1312 if (needactivate) { 1313 if (bus_activate_resource(child, type, *rid, rv)) { 1314 rman_release_resource(rv); 1315 return (NULL); 1316 } 1317 } 1318 return (rv); 1319} 1320 1321static int 1322schizo_activate_resource(device_t bus, device_t child, int type, int rid, 1323 struct resource *r) 1324{ 1325 void *p; 1326 int error; 1327 1328 if (type == SYS_RES_IRQ) 1329 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1330 type, rid, r)); 1331 if (type == SYS_RES_MEMORY) { 1332 /* 1333 * Need to memory-map the device space, as some drivers 1334 * depend on the virtual address being set and usable. 1335 */ 1336 error = sparc64_bus_mem_map(rman_get_bustag(r), 1337 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1338 if (error != 0) 1339 return (error); 1340 rman_set_virtual(r, p); 1341 } 1342 return (rman_activate_resource(r)); 1343} 1344 1345static int 1346schizo_deactivate_resource(device_t bus, device_t child, int type, int rid, 1347 struct resource *r) 1348{ 1349 1350 if (type == SYS_RES_IRQ) 1351 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1352 type, rid, r)); 1353 if (type == SYS_RES_MEMORY) { 1354 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1355 rman_set_virtual(r, NULL); 1356 } 1357 return (rman_deactivate_resource(r)); 1358} 1359 1360static int 1361schizo_release_resource(device_t bus, device_t child, int type, int rid, 1362 struct resource *r) 1363{ 1364 int error; 1365 1366 if (type == SYS_RES_IRQ) 1367 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1368 type, rid, r)); 1369 if (rman_get_flags(r) & RF_ACTIVE) { 1370 error = bus_deactivate_resource(child, type, rid, r); 1371 if (error) 1372 return (error); 1373 } 1374 return (rman_release_resource(r)); 1375} 1376 1377static bus_dma_tag_t 1378schizo_get_dma_tag(device_t bus, device_t child) 1379{ 1380 struct schizo_softc *sc; 1381 1382 sc = device_get_softc(bus); 1383 return (sc->sc_pci_dmat); 1384} 1385 1386static phandle_t 1387schizo_get_node(device_t bus, device_t dev) 1388{ 1389 struct schizo_softc *sc; 1390 1391 sc = device_get_softc(bus); 1392 /* We only have one child, the PCI bus, which needs our own node. */ 1393 return (sc->sc_node); 1394} 1395 1396static bus_space_tag_t 1397schizo_alloc_bus_tag(struct schizo_softc *sc, int type) 1398{ 1399 bus_space_tag_t bt; 1400 1401 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1402 M_NOWAIT | M_ZERO); 1403 if (bt == NULL) 1404 panic("%s: out of memory", __func__); 1405 1406 bt->bst_cookie = sc; 1407 bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1408 bt->bst_type = type; 1409 return (bt); 1410} 1411 1412static u_int 1413schizo_get_timecount(struct timecounter *tc) 1414{ 1415 struct schizo_softc *sc; 1416 1417 sc = tc->tc_priv; 1418 return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1419 (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)); 1420} 1421