schizo.c revision 184428
1/*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 184428 2008-10-28 22:05:20Z marius $"); 36 37/* 38 * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to 39 * PCI 2.2 bridges 40 */ 41 42#include "opt_ofw_pci.h" 43#include "opt_schizo.h" 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48#include <sys/kernel.h> 49#include <sys/lock.h> 50#include <sys/malloc.h> 51#include <sys/module.h> 52#include <sys/mutex.h> 53#include <sys/pcpu.h> 54#include <sys/rman.h> 55#include <sys/timetc.h> 56 57#include <dev/ofw/ofw_bus.h> 58#include <dev/ofw/ofw_pci.h> 59#include <dev/ofw/openfirm.h> 60 61#include <machine/bus.h> 62#include <machine/bus_common.h> 63#include <machine/bus_private.h> 64#include <machine/fsr.h> 65#include <machine/iommureg.h> 66#include <machine/iommuvar.h> 67#include <machine/ofw_bus.h> 68#include <machine/resource.h> 69 70#include <dev/pci/pcireg.h> 71#include <dev/pci/pcivar.h> 72 73#include <sparc64/pci/ofw_pci.h> 74#include <sparc64/pci/schizoreg.h> 75#include <sparc64/pci/schizovar.h> 76 77#include "pcib_if.h" 78 79static const struct schizo_desc *schizo_get_desc(device_t); 80static void schizo_set_intr(struct schizo_softc *, u_int, u_int, 81 driver_filter_t); 82static driver_filter_t schizo_dmasync; 83static void schizo_intr_enable(void *); 84static void schizo_intr_disable(void *); 85static void schizo_intr_assign(void *); 86static void schizo_intr_clear(void *); 87static int schizo_get_intrmap(struct schizo_softc *, u_int, 88 bus_addr_t *, bus_addr_t *); 89static bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int); 90static timecounter_get_t schizo_get_timecount; 91 92/* Interrupt handlers */ 93static driver_filter_t schizo_pci_bus; 94static driver_filter_t schizo_ue; 95static driver_filter_t schizo_ce; 96static driver_filter_t schizo_host_bus; 97 98/* IOMMU support */ 99static void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 100 101/* 102 * Methods 103 */ 104static device_probe_t schizo_probe; 105static device_attach_t schizo_attach; 106static bus_read_ivar_t schizo_read_ivar; 107static bus_setup_intr_t schizo_setup_intr; 108static bus_teardown_intr_t schizo_teardown_intr; 109static bus_alloc_resource_t schizo_alloc_resource; 110static bus_activate_resource_t schizo_activate_resource; 111static bus_deactivate_resource_t schizo_deactivate_resource; 112static bus_release_resource_t schizo_release_resource; 113static bus_get_dma_tag_t schizo_get_dma_tag; 114static pcib_maxslots_t schizo_maxslots; 115static pcib_read_config_t schizo_read_config; 116static pcib_write_config_t schizo_write_config; 117static pcib_route_interrupt_t schizo_route_interrupt; 118static ofw_bus_get_node_t schizo_get_node; 119 120static device_method_t schizo_methods[] = { 121 /* Device interface */ 122 DEVMETHOD(device_probe, schizo_probe), 123 DEVMETHOD(device_attach, schizo_attach), 124 DEVMETHOD(device_shutdown, bus_generic_shutdown), 125 DEVMETHOD(device_suspend, bus_generic_suspend), 126 DEVMETHOD(device_resume, bus_generic_resume), 127 128 /* Bus interface */ 129 DEVMETHOD(bus_print_child, bus_generic_print_child), 130 DEVMETHOD(bus_read_ivar, schizo_read_ivar), 131 DEVMETHOD(bus_setup_intr, schizo_setup_intr), 132 DEVMETHOD(bus_teardown_intr, schizo_teardown_intr), 133 DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 134 DEVMETHOD(bus_activate_resource, schizo_activate_resource), 135 DEVMETHOD(bus_deactivate_resource, schizo_deactivate_resource), 136 DEVMETHOD(bus_release_resource, schizo_release_resource), 137 DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 138 139 /* pcib interface */ 140 DEVMETHOD(pcib_maxslots, schizo_maxslots), 141 DEVMETHOD(pcib_read_config, schizo_read_config), 142 DEVMETHOD(pcib_write_config, schizo_write_config), 143 DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 144 145 /* ofw_bus interface */ 146 DEVMETHOD(ofw_bus_get_node, schizo_get_node), 147 148 { 0, 0 } 149}; 150 151static devclass_t schizo_devclass; 152 153DEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 154 sizeof(struct schizo_softc)); 155DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0); 156 157static SLIST_HEAD(, schizo_softc) schizo_softcs = 158 SLIST_HEAD_INITIALIZER(schizo_softcs); 159 160static const struct intr_controller schizo_ic = { 161 schizo_intr_enable, 162 schizo_intr_disable, 163 schizo_intr_assign, 164 schizo_intr_clear 165}; 166 167struct schizo_icarg { 168 struct schizo_softc *sica_sc; 169 bus_addr_t sica_map; 170 bus_addr_t sica_clr; 171}; 172 173struct schizo_dmasync { 174 struct schizo_softc *sds_sc; 175 driver_filter_t *sds_handler; 176 void *sds_arg; 177 void *sds_cookie; 178 uint64_t sds_syncval; 179 u_int sds_bswar; 180}; 181 182#define SCHIZO_PERF_CNT_QLTY 100 183 184#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 185 bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 186#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 187 bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 188 189#define SCHIZO_PCI_READ_8(sc, offs) \ 190 SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 191#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 192 SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 193#define SCHIZO_CTRL_READ_8(sc, offs) \ 194 SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 195#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 196 SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 197#define SCHIZO_PCICFG_READ_8(sc, offs) \ 198 SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 199#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 200 SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 201#define SCHIZO_ICON_READ_8(sc, offs) \ 202 SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 203#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 204 SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 205 206#define OFW_PCI_TYPE "pci" 207 208struct schizo_desc { 209 const char *sd_string; 210 int sd_mode; 211 const char *sd_name; 212}; 213 214static const struct schizo_desc schizo_compats[] = { 215 { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 216 { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 217 { NULL, 0, NULL } 218}; 219 220static const struct schizo_desc * 221schizo_get_desc(device_t dev) 222{ 223 const struct schizo_desc *desc; 224 const char *compat; 225 226 compat = ofw_bus_get_compat(dev); 227 if (compat == NULL) 228 return (NULL); 229 for (desc = schizo_compats; desc->sd_string != NULL; desc++) 230 if (strcmp(desc->sd_string, compat) == 0) 231 return (desc); 232 return (NULL); 233} 234 235static int 236schizo_probe(device_t dev) 237{ 238 const char *dtype; 239 240 dtype = ofw_bus_get_type(dev); 241 if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 && 242 schizo_get_desc(dev) != NULL) { 243 device_set_desc(dev, "Sun Host-PCI bridge"); 244 return (0); 245 } 246 return (ENXIO); 247} 248 249static int 250schizo_attach(device_t dev) 251{ 252 struct ofw_pci_ranges *range; 253 const struct schizo_desc *desc; 254 struct schizo_icarg *sica; 255 struct schizo_softc *asc, *sc, *osc; 256 struct timecounter *tc; 257 bus_addr_t intrclr, intrmap; 258 uint64_t ino_bitmap, reg; 259 phandle_t node; 260 uint32_t prop, prop_array[2]; 261 int i, mode, n, nrange, rid, tsbsize; 262 263 sc = device_get_softc(dev); 264 node = ofw_bus_get_node(dev); 265 desc = schizo_get_desc(dev); 266 mode = desc->sd_mode; 267 268 sc->sc_dev = dev; 269 sc->sc_node = node; 270 sc->sc_mode = mode; 271 272 /* 273 * The Schizo has three register banks: 274 * (0) per-PBM PCI configuration and status registers, but for bus B 275 * shared with the UPA64s interrupt mapping register banks 276 * (1) shared Schizo controller configuration and status registers 277 * (2) per-PBM PCI configuration space 278 * 279 * The Tomatillo has four register banks: 280 * (0) per-PBM PCI configuration and status registers 281 * (1) per-PBM Tomatillo controller configuration registers, but on 282 * machines having the `jbusppm' device shared with its Estar 283 * register bank for bus A 284 * (2) per-PBM PCI configuration space 285 * (3) per-PBM interrupt concentrator registers 286 */ 287 sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 288 20) & 1; 289 for (n = 0; n < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 290 n++) { 291 rid = n; 292 sc->sc_mem_res[n] = bus_alloc_resource_any(dev, 293 SYS_RES_MEMORY, &rid, 294 (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 295 n == STX_PCI) || n == STX_CTRL)) || 296 (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 297 n == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 298 if (sc->sc_mem_res[n] == NULL) 299 panic("%s: could not allocate register bank %d", 300 __func__, n); 301 } 302 303 /* 304 * Match other Schizos that are already configured against 305 * the controller base physical address. This will be the 306 * same for a pair of devices that share register space. 307 */ 308 osc = NULL; 309 SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 310 if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 311 rman_get_start(sc->sc_mem_res[STX_CTRL])) { 312 /* Found partner. */ 313 osc = asc; 314 break; 315 } 316 } 317 if (osc == NULL) { 318 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 319 M_NOWAIT | M_ZERO); 320 if (sc->sc_mtx == NULL) 321 panic("%s: could not malloc mutex", __func__); 322 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 323 } else { 324 if (mtx_initialized(osc->sc_mtx) == 0) 325 panic("%s: mutex not initialized", __func__); 326 sc->sc_mtx = osc->sc_mtx; 327 } 328 329 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 330 panic("%s: could not determine IGN", __func__); 331 if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == -1) 332 panic("%s: could not determine version", __func__); 333 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 334 prop = 33000000; 335 336 device_printf(dev, "%s, version %d, IGN %#x, bus %c, %dMHz\n", 337 desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half, 338 prop / 1000 / 1000); 339 340 /* Set up the PCI interrupt retry timer. */ 341#ifdef SCHIZO_DEBUG 342 device_printf(dev, "PCI IRT 0x%016llx\n", (unsigned long long) 343 SCHIZO_PCI_READ_8(sc, STX_PCI_INTR_RETRY_TIM)); 344#endif 345 SCHIZO_PCI_WRITE_8(sc, STX_PCI_INTR_RETRY_TIM, 5); 346 347 /* Set up the PCI control register. */ 348 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 349 reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 350 STX_PCI_CTRL_ERR_IEN | STX_PCI_CTRL_ARB_MASK; 351 reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK); 352 if (OF_getproplen(node, "no-bus-parking") < 0) 353 reg |= STX_PCI_CTRL_ARB_PARK; 354 if (mode == SCHIZO_MODE_TOM) { 355 reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 356 if (sc->sc_ver <= 1) /* revision <= 2.0 */ 357 reg |= TOM_PCI_CTRL_DTO_IEN; 358 else 359 reg |= STX_PCI_CTRL_PTO; 360 } 361#ifdef SCHIZO_DEBUG 362 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 363 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL), 364 (unsigned long long)reg); 365#endif 366 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, reg); 367 368 /* Set up the PCI diagnostic register. */ 369 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 370 reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 371 STX_PCI_DIAG_INTRSYNC_DIS); 372#ifdef SCHIZO_DEBUG 373 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 374 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG), 375 (unsigned long long)reg); 376#endif 377 SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg); 378 379 /* 380 * On Tomatillo clear the I/O prefetch lengths (workaround for a 381 * Jalapeno bug). 382 */ 383 if (mode == SCHIZO_MODE_TOM) 384 SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 385 (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 386 TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 387 388 /* 389 * Hunt through all the interrupt mapping regs and register 390 * the interrupt controller for our interrupt vectors. This 391 * is complicated by the fact that a pair of Schizo PBMs 392 * share one IGN. 393 */ 394 n = OF_getprop(node, "ino-bitmap", (void *)prop_array, 395 sizeof(prop_array)); 396 if (n == -1) 397 panic("%s: could not get ino-bitmap", __func__); 398 ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 399 for (n = 0; n <= STX_MAX_INO; n++) { 400 if ((ino_bitmap & (1ULL << n)) == 0) 401 continue; 402 if (n == STX_FB0_INO || n == STX_FB1_INO) 403 /* Leave for upa(4). */ 404 continue; 405 if (schizo_get_intrmap(sc, n, &intrmap, &intrclr) == 0) 406 continue; 407 sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 408 if (sica == NULL) 409 panic("%s: could not allocate interrupt controller " 410 "argument", __func__); 411 sica->sica_sc = sc; 412 sica->sica_map = intrmap; 413 sica->sica_clr = intrclr; 414#ifdef SCHIZO_DEBUG 415 device_printf(dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 416 n, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 417 (u_long)intrclr); 418#endif 419 if (intr_controller_register(INTMAP_VEC(sc->sc_ign, n), 420 &schizo_ic, sica) != 0) 421 panic("%s: could not register interrupt controller " 422 "for INO %d", __func__, n); 423 } 424 425 /* 426 * Setup Safari/JBus performance counter 0 in bus cycle counting 427 * mode as timecounter. Unfortunately, this is broken with at 428 * least the version 4 Tomatillos found in Fire V120 and Blade 429 * 1500, which apparently actually count some different event at 430 * ~0.5 and 3MHz respectively instead (also when running in full 431 * power mode). Besides, one counter seems to be shared by a 432 * "pair" of Tomatillos, too. 433 */ 434 if (sc->sc_half == 0) { 435 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_PERF, 436 (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 437 (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 438 tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 439 if (tc == NULL) 440 panic("%s: could not malloc timecounter", __func__); 441 tc->tc_get_timecount = schizo_get_timecount; 442 tc->tc_poll_pps = NULL; 443 tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 444 if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 445 sizeof(prop)) == -1) 446 panic("%s: could not determine clock frequency", 447 __func__); 448 tc->tc_frequency = prop; 449 tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 450 if (mode == SCHIZO_MODE_SCZ) 451 tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 452 else 453 tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 454 tc->tc_priv = sc; 455 tc_init(tc); 456 } 457 458 /* Set up the IOMMU. Both Schizo and Tomatillo have one per PBM. */ 459 sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 460 sc->sc_is.is_sb[0] = 0; 461 sc->sc_is.is_sb[1] = 0; 462 if (OF_getproplen(node, "no-streaming-cache") < 0) 463 sc->sc_is.is_sb[0] = STX_PCI_STRBUF; 464 465#define TSBCASE(x) \ 466 case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 467 tsbsize = (x); \ 468 break; \ 469 470 n = OF_getprop(node, "virtual-dma", (void *)prop_array, 471 sizeof(prop_array)); 472 if (n == -1 || n != sizeof(prop_array)) 473 schizo_iommu_init(sc, 7, -1); 474 else { 475 switch (prop_array[1]) { 476 TSBCASE(1); 477 TSBCASE(2); 478 TSBCASE(3); 479 TSBCASE(4); 480 TSBCASE(5); 481 TSBCASE(6); 482 TSBCASE(7); 483 TSBCASE(8); 484 default: 485 panic("%s: unsupported DVMA size 0x%x", 486 __func__, prop_array[1]); 487 /* NOTREACHED */ 488 } 489 schizo_iommu_init(sc, tsbsize, prop_array[0]); 490 } 491#undef TSBCASE 492 493 /* Initialize memory and I/O rmans. */ 494 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 495 sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 496 if (rman_init(&sc->sc_pci_io_rman) != 0 || 497 rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 498 panic("%s: failed to set up I/O rman", __func__); 499 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 500 sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 501 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 502 rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 503 panic("%s: failed to set up memory rman", __func__); 504 505 nrange = OF_getprop_alloc(node, "ranges", sizeof(*range), 506 (void **)&range); 507 /* 508 * Make sure that the expected ranges are present. The 509 * OFW_PCI_CS_MEM64 one is not currently used though. 510 */ 511 if (nrange != STX_NRANGE) 512 panic("%s: unsupported number of ranges", __func__); 513 /* 514 * Find the addresses of the various bus spaces. 515 * There should not be multiple ones of one kind. 516 * The physical start addresses of the ranges are the configuration, 517 * memory and I/O handles. 518 */ 519 for (n = 0; n < STX_NRANGE; n++) { 520 i = OFW_PCI_RANGE_CS(&range[n]); 521 if (sc->sc_pci_bh[i] != 0) 522 panic("%s: duplicate range for space %d", __func__, i); 523 sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]); 524 } 525 free(range, M_OFWPROP); 526 527 /* Register the softc, this is needed for paired Schizos. */ 528 SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 529 530 /* Allocate our tags. */ 531 sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 532 sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 533 sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 534 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 535 sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr, 536 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 537 panic("%s: bus_dma_tag_create failed", __func__); 538 /* Customize the tag. */ 539 sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 540 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 541 542 /* 543 * Get the bus range from the firmware. 544 * NB: Tomatillos don't support PCI bus reenumeration. 545 */ 546 n = OF_getprop(node, "bus-range", (void *)prop_array, 547 sizeof(prop_array)); 548 if (n == -1) 549 panic("%s: could not get bus-range", __func__); 550 if (n != sizeof(prop_array)) 551 panic("%s: broken bus-range (%d)", __func__, n); 552 if (bootverbose) 553 device_printf(dev, "bus range %u to %u; PCI bus %d\n", 554 prop_array[0], prop_array[1], prop_array[0]); 555 sc->sc_pci_secbus = prop_array[0]; 556 557 /* Clear any pending PCI error bits. */ 558 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 559 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 560 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 561 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, 562 SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 563 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, 564 SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 565 566 /* 567 * Establish handlers for interesting interrupts... 568 * Someone at Sun clearly was smoking crack; with Schizos PCI 569 * bus error interrupts for one PBM can be routed to the other 570 * PBM though we obviously need to use the softc of the former 571 * as the argument for the interrupt handler and the softc of 572 * the latter as the argument for the interrupt controller. 573 */ 574 if (sc->sc_half == 0) { 575 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 576 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 577 INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 578 sica_sc == osc)) 579 /* 580 * We are the driver for PBM A and either also 581 * registered the interrupt controller for us or 582 * the driver for PBM B has probed first and 583 * registered it for us. 584 */ 585 schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 586 schizo_pci_bus); 587 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 588 osc != NULL) 589 /* 590 * We are the driver for PBM A but registered 591 * the interrupt controller for PBM B, i.e. the 592 * driver for PBM B attached first but couldn't 593 * set up a handler for PBM B. 594 */ 595 schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 596 schizo_pci_bus); 597 } else { 598 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 599 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 600 INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 601 sica_sc == osc)) 602 /* 603 * We are the driver for PBM B and either also 604 * registered the interrupt controller for us or 605 * the driver for PBM A has probed first and 606 * registered it for us. 607 */ 608 schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 609 schizo_pci_bus); 610 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 611 osc != NULL) 612 /* 613 * We are the driver for PBM B but registered 614 * the interrupt controller for PBM A, i.e. the 615 * driver for PBM A attached first but couldn't 616 * set up a handler for PBM A. 617 */ 618 schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 619 schizo_pci_bus); 620 } 621 if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 622 schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 623 if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 624 schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 625 if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 626 schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 627 628 /* 629 * Set the latency timer register as this isn't always done by the 630 * firmware. 631 */ 632 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 633 PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 634 635 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 636 637 device_add_child(dev, "pci", -1); 638 return (bus_generic_attach(dev)); 639} 640 641static void 642schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 643 driver_filter_t handler) 644{ 645 u_long vec; 646 int rid; 647 648 rid = index; 649 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ, 650 &rid, RF_ACTIVE); 651 if (sc->sc_irq_res[index] == NULL || 652 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign || 653 INTINO(vec) != ino || 654 intr_vectors[vec].iv_ic != &schizo_ic || 655 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], INTR_TYPE_MISC, 656 handler, NULL, sc, &sc->sc_ihand[index]) != 0) 657 panic("%s: failed to set up interrupt %d", __func__, index); 658} 659 660static int 661schizo_get_intrmap(struct schizo_softc *sc, u_int ino, bus_addr_t *intrmapptr, 662 bus_addr_t *intrclrptr) 663{ 664 bus_addr_t intrclr, intrmap; 665 uint64_t mr; 666 667 /* 668 * XXX we only look for INOs rather than INRs since the firmware 669 * may not provide the IGN and the IGN is constant for all devices 670 * on that PCI controller. 671 */ 672 673 if (ino > STX_MAX_INO) { 674 device_printf(sc->sc_dev, "out of range INO %d requested\n", 675 ino); 676 return (0); 677 } 678 679 intrmap = STX_PCI_IMAP_BASE + (ino << 3); 680 intrclr = STX_PCI_ICLR_BASE + (ino << 3); 681 mr = SCHIZO_PCI_READ_8(sc, intrmap); 682 if (INTINO(mr) != ino) { 683 device_printf(sc->sc_dev, 684 "interrupt map entry does not match INO (%d != %d)\n", 685 (int)INTINO(mr), ino); 686 return (0); 687 } 688 689 if (intrmapptr != NULL) 690 *intrmapptr = intrmap; 691 if (intrclrptr != NULL) 692 *intrclrptr = intrclr; 693 return (1); 694} 695 696/* 697 * Interrupt handlers 698 */ 699static int 700schizo_pci_bus(void *arg) 701{ 702 struct schizo_softc *sc = arg; 703 uint64_t afar, afsr, csr, iommu; 704 uint32_t status; 705 706 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 707 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 708 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 709 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 710 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 711 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 712 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0) { 713 if ((iommu & TOM_PCI_IOMMU_ERR) == 0) 714 goto clear_error; 715 716 /* These are non-fatal if target abort was signaled. */ 717 if ((status & PCIM_STATUS_STABORT) != 0 && 718 ((iommu & TOM_PCI_IOMMU_ERRMASK) == 719 TOM_PCI_IOMMU_INVALID_ERR || 720 (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) != 0 || 721 (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) != 0)) { 722 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 723 goto clear_error; 724 } 725 } 726 727 panic("%s: PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 728 "IOMMU %#llx STATUS %#llx", device_get_name(sc->sc_dev), 729 'A' + sc->sc_half, (unsigned long long)afar, 730 (unsigned long long)afsr, (unsigned long long)csr, 731 (unsigned long long)iommu, (unsigned long long)status); 732 733 clear_error: 734 if (bootverbose) 735 device_printf(sc->sc_dev, 736 "PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 737 "STATUS %#llx", 'A' + sc->sc_half, 738 (unsigned long long)afar, (unsigned long long)afsr, 739 (unsigned long long)csr, (unsigned long long)status); 740 /* Clear the error bits that we caught. */ 741 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 742 STX_CS_FUNC, PCIR_STATUS, status, 2); 743 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 744 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 745 return (FILTER_HANDLED); 746} 747 748static int 749schizo_ue(void *arg) 750{ 751 struct schizo_softc *sc = arg; 752 uint64_t afar, afsr; 753 int i; 754 755 mtx_lock_spin(sc->sc_mtx); 756 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 757 for (i = 0; i < 1000; i++) 758 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 759 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 760 break; 761 mtx_unlock_spin(sc->sc_mtx); 762 panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 763 device_get_name(sc->sc_dev), (unsigned long long)afar, 764 (unsigned long long)afsr); 765 return (FILTER_HANDLED); 766} 767 768static int 769schizo_ce(void *arg) 770{ 771 struct schizo_softc *sc = arg; 772 uint64_t afar, afsr; 773 int i; 774 775 mtx_lock_spin(sc->sc_mtx); 776 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 777 for (i = 0; i < 1000; i++) 778 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 779 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 780 break; 781 device_printf(sc->sc_dev, 782 "correctable DMA error AFAR %#llx AFSR %#llx\n", 783 (unsigned long long)afar, (unsigned long long)afsr); 784 /* Clear the error bits that we caught. */ 785 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 786 mtx_unlock_spin(sc->sc_mtx); 787 return (FILTER_HANDLED); 788} 789 790static int 791schizo_host_bus(void *arg) 792{ 793 struct schizo_softc *sc = arg; 794 uint64_t errlog; 795 796 errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 797 panic("%s: %s error %#llx", device_get_name(sc->sc_dev), 798 sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 799 (unsigned long long)errlog); 800 return (FILTER_HANDLED); 801} 802 803static void 804schizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 805{ 806 807 /* Punch in our copies. */ 808 sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 809 sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 810 sc->sc_is.is_iommu = STX_PCI_IOMMU; 811 sc->sc_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 812 sc->sc_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 813 sc->sc_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 814 sc->sc_is.is_dva = STX_PCI_IOMMU_SVADIAG; 815 sc->sc_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 816 817 iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, tsbsize, 818 dvmabase, 0); 819} 820 821static int 822schizo_maxslots(device_t dev) 823{ 824 struct schizo_softc *sc; 825 826 sc = device_get_softc(dev); 827 if (sc->sc_mode == SCHIZO_MODE_SCZ) 828 return (sc->sc_half == 0 ? 4 : 6); 829 830 /* XXX: is this correct? */ 831 return (PCI_SLOTMAX); 832} 833 834static uint32_t 835schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 836 int width) 837{ 838 struct schizo_softc *sc; 839 bus_space_handle_t bh; 840 u_long offset = 0; 841 uint32_t r, wrd; 842 int i; 843 uint16_t shrt; 844 uint8_t byte; 845 846 sc = device_get_softc(dev); 847 848 /* 849 * The Schizo bridges contain a dupe of their header at 0x80. 850 */ 851 if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 852 slot == STX_CS_DEVICE && func == STX_CS_FUNC && 853 reg + width > 0x80) 854 return (0); 855 856 offset = STX_CONF_OFF(bus, slot, func, reg); 857 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 858 switch (width) { 859 case 1: 860 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 861 r = byte; 862 break; 863 case 2: 864 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 865 r = shrt; 866 break; 867 case 4: 868 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 869 r = wrd; 870 break; 871 default: 872 panic("%s: bad width", __func__); 873 /* NOTREACHED */ 874 } 875 876 if (i) { 877#ifdef SCHIZO_DEBUG 878 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 879 __func__, bus, slot, func, reg); 880#endif 881 r = -1; 882 } 883 return (r); 884} 885 886static void 887schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 888 uint32_t val, int width) 889{ 890 struct schizo_softc *sc; 891 bus_space_handle_t bh; 892 u_long offset = 0; 893 894 sc = device_get_softc(dev); 895 offset = STX_CONF_OFF(bus, slot, func, reg); 896 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 897 switch (width) { 898 case 1: 899 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 900 break; 901 case 2: 902 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 903 break; 904 case 4: 905 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 906 break; 907 default: 908 panic("%s: bad width", __func__); 909 /* NOTREACHED */ 910 } 911} 912 913static int 914schizo_route_interrupt(device_t bridge, device_t dev, int pin) 915{ 916 struct schizo_softc *sc; 917 struct ofw_pci_register reg; 918 ofw_pci_intr_t pintr, mintr; 919 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 920 921 sc = device_get_softc(bridge); 922 pintr = pin; 923 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 924 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 925 return (mintr); 926 927 device_printf(bridge, "could not route pin %d for device %d.%d\n", 928 pin, pci_get_slot(dev), pci_get_function(dev)); 929 return (PCI_INVALID_IRQ); 930} 931 932static int 933schizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 934{ 935 struct schizo_softc *sc; 936 937 sc = device_get_softc(dev); 938 switch (which) { 939 case PCIB_IVAR_DOMAIN: 940 *result = device_get_unit(dev); 941 return (0); 942 case PCIB_IVAR_BUS: 943 *result = sc->sc_pci_secbus; 944 return (0); 945 } 946 return (ENOENT); 947} 948 949#define VIS_BLOCKSIZE 64 950 951static int 952schizo_dmasync(void *arg) 953{ 954 static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 955 struct schizo_dmasync *sds = arg; 956 struct schizo_softc *sc = sds->sds_sc; 957 register_t reg, s; 958 int timeout; 959 960 SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, sds->sds_syncval); 961 timeout = 1000000; 962 for (; (SCHIZO_PCI_READ_8(sc, TOMXMS_PCI_DMA_SYNC_PEND) & 963 sds->sds_syncval) != 0;) 964 if (--timeout < 0) 965 panic("%s: DMA does not sync", __func__); 966 967 if (sds->sds_bswar != 0) { 968 s = intr_disable(); 969 reg = rd(fprs); 970 wr(fprs, reg | FPRS_FEF, 0); 971 __asm __volatile("stda %%f0, [%0] %1" 972 : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 973 membar(Sync); 974 wr(fprs, reg, 0); 975 intr_restore(s); 976 } 977 return (sds->sds_handler(sds->sds_arg)); 978} 979 980static void 981schizo_intr_enable(void *arg) 982{ 983 struct intr_vector *iv = arg; 984 struct schizo_icarg *sica = iv->iv_icarg; 985 986 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 987 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 988} 989 990static void 991schizo_intr_disable(void *arg) 992{ 993 struct intr_vector *iv = arg; 994 struct schizo_icarg *sica = iv->iv_icarg; 995 996 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 997} 998 999static void 1000schizo_intr_assign(void *arg) 1001{ 1002 struct intr_vector *iv = arg; 1003 struct schizo_icarg *sica = iv->iv_icarg; 1004 1005 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1006 SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1007} 1008 1009static void 1010schizo_intr_clear(void *arg) 1011{ 1012 struct intr_vector *iv = arg; 1013 struct schizo_icarg *sica = iv->iv_icarg; 1014 1015 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, 0); 1016} 1017 1018static int 1019schizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1020 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1021 void **cookiep) 1022{ 1023 struct schizo_dmasync *sds; 1024 struct schizo_softc *sc; 1025 u_long vec; 1026 int error; 1027 1028 sc = device_get_softc(dev); 1029 /* 1030 * Make sure the vector is fully specified and we registered 1031 * our interrupt controller for it. 1032 */ 1033 vec = rman_get_start(ires); 1034 if (INTIGN(vec) != sc->sc_ign || 1035 intr_vectors[vec].iv_ic != &schizo_ic) { 1036 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1037 return (EINVAL); 1038 } 1039 1040 /* 1041 * Tomatillo and XMITS bridges need to be told to sync DMA writes 1042 * based on the INO of the respective device. 1043 * Tomatillo revision <= 2.3 (i.e. version <= 4) bridges additionally 1044 * need a block store as a workaround for a hardware bug. 1045 * XXX setup of the wrapper and the contents of schizo_dmasync() 1046 * should be moved to schizo(4)-specific bus_dma_tag_create() and 1047 * bus_dmamap_sync() methods, respectively, once DMA tag creation 1048 * is newbus'ified, so the wrapper isn't only applied for interrupt 1049 * handlers but also for polling(4) callbacks. 1050 */ 1051 if (sc->sc_mode == SCHIZO_MODE_TOM || sc->sc_mode == SCHIZO_MODE_XMS) { 1052 sds = malloc(sizeof(*sds), M_DEVBUF, M_NOWAIT | M_ZERO); 1053 if (sds == NULL) 1054 return (ENOMEM); 1055 sds->sds_sc = sc; 1056 sds->sds_arg = arg; 1057 sds->sds_syncval = 1ULL << INTINO(vec); 1058 if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 1059 sds->sds_bswar = 1; 1060 if (intr == NULL) { 1061 sds->sds_handler = filt; 1062 error = bus_generic_setup_intr(dev, child, ires, 1063 flags, schizo_dmasync, intr, sds, cookiep); 1064 } else { 1065 sds->sds_handler = (driver_filter_t *)intr; 1066 error = bus_generic_setup_intr(dev, child, ires, 1067 flags, filt, (driver_intr_t *)schizo_dmasync, 1068 sds, cookiep); 1069 } 1070 if (error != 0) { 1071 free(sds, M_DEVBUF); 1072 return (error); 1073 } 1074 sds->sds_cookie = *cookiep; 1075 *cookiep = sds; 1076 return (error); 1077 } 1078 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1079 arg, cookiep)); 1080} 1081 1082static int 1083schizo_teardown_intr(device_t dev, device_t child, struct resource *vec, 1084 void *cookie) 1085{ 1086 struct schizo_dmasync *sds; 1087 struct schizo_softc *sc; 1088 int error; 1089 1090 sc = device_get_softc(dev); 1091 if (sc->sc_mode == SCHIZO_MODE_TOM) { 1092 sds = cookie; 1093 error = bus_generic_teardown_intr(dev, child, vec, 1094 sds->sds_cookie); 1095 if (error == 0) 1096 free(sds, M_DEVBUF); 1097 return (error); 1098 } 1099 return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1100} 1101 1102static struct resource * 1103schizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1104 u_long start, u_long end, u_long count, u_int flags) 1105{ 1106 struct schizo_softc *sc; 1107 struct resource *rv; 1108 struct rman *rm; 1109 bus_space_tag_t bt; 1110 bus_space_handle_t bh; 1111 int needactivate = flags & RF_ACTIVE; 1112 1113 flags &= ~RF_ACTIVE; 1114 1115 sc = device_get_softc(bus); 1116 if (type == SYS_RES_IRQ) { 1117 /* 1118 * XXX: Don't accept blank ranges for now, only single 1119 * interrupts. The other case should not happen with 1120 * the MI PCI code... 1121 * XXX: This may return a resource that is out of the 1122 * range that was specified. Is this correct...? 1123 */ 1124 if (start != end) 1125 panic("%s: XXX: interrupt range", __func__); 1126 start = end = INTMAP_VEC(sc->sc_ign, end); 1127 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1128 rid, start, end, count, flags)); 1129 } 1130 switch (type) { 1131 case SYS_RES_MEMORY: 1132 rm = &sc->sc_pci_mem_rman; 1133 bt = sc->sc_pci_memt; 1134 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1135 break; 1136 case SYS_RES_IOPORT: 1137 rm = &sc->sc_pci_io_rman; 1138 bt = sc->sc_pci_iot; 1139 bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1140 break; 1141 default: 1142 return (NULL); 1143 /* NOTREACHED */ 1144 } 1145 1146 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1147 if (rv == NULL) 1148 return (NULL); 1149 rman_set_rid(rv, *rid); 1150 bh += rman_get_start(rv); 1151 rman_set_bustag(rv, bt); 1152 rman_set_bushandle(rv, bh); 1153 1154 if (needactivate) { 1155 if (bus_activate_resource(child, type, *rid, rv)) { 1156 rman_release_resource(rv); 1157 return (NULL); 1158 } 1159 } 1160 return (rv); 1161} 1162 1163static int 1164schizo_activate_resource(device_t bus, device_t child, int type, int rid, 1165 struct resource *r) 1166{ 1167 void *p; 1168 int error; 1169 1170 if (type == SYS_RES_IRQ) 1171 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1172 type, rid, r)); 1173 if (type == SYS_RES_MEMORY) { 1174 /* 1175 * Need to memory-map the device space, as some drivers depend 1176 * on the virtual address being set and useable. 1177 */ 1178 error = sparc64_bus_mem_map(rman_get_bustag(r), 1179 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1180 if (error != 0) 1181 return (error); 1182 rman_set_virtual(r, p); 1183 } 1184 return (rman_activate_resource(r)); 1185} 1186 1187static int 1188schizo_deactivate_resource(device_t bus, device_t child, int type, int rid, 1189 struct resource *r) 1190{ 1191 1192 if (type == SYS_RES_IRQ) 1193 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1194 type, rid, r)); 1195 if (type == SYS_RES_MEMORY) { 1196 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1197 rman_set_virtual(r, NULL); 1198 } 1199 return (rman_deactivate_resource(r)); 1200} 1201 1202static int 1203schizo_release_resource(device_t bus, device_t child, int type, int rid, 1204 struct resource *r) 1205{ 1206 int error; 1207 1208 if (type == SYS_RES_IRQ) 1209 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1210 type, rid, r)); 1211 if (rman_get_flags(r) & RF_ACTIVE) { 1212 error = bus_deactivate_resource(child, type, rid, r); 1213 if (error) 1214 return (error); 1215 } 1216 return (rman_release_resource(r)); 1217} 1218 1219static bus_dma_tag_t 1220schizo_get_dma_tag(device_t bus, device_t child) 1221{ 1222 struct schizo_softc *sc; 1223 1224 sc = device_get_softc(bus); 1225 return (sc->sc_pci_dmat); 1226} 1227 1228static phandle_t 1229schizo_get_node(device_t bus, device_t dev) 1230{ 1231 struct schizo_softc *sc; 1232 1233 sc = device_get_softc(bus); 1234 /* We only have one child, the PCI bus, which needs our own node. */ 1235 return (sc->sc_node); 1236} 1237 1238static bus_space_tag_t 1239schizo_alloc_bus_tag(struct schizo_softc *sc, int type) 1240{ 1241 bus_space_tag_t bt; 1242 1243 bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1244 M_NOWAIT | M_ZERO); 1245 if (bt == NULL) 1246 panic("%s: out of memory", __func__); 1247 1248 bt->bst_cookie = sc; 1249 bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1250 bt->bst_type = type; 1251 return (bt); 1252} 1253 1254static u_int 1255schizo_get_timecount(struct timecounter *tc) 1256{ 1257 struct schizo_softc *sc; 1258 1259 sc = tc->tc_priv; 1260 return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1261 (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)); 1262} 1263