schizo.c revision 183423
1183423Smarius/*- 2183423Smarius * Copyright (c) 1999, 2000 Matthew R. Green 3183423Smarius * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4183423Smarius * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org> 5183423Smarius * All rights reserved. 6183423Smarius * 7183423Smarius * Redistribution and use in source and binary forms, with or without 8183423Smarius * modification, are permitted provided that the following conditions 9183423Smarius * are met: 10183423Smarius * 1. Redistributions of source code must retain the above copyright 11183423Smarius * notice, this list of conditions and the following disclaimer. 12183423Smarius * 2. Redistributions in binary form must reproduce the above copyright 13183423Smarius * notice, this list of conditions and the following disclaimer in the 14183423Smarius * documentation and/or other materials provided with the distribution. 15183423Smarius * 3. The name of the author may not be used to endorse or promote products 16183423Smarius * derived from this software without specific prior written permission. 17183423Smarius * 18183423Smarius * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19183423Smarius * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20183423Smarius * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21183423Smarius * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22183423Smarius * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23183423Smarius * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24183423Smarius * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25183423Smarius * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26183423Smarius * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27183423Smarius * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28183423Smarius * SUCH DAMAGE. 29183423Smarius * 30183423Smarius * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31183423Smarius * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32183423Smarius */ 33183423Smarius 34183423Smarius#include <sys/cdefs.h> 35183423Smarius__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 183423 2008-09-28 00:07:05Z marius $"); 36183423Smarius 37183423Smarius/* 38183423Smarius * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to 39183423Smarius * PCI 2.2 bridges 40183423Smarius */ 41183423Smarius 42183423Smarius#include "opt_ofw_pci.h" 43183423Smarius#include "opt_schizo.h" 44183423Smarius 45183423Smarius#include <sys/param.h> 46183423Smarius#include <sys/systm.h> 47183423Smarius#include <sys/bus.h> 48183423Smarius#include <sys/kernel.h> 49183423Smarius#include <sys/lock.h> 50183423Smarius#include <sys/malloc.h> 51183423Smarius#include <sys/module.h> 52183423Smarius#include <sys/mutex.h> 53183423Smarius#include <sys/pcpu.h> 54183423Smarius#include <sys/rman.h> 55183423Smarius#include <sys/timetc.h> 56183423Smarius 57183423Smarius#include <dev/ofw/ofw_bus.h> 58183423Smarius#include <dev/ofw/ofw_pci.h> 59183423Smarius#include <dev/ofw/openfirm.h> 60183423Smarius 61183423Smarius#include <machine/bus.h> 62183423Smarius#include <machine/bus_common.h> 63183423Smarius#include <machine/bus_private.h> 64183423Smarius#include <machine/fsr.h> 65183423Smarius#include <machine/iommureg.h> 66183423Smarius#include <machine/iommuvar.h> 67183423Smarius#include <machine/ofw_bus.h> 68183423Smarius#include <machine/resource.h> 69183423Smarius 70183423Smarius#include <dev/pci/pcireg.h> 71183423Smarius#include <dev/pci/pcivar.h> 72183423Smarius 73183423Smarius#include <sparc64/pci/ofw_pci.h> 74183423Smarius#include <sparc64/pci/schizoreg.h> 75183423Smarius#include <sparc64/pci/schizovar.h> 76183423Smarius 77183423Smarius#include "pcib_if.h" 78183423Smarius 79183423Smariusstatic const struct schizo_desc *schizo_get_desc(device_t); 80183423Smariusstatic void schizo_set_intr(struct schizo_softc *, u_int, u_int, 81183423Smarius driver_filter_t); 82183423Smariusstatic driver_filter_t schizo_dmasync; 83183423Smariusstatic void schizo_intr_enable(void *); 84183423Smariusstatic void schizo_intr_disable(void *); 85183423Smariusstatic void schizo_intr_assign(void *); 86183423Smariusstatic void schizo_intr_clear(void *); 87183423Smariusstatic int schizo_get_intrmap(struct schizo_softc *, u_int, 88183423Smarius bus_addr_t *, bus_addr_t *); 89183423Smariusstatic bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int); 90183423Smariusstatic timecounter_get_t schizo_get_timecount; 91183423Smarius 92183423Smarius/* Interrupt handlers */ 93183423Smariusstatic driver_filter_t schizo_pci_bus; 94183423Smariusstatic driver_filter_t schizo_ue; 95183423Smariusstatic driver_filter_t schizo_ce; 96183423Smariusstatic driver_filter_t schizo_host_bus; 97183423Smarius 98183423Smarius/* IOMMU support */ 99183423Smariusstatic void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 100183423Smarius 101183423Smarius/* 102183423Smarius * Methods 103183423Smarius */ 104183423Smariusstatic device_probe_t schizo_probe; 105183423Smariusstatic device_attach_t schizo_attach; 106183423Smariusstatic bus_read_ivar_t schizo_read_ivar; 107183423Smariusstatic bus_setup_intr_t schizo_setup_intr; 108183423Smariusstatic bus_teardown_intr_t schizo_teardown_intr; 109183423Smariusstatic bus_alloc_resource_t schizo_alloc_resource; 110183423Smariusstatic bus_activate_resource_t schizo_activate_resource; 111183423Smariusstatic bus_deactivate_resource_t schizo_deactivate_resource; 112183423Smariusstatic bus_release_resource_t schizo_release_resource; 113183423Smariusstatic bus_get_dma_tag_t schizo_get_dma_tag; 114183423Smariusstatic pcib_maxslots_t schizo_maxslots; 115183423Smariusstatic pcib_read_config_t schizo_read_config; 116183423Smariusstatic pcib_write_config_t schizo_write_config; 117183423Smariusstatic pcib_route_interrupt_t schizo_route_interrupt; 118183423Smariusstatic ofw_bus_get_node_t schizo_get_node; 119183423Smarius 120183423Smariusstatic device_method_t schizo_methods[] = { 121183423Smarius /* Device interface */ 122183423Smarius DEVMETHOD(device_probe, schizo_probe), 123183423Smarius DEVMETHOD(device_attach, schizo_attach), 124183423Smarius DEVMETHOD(device_shutdown, bus_generic_shutdown), 125183423Smarius DEVMETHOD(device_suspend, bus_generic_suspend), 126183423Smarius DEVMETHOD(device_resume, bus_generic_resume), 127183423Smarius 128183423Smarius /* Bus interface */ 129183423Smarius DEVMETHOD(bus_print_child, bus_generic_print_child), 130183423Smarius DEVMETHOD(bus_read_ivar, schizo_read_ivar), 131183423Smarius DEVMETHOD(bus_setup_intr, schizo_setup_intr), 132183423Smarius DEVMETHOD(bus_teardown_intr, schizo_teardown_intr), 133183423Smarius DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 134183423Smarius DEVMETHOD(bus_activate_resource, schizo_activate_resource), 135183423Smarius DEVMETHOD(bus_deactivate_resource, schizo_deactivate_resource), 136183423Smarius DEVMETHOD(bus_release_resource, schizo_release_resource), 137183423Smarius DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag), 138183423Smarius 139183423Smarius /* pcib interface */ 140183423Smarius DEVMETHOD(pcib_maxslots, schizo_maxslots), 141183423Smarius DEVMETHOD(pcib_read_config, schizo_read_config), 142183423Smarius DEVMETHOD(pcib_write_config, schizo_write_config), 143183423Smarius DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 144183423Smarius 145183423Smarius /* ofw_bus interface */ 146183423Smarius DEVMETHOD(ofw_bus_get_node, schizo_get_node), 147183423Smarius 148183423Smarius { 0, 0 } 149183423Smarius}; 150183423Smarius 151183423Smariusstatic devclass_t schizo_devclass; 152183423Smarius 153183423SmariusDEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 154183423Smarius sizeof(struct schizo_softc)); 155183423SmariusDRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0); 156183423Smarius 157183423Smariusstatic SLIST_HEAD(, schizo_softc) schizo_softcs = 158183423Smarius SLIST_HEAD_INITIALIZER(schizo_softcs); 159183423Smarius 160183423Smariusstatic const struct intr_controller schizo_ic = { 161183423Smarius schizo_intr_enable, 162183423Smarius schizo_intr_disable, 163183423Smarius schizo_intr_assign, 164183423Smarius schizo_intr_clear 165183423Smarius}; 166183423Smarius 167183423Smariusstruct schizo_icarg { 168183423Smarius struct schizo_softc *sica_sc; 169183423Smarius bus_addr_t sica_map; 170183423Smarius bus_addr_t sica_clr; 171183423Smarius}; 172183423Smarius 173183423Smariusstruct schizo_dmasync { 174183423Smarius struct schizo_softc *sds_sc; 175183423Smarius driver_filter_t *sds_handler; 176183423Smarius void *sds_arg; 177183423Smarius void *sds_cookie; 178183423Smarius bus_size_t sds_syncreg; 179183423Smarius uint64_t sds_syncval; 180183423Smarius u_int sds_bswar; 181183423Smarius}; 182183423Smarius 183183423Smarius#define SCHIZO_PERF_CNT_QLTY 100 184183423Smarius 185183423Smarius#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 186183423Smarius bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 187183423Smarius#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 188183423Smarius bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 189183423Smarius 190183423Smarius#define SCHIZO_PCI_READ_8(sc, offs) \ 191183423Smarius SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 192183423Smarius#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 193183423Smarius SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 194183423Smarius#define SCHIZO_CTRL_READ_8(sc, offs) \ 195183423Smarius SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 196183423Smarius#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 197183423Smarius SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 198183423Smarius#define SCHIZO_PCICFG_READ_8(sc, offs) \ 199183423Smarius SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 200183423Smarius#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 201183423Smarius SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 202183423Smarius#define SCHIZO_ICON_READ_8(sc, offs) \ 203183423Smarius SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 204183423Smarius#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 205183423Smarius SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 206183423Smarius 207183423Smarius#define OFW_PCI_TYPE "pci" 208183423Smarius 209183423Smariusstruct schizo_desc { 210183423Smarius const char *sd_string; 211183423Smarius int sd_mode; 212183423Smarius const char *sd_name; 213183423Smarius}; 214183423Smarius 215183423Smariusstatic const struct schizo_desc schizo_compats[] = { 216183423Smarius { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 217183423Smarius { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 218183423Smarius { NULL, 0, NULL } 219183423Smarius}; 220183423Smarius 221183423Smariusstatic const struct schizo_desc * 222183423Smariusschizo_get_desc(device_t dev) 223183423Smarius{ 224183423Smarius const struct schizo_desc *desc; 225183423Smarius const char *compat; 226183423Smarius 227183423Smarius compat = ofw_bus_get_compat(dev); 228183423Smarius if (compat == NULL) 229183423Smarius return (NULL); 230183423Smarius for (desc = schizo_compats; desc->sd_string != NULL; desc++) 231183423Smarius if (strcmp(desc->sd_string, compat) == 0) 232183423Smarius return (desc); 233183423Smarius return (NULL); 234183423Smarius} 235183423Smarius 236183423Smariusstatic int 237183423Smariusschizo_probe(device_t dev) 238183423Smarius{ 239183423Smarius const char *dtype; 240183423Smarius 241183423Smarius dtype = ofw_bus_get_type(dev); 242183423Smarius if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 && 243183423Smarius schizo_get_desc(dev) != NULL) { 244183423Smarius device_set_desc(dev, "Sun Host-PCI bridge"); 245183423Smarius return (0); 246183423Smarius } 247183423Smarius return (ENXIO); 248183423Smarius} 249183423Smarius 250183423Smariusstatic int 251183423Smariusschizo_attach(device_t dev) 252183423Smarius{ 253183423Smarius struct ofw_pci_ranges *range; 254183423Smarius const struct schizo_desc *desc; 255183423Smarius struct schizo_icarg *sica; 256183423Smarius struct schizo_softc *asc, *sc, *osc; 257183423Smarius struct timecounter *tc; 258183423Smarius bus_addr_t intrclr, intrmap; 259183423Smarius uint64_t ino_bitmap, reg; 260183423Smarius phandle_t node; 261183423Smarius uint32_t prop, prop_array[2]; 262183423Smarius int i, mode, n, nrange, rid, tsbsize; 263183423Smarius 264183423Smarius sc = device_get_softc(dev); 265183423Smarius node = ofw_bus_get_node(dev); 266183423Smarius desc = schizo_get_desc(dev); 267183423Smarius mode = desc->sd_mode; 268183423Smarius 269183423Smarius sc->sc_dev = dev; 270183423Smarius sc->sc_node = node; 271183423Smarius sc->sc_mode = mode; 272183423Smarius 273183423Smarius /* 274183423Smarius * The Schizo has three register banks: 275183423Smarius * (0) per-PBM PCI configuration and status registers, but for bus B 276183423Smarius * shared with the UPA64s interrupt mapping register banks 277183423Smarius * (1) shared Schizo controller configuration and status registers 278183423Smarius * (2) per-PBM PCI configuration space 279183423Smarius * 280183423Smarius * The Tomatillo has four register banks: 281183423Smarius * (0) per-PBM PCI configuration and status registers 282183423Smarius * (1) per-PBM Tomatillo controller configuration registers, but on 283183423Smarius * machines having the `jbusppm' device shared with its Estar 284183423Smarius * register bank for bus A 285183423Smarius * (2) per-PBM PCI configuration space 286183423Smarius * (3) per-PBM interrupt concentrator registers 287183423Smarius */ 288183423Smarius sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 289183423Smarius 20) & 1; 290183423Smarius for (n = 0; n < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 291183423Smarius n++) { 292183423Smarius rid = n; 293183423Smarius sc->sc_mem_res[n] = bus_alloc_resource_any(dev, 294183423Smarius SYS_RES_MEMORY, &rid, 295183423Smarius (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 296183423Smarius n == STX_PCI) || n == STX_CTRL)) || 297183423Smarius (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 298183423Smarius n == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 299183423Smarius if (sc->sc_mem_res[n] == NULL) 300183423Smarius panic("%s: could not allocate register bank %d", 301183423Smarius __func__, n); 302183423Smarius } 303183423Smarius 304183423Smarius /* 305183423Smarius * Match other Schizos that are already configured against 306183423Smarius * the controller base physical address. This will be the 307183423Smarius * same for a pair of devices that share register space. 308183423Smarius */ 309183423Smarius osc = NULL; 310183423Smarius SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 311183423Smarius if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 312183423Smarius rman_get_start(sc->sc_mem_res[STX_CTRL])) { 313183423Smarius /* Found partner. */ 314183423Smarius osc = asc; 315183423Smarius break; 316183423Smarius } 317183423Smarius } 318183423Smarius if (osc == NULL) { 319183423Smarius sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 320183423Smarius M_NOWAIT | M_ZERO); 321183423Smarius if (sc->sc_mtx == NULL) 322183423Smarius panic("%s: could not malloc mutex", __func__); 323183423Smarius mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 324183423Smarius } else { 325183423Smarius if (mtx_initialized(osc->sc_mtx) == 0) 326183423Smarius panic("%s: mutex not initialized", __func__); 327183423Smarius sc->sc_mtx = osc->sc_mtx; 328183423Smarius } 329183423Smarius 330183423Smarius if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 331183423Smarius panic("%s: could not determine IGN", __func__); 332183423Smarius if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == -1) 333183423Smarius panic("%s: could not determine version", __func__); 334183423Smarius if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 335183423Smarius prop = 33000000; 336183423Smarius 337183423Smarius device_printf(dev, "%s, version %d, IGN %#x, bus %c, %dMHz\n", 338183423Smarius desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half, 339183423Smarius prop / 1000 / 1000); 340183423Smarius 341183423Smarius /* Set up the PCI interrupt retry timer. */ 342183423Smarius#ifdef SCHIZO_DEBUG 343183423Smarius device_printf(dev, "PCI IRT 0x%016llx\n", (unsigned long long) 344183423Smarius SCHIZO_PCI_READ_8(sc, STX_PCI_INTR_RETRY_TIM)); 345183423Smarius#endif 346183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_INTR_RETRY_TIM, 5); 347183423Smarius 348183423Smarius /* Set up the PCI control register. */ 349183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 350183423Smarius reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 351183423Smarius STX_PCI_CTRL_ERR_IEN | STX_PCI_CTRL_ARB_MASK; 352183423Smarius reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK); 353183423Smarius if (OF_getproplen(node, "no-bus-parking") < 0) 354183423Smarius reg |= STX_PCI_CTRL_ARB_PARK; 355183423Smarius if (mode == SCHIZO_MODE_TOM) { 356183423Smarius reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 357183423Smarius if (sc->sc_ver <= 1) /* revision <= 2.0 */ 358183423Smarius reg |= TOM_PCI_CTRL_DTO_IEN; 359183423Smarius else 360183423Smarius reg |= STX_PCI_CTRL_PTO; 361183423Smarius } 362183423Smarius#ifdef SCHIZO_DEBUG 363183423Smarius device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 364183423Smarius (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL), 365183423Smarius (unsigned long long)reg); 366183423Smarius#endif 367183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, reg); 368183423Smarius 369183423Smarius /* Set up the PCI diagnostic register. */ 370183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 371183423Smarius reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 372183423Smarius STX_PCI_DIAG_INTRSYNC_DIS); 373183423Smarius#ifdef SCHIZO_DEBUG 374183423Smarius device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 375183423Smarius (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG), 376183423Smarius (unsigned long long)reg); 377183423Smarius#endif 378183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg); 379183423Smarius 380183423Smarius /* 381183423Smarius * On Tomatillo clear the I/O prefetch lengths (workaround for a 382183423Smarius * Jalapeno bug). 383183423Smarius */ 384183423Smarius if (mode == SCHIZO_MODE_TOM) 385183423Smarius SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 386183423Smarius (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 387183423Smarius TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 388183423Smarius 389183423Smarius /* 390183423Smarius * Hunt through all the interrupt mapping regs and register 391183423Smarius * the interrupt controller for our interrupt vectors. This 392183423Smarius * is complicated by the fact that a pair of Schizo PBMs 393183423Smarius * share one IGN. 394183423Smarius */ 395183423Smarius n = OF_getprop(node, "ino-bitmap", (void *)prop_array, 396183423Smarius sizeof(prop_array)); 397183423Smarius if (n == -1) 398183423Smarius panic("%s: could not get ino-bitmap", __func__); 399183423Smarius ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 400183423Smarius for (n = 0; n <= STX_MAX_INO; n++) { 401183423Smarius if ((ino_bitmap & (1ULL << n)) == 0) 402183423Smarius continue; 403183423Smarius if (n == STX_FB0_INO || n == STX_FB1_INO) 404183423Smarius /* Leave for upa(4). */ 405183423Smarius continue; 406183423Smarius if (schizo_get_intrmap(sc, n, &intrmap, &intrclr) == 0) 407183423Smarius continue; 408183423Smarius sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 409183423Smarius if (sica == NULL) 410183423Smarius panic("%s: could not allocate interrupt controller " 411183423Smarius "argument", __func__); 412183423Smarius sica->sica_sc = sc; 413183423Smarius sica->sica_map = intrmap; 414183423Smarius sica->sica_clr = intrclr; 415183423Smarius#ifdef SCHIZO_DEBUG 416183423Smarius device_printf(dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 417183423Smarius n, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 418183423Smarius (u_long)intrclr); 419183423Smarius#endif 420183423Smarius if (intr_controller_register(INTMAP_VEC(sc->sc_ign, n), 421183423Smarius &schizo_ic, sica) != 0) 422183423Smarius panic("%s: could not register interrupt controller " 423183423Smarius "for INO %d", __func__, n); 424183423Smarius } 425183423Smarius 426183423Smarius /* 427183423Smarius * Setup Safari/JBus performance counter 0 in bus cycle counting 428183423Smarius * mode as timecounter. Unfortunately, this is broken with at 429183423Smarius * least the version 4 Tomatillos found in Fire V120 and Blade 430183423Smarius * 1500, which apparently actually count some different event at 431183423Smarius * ~0.5 and 3MHz respectively instead (also when running in full 432183423Smarius * power mode). Besides, one counter seems to be shared by a 433183423Smarius * "pair" of Tomatillos, too. 434183423Smarius */ 435183423Smarius if (sc->sc_half == 0) { 436183423Smarius SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_PERF, 437183423Smarius (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 438183423Smarius (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 439183423Smarius tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 440183423Smarius if (tc == NULL) 441183423Smarius panic("%s: could not malloc timecounter", __func__); 442183423Smarius tc->tc_get_timecount = schizo_get_timecount; 443183423Smarius tc->tc_poll_pps = NULL; 444183423Smarius tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 445183423Smarius if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 446183423Smarius sizeof(prop)) == -1) 447183423Smarius panic("%s: could not determine clock frequency", 448183423Smarius __func__); 449183423Smarius tc->tc_frequency = prop; 450183423Smarius tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 451183423Smarius if (mode == SCHIZO_MODE_SCZ) 452183423Smarius tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 453183423Smarius else 454183423Smarius tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 455183423Smarius tc->tc_priv = sc; 456183423Smarius tc_init(tc); 457183423Smarius } 458183423Smarius 459183423Smarius /* Set up the IOMMU. Both Schizo and Tomatillo have one per PBM. */ 460183423Smarius sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 461183423Smarius sc->sc_is.is_sb[0] = 0; 462183423Smarius sc->sc_is.is_sb[1] = 0; 463183423Smarius if (OF_getproplen(node, "no-streaming-cache") < 0) 464183423Smarius sc->sc_is.is_sb[0] = STX_PCI_STRBUF; 465183423Smarius 466183423Smarius#define TSBCASE(x) \ 467183423Smarius case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 468183423Smarius tsbsize = (x); \ 469183423Smarius break; \ 470183423Smarius 471183423Smarius n = OF_getprop(node, "virtual-dma", (void *)prop_array, 472183423Smarius sizeof(prop_array)); 473183423Smarius if (n == -1 || n != sizeof(prop_array)) 474183423Smarius schizo_iommu_init(sc, 7, -1); 475183423Smarius else { 476183423Smarius switch (prop_array[1]) { 477183423Smarius TSBCASE(1); 478183423Smarius TSBCASE(2); 479183423Smarius TSBCASE(3); 480183423Smarius TSBCASE(4); 481183423Smarius TSBCASE(5); 482183423Smarius TSBCASE(6); 483183423Smarius TSBCASE(7); 484183423Smarius TSBCASE(8); 485183423Smarius default: 486183423Smarius panic("%s: unsupported DVMA size 0x%x", 487183423Smarius __func__, prop_array[1]); 488183423Smarius /* NOTREACHED */ 489183423Smarius } 490183423Smarius schizo_iommu_init(sc, tsbsize, prop_array[0]); 491183423Smarius } 492183423Smarius#undef TSBCASE 493183423Smarius 494183423Smarius /* Initialize memory and I/O rmans. */ 495183423Smarius sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 496183423Smarius sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports"; 497183423Smarius if (rman_init(&sc->sc_pci_io_rman) != 0 || 498183423Smarius rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0) 499183423Smarius panic("%s: failed to set up I/O rman", __func__); 500183423Smarius sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 501183423Smarius sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory"; 502183423Smarius if (rman_init(&sc->sc_pci_mem_rman) != 0 || 503183423Smarius rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0) 504183423Smarius panic("%s: failed to set up memory rman", __func__); 505183423Smarius 506183423Smarius nrange = OF_getprop_alloc(node, "ranges", sizeof(*range), 507183423Smarius (void **)&range); 508183423Smarius /* 509183423Smarius * Make sure that the expected ranges are present. The 510183423Smarius * OFW_PCI_CS_MEM64 one is not currently used though. 511183423Smarius */ 512183423Smarius if (nrange != STX_NRANGE) 513183423Smarius panic("%s: unsupported number of ranges", __func__); 514183423Smarius /* 515183423Smarius * Find the addresses of the various bus spaces. 516183423Smarius * There should not be multiple ones of one kind. 517183423Smarius * The physical start addresses of the ranges are the configuration, 518183423Smarius * memory and I/O handles. 519183423Smarius */ 520183423Smarius for (n = 0; n < STX_NRANGE; n++) { 521183423Smarius i = OFW_PCI_RANGE_CS(&range[n]); 522183423Smarius if (sc->sc_pci_bh[i] != 0) 523183423Smarius panic("%s: duplicate range for space %d", __func__, i); 524183423Smarius sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]); 525183423Smarius } 526183423Smarius free(range, M_OFWPROP); 527183423Smarius 528183423Smarius /* Register the softc, this is needed for paired Schizos. */ 529183423Smarius SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 530183423Smarius 531183423Smarius /* Allocate our tags. */ 532183423Smarius sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 533183423Smarius sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 534183423Smarius sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 535183423Smarius if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 536183423Smarius sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr, 537183423Smarius 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 538183423Smarius panic("%s: bus_dma_tag_create failed", __func__); 539183423Smarius /* Customize the tag. */ 540183423Smarius sc->sc_pci_dmat->dt_cookie = &sc->sc_is; 541183423Smarius sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 542183423Smarius 543183423Smarius /* 544183423Smarius * Get the bus range from the firmware. 545183423Smarius * NB: Tomatillos don't support PCI bus reenumeration. 546183423Smarius */ 547183423Smarius n = OF_getprop(node, "bus-range", (void *)prop_array, 548183423Smarius sizeof(prop_array)); 549183423Smarius if (n == -1) 550183423Smarius panic("%s: could not get bus-range", __func__); 551183423Smarius if (n != sizeof(prop_array)) 552183423Smarius panic("%s: broken bus-range (%d)", __func__, n); 553183423Smarius if (bootverbose) 554183423Smarius device_printf(dev, "bus range %u to %u; PCI bus %d\n", 555183423Smarius prop_array[0], prop_array[1], prop_array[0]); 556183423Smarius sc->sc_pci_secbus = prop_array[0]; 557183423Smarius 558183423Smarius /* Clear any pending PCI error bits. */ 559183423Smarius PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 560183423Smarius PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 561183423Smarius STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2); 562183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, 563183423Smarius SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 564183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, 565183423Smarius SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 566183423Smarius 567183423Smarius /* 568183423Smarius * Establish handlers for interesting interrupts... 569183423Smarius * Someone at Sun clearly was smoking crack; with Schizos PCI 570183423Smarius * bus error interrupts for one PBM can be routed to the other 571183423Smarius * PBM though we obviously need to use the softc of the former 572183423Smarius * as the argument for the interrupt handler and the softc of 573183423Smarius * the latter as the argument for the interrupt controller. 574183423Smarius */ 575183423Smarius if (sc->sc_half == 0) { 576183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 577183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 578183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 579183423Smarius sica_sc == osc)) 580183423Smarius /* 581183423Smarius * We are the driver for PBM A and either also 582183423Smarius * registered the interrupt controller for us or 583183423Smarius * the driver for PBM B has probed first and 584183423Smarius * registered it for us. 585183423Smarius */ 586183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 587183423Smarius schizo_pci_bus); 588183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 589183423Smarius osc != NULL) 590183423Smarius /* 591183423Smarius * We are the driver for PBM A but registered 592183423Smarius * the interrupt controller for PBM B, i.e. the 593183423Smarius * driver for PBM B attached first but couldn't 594183423Smarius * set up a handler for PBM B. 595183423Smarius */ 596183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 597183423Smarius schizo_pci_bus); 598183423Smarius } else { 599183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 600183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 601183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 602183423Smarius sica_sc == osc)) 603183423Smarius /* 604183423Smarius * We are the driver for PBM B and either also 605183423Smarius * registered the interrupt controller for us or 606183423Smarius * the driver for PBM A has probed first and 607183423Smarius * registered it for us. 608183423Smarius */ 609183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 610183423Smarius schizo_pci_bus); 611183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 612183423Smarius osc != NULL) 613183423Smarius /* 614183423Smarius * We are the driver for PBM B but registered 615183423Smarius * the interrupt controller for PBM A, i.e. the 616183423Smarius * driver for PBM A attached first but couldn't 617183423Smarius * set up a handler for PBM A. 618183423Smarius */ 619183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 620183423Smarius schizo_pci_bus); 621183423Smarius } 622183423Smarius if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 623183423Smarius schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 624183423Smarius if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 625183423Smarius schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 626183423Smarius if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 627183423Smarius schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 628183423Smarius 629183423Smarius /* 630183423Smarius * Set the latency timer register as this isn't always done by the 631183423Smarius * firmware. 632183423Smarius */ 633183423Smarius PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, 634183423Smarius PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 635183423Smarius 636183423Smarius ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 637183423Smarius 638183423Smarius device_add_child(dev, "pci", -1); 639183423Smarius return (bus_generic_attach(dev)); 640183423Smarius} 641183423Smarius 642183423Smariusstatic void 643183423Smariusschizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 644183423Smarius driver_filter_t handler) 645183423Smarius{ 646183423Smarius u_long vec; 647183423Smarius int rid; 648183423Smarius 649183423Smarius rid = index; 650183423Smarius sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ, 651183423Smarius &rid, RF_ACTIVE); 652183423Smarius if (sc->sc_irq_res[index] == NULL || 653183423Smarius INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign || 654183423Smarius INTINO(vec) != ino || 655183423Smarius intr_vectors[vec].iv_ic != &schizo_ic || 656183423Smarius bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], INTR_TYPE_MISC, 657183423Smarius handler, NULL, sc, &sc->sc_ihand[index]) != 0) 658183423Smarius panic("%s: failed to set up interrupt %d", __func__, index); 659183423Smarius} 660183423Smarius 661183423Smariusstatic int 662183423Smariusschizo_get_intrmap(struct schizo_softc *sc, u_int ino, bus_addr_t *intrmapptr, 663183423Smarius bus_addr_t *intrclrptr) 664183423Smarius{ 665183423Smarius bus_addr_t intrclr, intrmap; 666183423Smarius uint64_t mr; 667183423Smarius 668183423Smarius /* 669183423Smarius * XXX we only look for INOs rather than INRs since the firmware 670183423Smarius * may not provide the IGN and the IGN is constant for all devices 671183423Smarius * on that PCI controller. 672183423Smarius */ 673183423Smarius 674183423Smarius if (ino > STX_MAX_INO) { 675183423Smarius device_printf(sc->sc_dev, "out of range INO %d requested\n", 676183423Smarius ino); 677183423Smarius return (0); 678183423Smarius } 679183423Smarius 680183423Smarius intrmap = STX_PCI_IMAP_BASE + (ino << 3); 681183423Smarius intrclr = STX_PCI_ICLR_BASE + (ino << 3); 682183423Smarius mr = SCHIZO_PCI_READ_8(sc, intrmap); 683183423Smarius if (INTINO(mr) != ino) { 684183423Smarius device_printf(sc->sc_dev, 685183423Smarius "interrupt map entry does not match INO (%d != %d)\n", 686183423Smarius (int)INTINO(mr), ino); 687183423Smarius return (0); 688183423Smarius } 689183423Smarius 690183423Smarius if (intrmapptr != NULL) 691183423Smarius *intrmapptr = intrmap; 692183423Smarius if (intrclrptr != NULL) 693183423Smarius *intrclrptr = intrclr; 694183423Smarius return (1); 695183423Smarius} 696183423Smarius 697183423Smarius/* 698183423Smarius * Interrupt handlers 699183423Smarius */ 700183423Smariusstatic int 701183423Smariusschizo_pci_bus(void *arg) 702183423Smarius{ 703183423Smarius struct schizo_softc *sc = arg; 704183423Smarius uint64_t afar, afsr, csr, iommu; 705183423Smarius uint32_t status; 706183423Smarius 707183423Smarius afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 708183423Smarius afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 709183423Smarius csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 710183423Smarius iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 711183423Smarius status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus, 712183423Smarius STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 713183423Smarius if ((csr & STX_PCI_CTRL_MMU_ERR) != 0) { 714183423Smarius if ((iommu & TOM_PCI_IOMMU_ERR) == 0) 715183423Smarius goto clear_error; 716183423Smarius 717183423Smarius /* These are non-fatal if target abort was signaled. */ 718183423Smarius if ((status & PCIM_STATUS_STABORT) != 0 && 719183423Smarius ((iommu & TOM_PCI_IOMMU_ERRMASK) == 720183423Smarius TOM_PCI_IOMMU_INVALID_ERR || 721183423Smarius (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) != 0 || 722183423Smarius (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) != 0)) { 723183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 724183423Smarius goto clear_error; 725183423Smarius } 726183423Smarius } 727183423Smarius 728183423Smarius panic("%s: PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 729183423Smarius "IOMMU %#llx STATUS %#llx", device_get_name(sc->sc_dev), 730183423Smarius 'A' + sc->sc_half, (unsigned long long)afar, 731183423Smarius (unsigned long long)afsr, (unsigned long long)csr, 732183423Smarius (unsigned long long)iommu, (unsigned long long)status); 733183423Smarius 734183423Smarius clear_error: 735183423Smarius if (bootverbose) 736183423Smarius device_printf(sc->sc_dev, 737183423Smarius "PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx " 738183423Smarius "STATUS %#llx", 'A' + sc->sc_half, 739183423Smarius (unsigned long long)afar, (unsigned long long)afsr, 740183423Smarius (unsigned long long)csr, (unsigned long long)status); 741183423Smarius /* Clear the error bits that we caught. */ 742183423Smarius PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE, 743183423Smarius STX_CS_FUNC, PCIR_STATUS, status, 2); 744183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 745183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 746183423Smarius return (FILTER_HANDLED); 747183423Smarius} 748183423Smarius 749183423Smariusstatic int 750183423Smariusschizo_ue(void *arg) 751183423Smarius{ 752183423Smarius struct schizo_softc *sc = arg; 753183423Smarius uint64_t afar, afsr; 754183423Smarius int i; 755183423Smarius 756183423Smarius mtx_lock_spin(sc->sc_mtx); 757183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 758183423Smarius for (i = 0; i < 1000; i++) 759183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 760183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 761183423Smarius break; 762183423Smarius mtx_unlock_spin(sc->sc_mtx); 763183423Smarius panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 764183423Smarius device_get_name(sc->sc_dev), (unsigned long long)afar, 765183423Smarius (unsigned long long)afsr); 766183423Smarius return (FILTER_HANDLED); 767183423Smarius} 768183423Smarius 769183423Smariusstatic int 770183423Smariusschizo_ce(void *arg) 771183423Smarius{ 772183423Smarius struct schizo_softc *sc = arg; 773183423Smarius uint64_t afar, afsr; 774183423Smarius int i; 775183423Smarius 776183423Smarius mtx_lock_spin(sc->sc_mtx); 777183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 778183423Smarius for (i = 0; i < 1000; i++) 779183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 780183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 781183423Smarius break; 782183423Smarius device_printf(sc->sc_dev, 783183423Smarius "correctable DMA error AFAR %#llx AFSR %#llx\n", 784183423Smarius (unsigned long long)afar, (unsigned long long)afsr); 785183423Smarius /* Clear the error bits that we caught. */ 786183423Smarius SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 787183423Smarius mtx_unlock_spin(sc->sc_mtx); 788183423Smarius return (FILTER_HANDLED); 789183423Smarius} 790183423Smarius 791183423Smariusstatic int 792183423Smariusschizo_host_bus(void *arg) 793183423Smarius{ 794183423Smarius struct schizo_softc *sc = arg; 795183423Smarius uint64_t errlog; 796183423Smarius 797183423Smarius errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 798183423Smarius panic("%s: %s error %#llx", device_get_name(sc->sc_dev), 799183423Smarius sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 800183423Smarius (unsigned long long)errlog); 801183423Smarius return (FILTER_HANDLED); 802183423Smarius} 803183423Smarius 804183423Smariusstatic void 805183423Smariusschizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 806183423Smarius{ 807183423Smarius 808183423Smarius /* Punch in our copies. */ 809183423Smarius sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 810183423Smarius sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 811183423Smarius sc->sc_is.is_iommu = STX_PCI_IOMMU; 812183423Smarius sc->sc_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 813183423Smarius sc->sc_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 814183423Smarius sc->sc_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 815183423Smarius sc->sc_is.is_dva = STX_PCI_IOMMU_SVADIAG; 816183423Smarius sc->sc_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 817183423Smarius 818183423Smarius iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, tsbsize, 819183423Smarius dvmabase, 0); 820183423Smarius} 821183423Smarius 822183423Smariusstatic int 823183423Smariusschizo_maxslots(device_t dev) 824183423Smarius{ 825183423Smarius struct schizo_softc *sc; 826183423Smarius 827183423Smarius sc = device_get_softc(dev); 828183423Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ) 829183423Smarius return (sc->sc_half == 0 ? 4 : 6); 830183423Smarius 831183423Smarius /* XXX: is this correct? */ 832183423Smarius return (PCI_SLOTMAX); 833183423Smarius} 834183423Smarius 835183423Smariusstatic uint32_t 836183423Smariusschizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 837183423Smarius int width) 838183423Smarius{ 839183423Smarius struct schizo_softc *sc; 840183423Smarius bus_space_handle_t bh; 841183423Smarius u_long offset = 0; 842183423Smarius uint32_t r, wrd; 843183423Smarius int i; 844183423Smarius uint16_t shrt; 845183423Smarius uint8_t byte; 846183423Smarius 847183423Smarius sc = device_get_softc(dev); 848183423Smarius 849183423Smarius /* 850183423Smarius * The Schizo bridges contain a dupe of their header at 0x80. 851183423Smarius */ 852183423Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus && 853183423Smarius slot == STX_CS_DEVICE && func == STX_CS_FUNC && 854183423Smarius reg + width > 0x80) 855183423Smarius return (0); 856183423Smarius 857183423Smarius offset = STX_CONF_OFF(bus, slot, func, reg); 858183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 859183423Smarius switch (width) { 860183423Smarius case 1: 861183423Smarius i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 862183423Smarius r = byte; 863183423Smarius break; 864183423Smarius case 2: 865183423Smarius i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 866183423Smarius r = shrt; 867183423Smarius break; 868183423Smarius case 4: 869183423Smarius i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 870183423Smarius r = wrd; 871183423Smarius break; 872183423Smarius default: 873183423Smarius panic("%s: bad width", __func__); 874183423Smarius /* NOTREACHED */ 875183423Smarius } 876183423Smarius 877183423Smarius if (i) { 878183423Smarius#ifdef SCHIZO_DEBUG 879183423Smarius printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 880183423Smarius __func__, bus, slot, func, reg); 881183423Smarius#endif 882183423Smarius r = -1; 883183423Smarius } 884183423Smarius return (r); 885183423Smarius} 886183423Smarius 887183423Smariusstatic void 888183423Smariusschizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 889183423Smarius uint32_t val, int width) 890183423Smarius{ 891183423Smarius struct schizo_softc *sc; 892183423Smarius bus_space_handle_t bh; 893183423Smarius u_long offset = 0; 894183423Smarius 895183423Smarius sc = device_get_softc(dev); 896183423Smarius offset = STX_CONF_OFF(bus, slot, func, reg); 897183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 898183423Smarius switch (width) { 899183423Smarius case 1: 900183423Smarius bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 901183423Smarius break; 902183423Smarius case 2: 903183423Smarius bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 904183423Smarius break; 905183423Smarius case 4: 906183423Smarius bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 907183423Smarius break; 908183423Smarius default: 909183423Smarius panic("%s: bad width", __func__); 910183423Smarius /* NOTREACHED */ 911183423Smarius } 912183423Smarius} 913183423Smarius 914183423Smariusstatic int 915183423Smariusschizo_route_interrupt(device_t bridge, device_t dev, int pin) 916183423Smarius{ 917183423Smarius struct schizo_softc *sc; 918183423Smarius struct ofw_pci_register reg; 919183423Smarius ofw_pci_intr_t pintr, mintr; 920183423Smarius uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 921183423Smarius 922183423Smarius sc = device_get_softc(bridge); 923183423Smarius pintr = pin; 924183423Smarius if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 925183423Smarius sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 926183423Smarius return (mintr); 927183423Smarius 928183423Smarius device_printf(bridge, "could not route pin %d for device %d.%d\n", 929183423Smarius pin, pci_get_slot(dev), pci_get_function(dev)); 930183423Smarius return (PCI_INVALID_IRQ); 931183423Smarius} 932183423Smarius 933183423Smariusstatic int 934183423Smariusschizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 935183423Smarius{ 936183423Smarius struct schizo_softc *sc; 937183423Smarius 938183423Smarius sc = device_get_softc(dev); 939183423Smarius switch (which) { 940183423Smarius case PCIB_IVAR_DOMAIN: 941183423Smarius *result = device_get_unit(dev); 942183423Smarius return (0); 943183423Smarius case PCIB_IVAR_BUS: 944183423Smarius *result = sc->sc_pci_secbus; 945183423Smarius return (0); 946183423Smarius } 947183423Smarius return (ENOENT); 948183423Smarius} 949183423Smarius 950183423Smarius#define VIS_BLOCKSIZE 64 951183423Smarius 952183423Smariusstatic int 953183423Smariusschizo_dmasync(void *arg) 954183423Smarius{ 955183423Smarius static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE); 956183423Smarius struct schizo_dmasync *sds = arg; 957183423Smarius struct schizo_softc *sc = sds->sds_sc; 958183423Smarius uint64_t reg; 959183423Smarius int timeout; 960183423Smarius 961183423Smarius SCHIZO_PCI_WRITE_8(sc, sds->sds_syncreg, sds->sds_syncval); 962183423Smarius timeout = 1000000; 963183423Smarius for (; (SCHIZO_PCI_READ_8(sc, sds->sds_syncreg) & 964183423Smarius sds->sds_syncval) != 0;) 965183423Smarius if (--timeout < 0) 966183423Smarius panic("%s: DMA does not sync", __func__); 967183423Smarius 968183423Smarius if (sds->sds_bswar != 0) { 969183423Smarius critical_enter(); 970183423Smarius reg = rd(fprs); 971183423Smarius wr(fprs, reg | FPRS_FEF, 0); 972183423Smarius __asm__ __volatile__("stda %%f0, [%0] %1" 973183423Smarius : : "r" (buf), "n" (ASI_BLK_COMMIT_S)); 974183423Smarius wr(fprs, reg, 0); 975183423Smarius membar(Sync); 976183423Smarius critical_exit(); 977183423Smarius } 978183423Smarius return (sds->sds_handler(sds->sds_arg)); 979183423Smarius} 980183423Smarius 981183423Smariusstatic void 982183423Smariusschizo_intr_enable(void *arg) 983183423Smarius{ 984183423Smarius struct intr_vector *iv = arg; 985183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 986183423Smarius 987183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 988183423Smarius INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 989183423Smarius} 990183423Smarius 991183423Smariusstatic void 992183423Smariusschizo_intr_disable(void *arg) 993183423Smarius{ 994183423Smarius struct intr_vector *iv = arg; 995183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 996183423Smarius 997183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 998183423Smarius} 999183423Smarius 1000183423Smariusstatic void 1001183423Smariusschizo_intr_assign(void *arg) 1002183423Smarius{ 1003183423Smarius struct intr_vector *iv = arg; 1004183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1005183423Smarius 1006183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1007183423Smarius SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1008183423Smarius} 1009183423Smarius 1010183423Smariusstatic void 1011183423Smariusschizo_intr_clear(void *arg) 1012183423Smarius{ 1013183423Smarius struct intr_vector *iv = arg; 1014183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1015183423Smarius 1016183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, 0); 1017183423Smarius} 1018183423Smarius 1019183423Smariusstatic int 1020183423Smariusschizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1021183423Smarius int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1022183423Smarius void **cookiep) 1023183423Smarius{ 1024183423Smarius struct schizo_dmasync *sds; 1025183423Smarius struct schizo_softc *sc; 1026183423Smarius u_long vec; 1027183423Smarius int error; 1028183423Smarius 1029183423Smarius sc = device_get_softc(dev); 1030183423Smarius /* 1031183423Smarius * Make sure the vector is fully specified and we registered 1032183423Smarius * our interrupt controller for it. 1033183423Smarius */ 1034183423Smarius vec = rman_get_start(ires); 1035183423Smarius if (INTIGN(vec) != sc->sc_ign || 1036183423Smarius intr_vectors[vec].iv_ic != &schizo_ic) { 1037183423Smarius device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1038183423Smarius return (EINVAL); 1039183423Smarius } 1040183423Smarius 1041183423Smarius /* 1042183423Smarius * Schizo revision >= 2.3 (i.e. version >= 5) and Tomatillo bridges 1043183423Smarius * need to be manually told to sync DMA writes. 1044183423Smarius * Tomatillo revision <= 2.3 (i.e. version <= 4) bridges additionally 1045183423Smarius * need a block store as a workaround for a hardware bug. 1046183423Smarius * XXX setup of the wrapper and the contents of schizo_dmasync() 1047183423Smarius * should be moved to schizo(4)-specific bus_dma_tag_create() and 1048183423Smarius * bus_dmamap_sync() methods, respectively, once DMA tag creation 1049183423Smarius * is newbus'ified, so the wrapper isn't only applied for interrupt 1050183423Smarius * handlers but also for polling(4) callbacks. 1051183423Smarius */ 1052183423Smarius if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 1053183423Smarius sc->sc_mode == SCHIZO_MODE_TOM) { 1054183423Smarius sds = malloc(sizeof(*sds), M_DEVBUF, M_NOWAIT | M_ZERO); 1055183423Smarius if (sds == NULL) 1056183423Smarius return (ENOMEM); 1057183423Smarius sds->sds_sc = sc; 1058183423Smarius sds->sds_arg = arg; 1059183423Smarius sds->sds_syncreg = sc->sc_mode == SCHIZO_MODE_SCZ ? 1060183423Smarius SCZ_PCI_DMA_SYNC : TOMXMS_PCI_DMA_SYNC_PEND; 1061183423Smarius sds->sds_syncval = 1ULL << INTINO(vec); 1062183423Smarius if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 1063183423Smarius sds->sds_bswar = 1; 1064183423Smarius if (intr == NULL) { 1065183423Smarius sds->sds_handler = filt; 1066183423Smarius error = bus_generic_setup_intr(dev, child, ires, 1067183423Smarius flags, schizo_dmasync, intr, sds, cookiep); 1068183423Smarius } else { 1069183423Smarius sds->sds_handler = (driver_filter_t *)intr; 1070183423Smarius error = bus_generic_setup_intr(dev, child, ires, 1071183423Smarius flags, filt, (driver_intr_t *)schizo_dmasync, 1072183423Smarius sds, cookiep); 1073183423Smarius } 1074183423Smarius if (error != 0) { 1075183423Smarius free(sds, M_DEVBUF); 1076183423Smarius return (error); 1077183423Smarius } 1078183423Smarius sds->sds_cookie = *cookiep; 1079183423Smarius *cookiep = sds; 1080183423Smarius return (error); 1081183423Smarius } 1082183423Smarius return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1083183423Smarius arg, cookiep)); 1084183423Smarius} 1085183423Smarius 1086183423Smariusstatic int 1087183423Smariusschizo_teardown_intr(device_t dev, device_t child, struct resource *vec, 1088183423Smarius void *cookie) 1089183423Smarius{ 1090183423Smarius struct schizo_dmasync *sds; 1091183423Smarius struct schizo_softc *sc; 1092183423Smarius int error; 1093183423Smarius 1094183423Smarius sc = device_get_softc(dev); 1095183423Smarius if (sc->sc_mode == SCHIZO_MODE_TOM) { 1096183423Smarius sds = cookie; 1097183423Smarius error = bus_generic_teardown_intr(dev, child, vec, 1098183423Smarius sds->sds_cookie); 1099183423Smarius if (error == 0) 1100183423Smarius free(sds, M_DEVBUF); 1101183423Smarius return (error); 1102183423Smarius } 1103183423Smarius return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1104183423Smarius} 1105183423Smarius 1106183423Smariusstatic struct resource * 1107183423Smariusschizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1108183423Smarius u_long start, u_long end, u_long count, u_int flags) 1109183423Smarius{ 1110183423Smarius struct schizo_softc *sc; 1111183423Smarius struct resource *rv; 1112183423Smarius struct rman *rm; 1113183423Smarius bus_space_tag_t bt; 1114183423Smarius bus_space_handle_t bh; 1115183423Smarius int needactivate = flags & RF_ACTIVE; 1116183423Smarius 1117183423Smarius flags &= ~RF_ACTIVE; 1118183423Smarius 1119183423Smarius sc = device_get_softc(bus); 1120183423Smarius if (type == SYS_RES_IRQ) { 1121183423Smarius /* 1122183423Smarius * XXX: Don't accept blank ranges for now, only single 1123183423Smarius * interrupts. The other case should not happen with 1124183423Smarius * the MI PCI code... 1125183423Smarius * XXX: This may return a resource that is out of the 1126183423Smarius * range that was specified. Is this correct...? 1127183423Smarius */ 1128183423Smarius if (start != end) 1129183423Smarius panic("%s: XXX: interrupt range", __func__); 1130183423Smarius start = end = INTMAP_VEC(sc->sc_ign, end); 1131183423Smarius return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1132183423Smarius rid, start, end, count, flags)); 1133183423Smarius } 1134183423Smarius switch (type) { 1135183423Smarius case SYS_RES_MEMORY: 1136183423Smarius rm = &sc->sc_pci_mem_rman; 1137183423Smarius bt = sc->sc_pci_memt; 1138183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1139183423Smarius break; 1140183423Smarius case SYS_RES_IOPORT: 1141183423Smarius rm = &sc->sc_pci_io_rman; 1142183423Smarius bt = sc->sc_pci_iot; 1143183423Smarius bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1144183423Smarius break; 1145183423Smarius default: 1146183423Smarius return (NULL); 1147183423Smarius /* NOTREACHED */ 1148183423Smarius } 1149183423Smarius 1150183423Smarius rv = rman_reserve_resource(rm, start, end, count, flags, child); 1151183423Smarius if (rv == NULL) 1152183423Smarius return (NULL); 1153183423Smarius rman_set_rid(rv, *rid); 1154183423Smarius bh += rman_get_start(rv); 1155183423Smarius rman_set_bustag(rv, bt); 1156183423Smarius rman_set_bushandle(rv, bh); 1157183423Smarius 1158183423Smarius if (needactivate) { 1159183423Smarius if (bus_activate_resource(child, type, *rid, rv)) { 1160183423Smarius rman_release_resource(rv); 1161183423Smarius return (NULL); 1162183423Smarius } 1163183423Smarius } 1164183423Smarius return (rv); 1165183423Smarius} 1166183423Smarius 1167183423Smariusstatic int 1168183423Smariusschizo_activate_resource(device_t bus, device_t child, int type, int rid, 1169183423Smarius struct resource *r) 1170183423Smarius{ 1171183423Smarius void *p; 1172183423Smarius int error; 1173183423Smarius 1174183423Smarius if (type == SYS_RES_IRQ) 1175183423Smarius return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1176183423Smarius type, rid, r)); 1177183423Smarius if (type == SYS_RES_MEMORY) { 1178183423Smarius /* 1179183423Smarius * Need to memory-map the device space, as some drivers depend 1180183423Smarius * on the virtual address being set and useable. 1181183423Smarius */ 1182183423Smarius error = sparc64_bus_mem_map(rman_get_bustag(r), 1183183423Smarius rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1184183423Smarius if (error != 0) 1185183423Smarius return (error); 1186183423Smarius rman_set_virtual(r, p); 1187183423Smarius } 1188183423Smarius return (rman_activate_resource(r)); 1189183423Smarius} 1190183423Smarius 1191183423Smariusstatic int 1192183423Smariusschizo_deactivate_resource(device_t bus, device_t child, int type, int rid, 1193183423Smarius struct resource *r) 1194183423Smarius{ 1195183423Smarius 1196183423Smarius if (type == SYS_RES_IRQ) 1197183423Smarius return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1198183423Smarius type, rid, r)); 1199183423Smarius if (type == SYS_RES_MEMORY) { 1200183423Smarius sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1201183423Smarius rman_set_virtual(r, NULL); 1202183423Smarius } 1203183423Smarius return (rman_deactivate_resource(r)); 1204183423Smarius} 1205183423Smarius 1206183423Smariusstatic int 1207183423Smariusschizo_release_resource(device_t bus, device_t child, int type, int rid, 1208183423Smarius struct resource *r) 1209183423Smarius{ 1210183423Smarius int error; 1211183423Smarius 1212183423Smarius if (type == SYS_RES_IRQ) 1213183423Smarius return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1214183423Smarius type, rid, r)); 1215183423Smarius if (rman_get_flags(r) & RF_ACTIVE) { 1216183423Smarius error = bus_deactivate_resource(child, type, rid, r); 1217183423Smarius if (error) 1218183423Smarius return (error); 1219183423Smarius } 1220183423Smarius return (rman_release_resource(r)); 1221183423Smarius} 1222183423Smarius 1223183423Smariusstatic bus_dma_tag_t 1224183423Smariusschizo_get_dma_tag(device_t bus, device_t child) 1225183423Smarius{ 1226183423Smarius struct schizo_softc *sc; 1227183423Smarius 1228183423Smarius sc = device_get_softc(bus); 1229183423Smarius return (sc->sc_pci_dmat); 1230183423Smarius} 1231183423Smarius 1232183423Smariusstatic phandle_t 1233183423Smariusschizo_get_node(device_t bus, device_t dev) 1234183423Smarius{ 1235183423Smarius struct schizo_softc *sc; 1236183423Smarius 1237183423Smarius sc = device_get_softc(bus); 1238183423Smarius /* We only have one child, the PCI bus, which needs our own node. */ 1239183423Smarius return (sc->sc_node); 1240183423Smarius} 1241183423Smarius 1242183423Smariusstatic bus_space_tag_t 1243183423Smariusschizo_alloc_bus_tag(struct schizo_softc *sc, int type) 1244183423Smarius{ 1245183423Smarius bus_space_tag_t bt; 1246183423Smarius 1247183423Smarius bt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 1248183423Smarius M_NOWAIT | M_ZERO); 1249183423Smarius if (bt == NULL) 1250183423Smarius panic("%s: out of memory", __func__); 1251183423Smarius 1252183423Smarius bt->bst_cookie = sc; 1253183423Smarius bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 1254183423Smarius bt->bst_type = type; 1255183423Smarius return (bt); 1256183423Smarius} 1257183423Smarius 1258183423Smariusstatic u_int 1259183423Smariusschizo_get_timecount(struct timecounter *tc) 1260183423Smarius{ 1261183423Smarius struct schizo_softc *sc; 1262183423Smarius 1263183423Smarius sc = tc->tc_priv; 1264183423Smarius return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1265183423Smarius (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)); 1266183423Smarius} 1267