1183423Smarius/*- 2183423Smarius * Copyright (c) 1999, 2000 Matthew R. Green 3183423Smarius * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4220038Smarius * Copyright (c) 2005 - 2011 by Marius Strobl <marius@FreeBSD.org> 5183423Smarius * All rights reserved. 6183423Smarius * 7183423Smarius * Redistribution and use in source and binary forms, with or without 8183423Smarius * modification, are permitted provided that the following conditions 9183423Smarius * are met: 10183423Smarius * 1. Redistributions of source code must retain the above copyright 11183423Smarius * notice, this list of conditions and the following disclaimer. 12183423Smarius * 2. Redistributions in binary form must reproduce the above copyright 13183423Smarius * notice, this list of conditions and the following disclaimer in the 14183423Smarius * documentation and/or other materials provided with the distribution. 15183423Smarius * 3. The name of the author may not be used to endorse or promote products 16183423Smarius * derived from this software without specific prior written permission. 17183423Smarius * 18183423Smarius * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19183423Smarius * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20183423Smarius * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21183423Smarius * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22183423Smarius * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23183423Smarius * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24183423Smarius * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25183423Smarius * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26183423Smarius * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27183423Smarius * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28183423Smarius * SUCH DAMAGE. 29183423Smarius * 30183423Smarius * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31183423Smarius * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32183423Smarius */ 33183423Smarius 34183423Smarius#include <sys/cdefs.h> 35183423Smarius__FBSDID("$FreeBSD: releng/10.3/sys/sparc64/pci/schizo.c 292789 2015-12-27 19:37:47Z marius $"); 36183423Smarius 37183423Smarius/* 38220038Smarius * Driver for `Schizo' Fireplane/Safari to PCI 2.1, `Tomatillo' JBus to 39220038Smarius * PCI 2.2 and `XMITS' Fireplane/Safari to PCI-X bridges 40183423Smarius */ 41183423Smarius 42183423Smarius#include "opt_ofw_pci.h" 43183423Smarius#include "opt_schizo.h" 44183423Smarius 45183423Smarius#include <sys/param.h> 46183423Smarius#include <sys/systm.h> 47183423Smarius#include <sys/bus.h> 48183423Smarius#include <sys/kernel.h> 49183423Smarius#include <sys/lock.h> 50183423Smarius#include <sys/malloc.h> 51183423Smarius#include <sys/module.h> 52183423Smarius#include <sys/mutex.h> 53183423Smarius#include <sys/pcpu.h> 54183423Smarius#include <sys/rman.h> 55208097Smarius#include <sys/sysctl.h> 56185133Smarius#include <sys/time.h> 57183423Smarius#include <sys/timetc.h> 58183423Smarius 59183423Smarius#include <dev/ofw/ofw_bus.h> 60183423Smarius#include <dev/ofw/openfirm.h> 61183423Smarius 62183423Smarius#include <machine/bus.h> 63183423Smarius#include <machine/bus_common.h> 64183423Smarius#include <machine/bus_private.h> 65183423Smarius#include <machine/iommureg.h> 66183423Smarius#include <machine/iommuvar.h> 67183423Smarius#include <machine/resource.h> 68183423Smarius 69183423Smarius#include <dev/pci/pcireg.h> 70183423Smarius#include <dev/pci/pcivar.h> 71183423Smarius 72183423Smarius#include <sparc64/pci/ofw_pci.h> 73183423Smarius#include <sparc64/pci/schizoreg.h> 74183423Smarius#include <sparc64/pci/schizovar.h> 75183423Smarius 76183423Smarius#include "pcib_if.h" 77183423Smarius 78183423Smariusstatic const struct schizo_desc *schizo_get_desc(device_t); 79183423Smariusstatic void schizo_set_intr(struct schizo_softc *, u_int, u_int, 80183423Smarius driver_filter_t); 81220038Smariusstatic void schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 82220038Smarius bus_dmasync_op_t op); 83220038Smariusstatic void ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 84220038Smarius bus_dmasync_op_t op); 85183423Smariusstatic void schizo_intr_enable(void *); 86183423Smariusstatic void schizo_intr_disable(void *); 87183423Smariusstatic void schizo_intr_assign(void *); 88183423Smariusstatic void schizo_intr_clear(void *); 89185133Smariusstatic int schizo_intr_register(struct schizo_softc *sc, u_int ino); 90183423Smariusstatic int schizo_get_intrmap(struct schizo_softc *, u_int, 91183423Smarius bus_addr_t *, bus_addr_t *); 92183423Smariusstatic timecounter_get_t schizo_get_timecount; 93183423Smarius 94183423Smarius/* Interrupt handlers */ 95183423Smariusstatic driver_filter_t schizo_pci_bus; 96183423Smariusstatic driver_filter_t schizo_ue; 97183423Smariusstatic driver_filter_t schizo_ce; 98183423Smariusstatic driver_filter_t schizo_host_bus; 99185133Smariusstatic driver_filter_t schizo_cdma; 100183423Smarius 101183423Smarius/* IOMMU support */ 102183423Smariusstatic void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 103183423Smarius 104183423Smarius/* 105183423Smarius * Methods 106183423Smarius */ 107183423Smariusstatic device_probe_t schizo_probe; 108183423Smariusstatic device_attach_t schizo_attach; 109183423Smariusstatic bus_setup_intr_t schizo_setup_intr; 110183423Smariusstatic bus_alloc_resource_t schizo_alloc_resource; 111183423Smariusstatic pcib_maxslots_t schizo_maxslots; 112183423Smariusstatic pcib_read_config_t schizo_read_config; 113183423Smariusstatic pcib_write_config_t schizo_write_config; 114183423Smariusstatic pcib_route_interrupt_t schizo_route_interrupt; 115220038Smariusstatic ofw_pci_setup_device_t schizo_setup_device; 116183423Smarius 117183423Smariusstatic device_method_t schizo_methods[] = { 118183423Smarius /* Device interface */ 119183423Smarius DEVMETHOD(device_probe, schizo_probe), 120183423Smarius DEVMETHOD(device_attach, schizo_attach), 121183423Smarius DEVMETHOD(device_shutdown, bus_generic_shutdown), 122183423Smarius DEVMETHOD(device_suspend, bus_generic_suspend), 123183423Smarius DEVMETHOD(device_resume, bus_generic_resume), 124183423Smarius 125183423Smarius /* Bus interface */ 126292789Smarius DEVMETHOD(bus_read_ivar, ofw_pci_read_ivar), 127183423Smarius DEVMETHOD(bus_setup_intr, schizo_setup_intr), 128220038Smarius DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 129183423Smarius DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 130292789Smarius DEVMETHOD(bus_activate_resource, ofw_pci_activate_resource), 131225931Smarius DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 132292789Smarius DEVMETHOD(bus_adjust_resource, ofw_pci_adjust_resource), 133225931Smarius DEVMETHOD(bus_release_resource, bus_generic_release_resource), 134292789Smarius DEVMETHOD(bus_get_dma_tag, ofw_pci_get_dma_tag), 135183423Smarius 136183423Smarius /* pcib interface */ 137183423Smarius DEVMETHOD(pcib_maxslots, schizo_maxslots), 138183423Smarius DEVMETHOD(pcib_read_config, schizo_read_config), 139183423Smarius DEVMETHOD(pcib_write_config, schizo_write_config), 140183423Smarius DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 141183423Smarius 142183423Smarius /* ofw_bus interface */ 143292789Smarius DEVMETHOD(ofw_bus_get_node, ofw_pci_get_node), 144183423Smarius 145225931Smarius /* ofw_pci interface */ 146220038Smarius DEVMETHOD(ofw_pci_setup_device, schizo_setup_device), 147220038Smarius 148227843Smarius DEVMETHOD_END 149183423Smarius}; 150183423Smarius 151183423Smariusstatic devclass_t schizo_devclass; 152183423Smarius 153183423SmariusDEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 154183423Smarius sizeof(struct schizo_softc)); 155215349SmariusEARLY_DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0, 156215349Smarius BUS_PASS_BUS); 157183423Smarius 158183423Smariusstatic SLIST_HEAD(, schizo_softc) schizo_softcs = 159183423Smarius SLIST_HEAD_INITIALIZER(schizo_softcs); 160183423Smarius 161183423Smariusstatic const struct intr_controller schizo_ic = { 162183423Smarius schizo_intr_enable, 163183423Smarius schizo_intr_disable, 164183423Smarius schizo_intr_assign, 165183423Smarius schizo_intr_clear 166183423Smarius}; 167183423Smarius 168183423Smariusstruct schizo_icarg { 169183423Smarius struct schizo_softc *sica_sc; 170183423Smarius bus_addr_t sica_map; 171183423Smarius bus_addr_t sica_clr; 172183423Smarius}; 173183423Smarius 174230664Smarius#define SCHIZO_CDMA_TIMEOUT 1 /* 1 second per try */ 175230664Smarius#define SCHIZO_CDMA_TRIES 15 176183423Smarius#define SCHIZO_PERF_CNT_QLTY 100 177183423Smarius 178220038Smarius#define SCHIZO_SPC_BARRIER(spc, sc, offs, len, flags) \ 179220038Smarius bus_barrier((sc)->sc_mem_res[(spc)], (offs), (len), (flags)) 180206018Smarius#define SCHIZO_SPC_READ_8(spc, sc, offs) \ 181183423Smarius bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 182206018Smarius#define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 183183423Smarius bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 184183423Smarius 185220038Smarius#ifndef SCHIZO_DEBUG 186220038Smarius#define SCHIZO_SPC_SET(spc, sc, offs, reg, v) \ 187220038Smarius SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)) 188220038Smarius#else 189220038Smarius#define SCHIZO_SPC_SET(spc, sc, offs, reg, v) do { \ 190220038Smarius device_printf((sc)->sc_dev, reg " 0x%016llx -> 0x%016llx\n", \ 191220038Smarius (unsigned long long)SCHIZO_SPC_READ_8((spc), (sc), (offs)), \ 192220038Smarius (unsigned long long)(v)); \ 193220038Smarius SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)); \ 194220038Smarius } while (0) 195220038Smarius#endif 196220038Smarius 197206018Smarius#define SCHIZO_PCI_READ_8(sc, offs) \ 198183423Smarius SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 199206018Smarius#define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 200183423Smarius SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 201206018Smarius#define SCHIZO_CTRL_READ_8(sc, offs) \ 202183423Smarius SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 203206018Smarius#define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 204183423Smarius SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 205206018Smarius#define SCHIZO_PCICFG_READ_8(sc, offs) \ 206183423Smarius SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 207206018Smarius#define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 208183423Smarius SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 209206018Smarius#define SCHIZO_ICON_READ_8(sc, offs) \ 210183423Smarius SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 211206018Smarius#define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 212183423Smarius SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 213183423Smarius 214220038Smarius#define SCHIZO_PCI_SET(sc, offs, v) \ 215220038Smarius SCHIZO_SPC_SET(STX_PCI, (sc), (offs), # offs, (v)) 216220038Smarius#define SCHIZO_CTRL_SET(sc, offs, v) \ 217220038Smarius SCHIZO_SPC_SET(STX_CTRL, (sc), (offs), # offs, (v)) 218220038Smarius 219183423Smariusstruct schizo_desc { 220183423Smarius const char *sd_string; 221183423Smarius int sd_mode; 222183423Smarius const char *sd_name; 223183423Smarius}; 224183423Smarius 225242625Sdimstatic const struct schizo_desc schizo_compats[] = { 226183423Smarius { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 227220038Smarius#if 0 228220038Smarius { "pci108e,8002", SCHIZO_MODE_XMS, "XMITS" }, 229220038Smarius#endif 230183423Smarius { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 231183423Smarius { NULL, 0, NULL } 232183423Smarius}; 233183423Smarius 234183423Smariusstatic const struct schizo_desc * 235183423Smariusschizo_get_desc(device_t dev) 236183423Smarius{ 237183423Smarius const struct schizo_desc *desc; 238183423Smarius const char *compat; 239183423Smarius 240183423Smarius compat = ofw_bus_get_compat(dev); 241183423Smarius if (compat == NULL) 242183423Smarius return (NULL); 243183423Smarius for (desc = schizo_compats; desc->sd_string != NULL; desc++) 244183423Smarius if (strcmp(desc->sd_string, compat) == 0) 245183423Smarius return (desc); 246183423Smarius return (NULL); 247183423Smarius} 248183423Smarius 249183423Smariusstatic int 250183423Smariusschizo_probe(device_t dev) 251183423Smarius{ 252183423Smarius const char *dtype; 253183423Smarius 254183423Smarius dtype = ofw_bus_get_type(dev); 255197164Smarius if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 256183423Smarius schizo_get_desc(dev) != NULL) { 257183423Smarius device_set_desc(dev, "Sun Host-PCI bridge"); 258183423Smarius return (0); 259183423Smarius } 260183423Smarius return (ENXIO); 261183423Smarius} 262183423Smarius 263183423Smariusstatic int 264183423Smariusschizo_attach(device_t dev) 265183423Smarius{ 266183423Smarius const struct schizo_desc *desc; 267183423Smarius struct schizo_softc *asc, *sc, *osc; 268183423Smarius struct timecounter *tc; 269292789Smarius bus_dma_tag_t dmat; 270183423Smarius uint64_t ino_bitmap, reg; 271183423Smarius phandle_t node; 272183423Smarius uint32_t prop, prop_array[2]; 273201199Smarius int i, j, mode, rid, tsbsize; 274183423Smarius 275183423Smarius sc = device_get_softc(dev); 276183423Smarius node = ofw_bus_get_node(dev); 277183423Smarius desc = schizo_get_desc(dev); 278183423Smarius mode = desc->sd_mode; 279183423Smarius 280183423Smarius sc->sc_dev = dev; 281183423Smarius sc->sc_mode = mode; 282185133Smarius sc->sc_flags = 0; 283183423Smarius 284183423Smarius /* 285183423Smarius * The Schizo has three register banks: 286183423Smarius * (0) per-PBM PCI configuration and status registers, but for bus B 287183423Smarius * shared with the UPA64s interrupt mapping register banks 288183423Smarius * (1) shared Schizo controller configuration and status registers 289183423Smarius * (2) per-PBM PCI configuration space 290183423Smarius * 291183423Smarius * The Tomatillo has four register banks: 292183423Smarius * (0) per-PBM PCI configuration and status registers 293183423Smarius * (1) per-PBM Tomatillo controller configuration registers, but on 294183423Smarius * machines having the `jbusppm' device shared with its Estar 295183423Smarius * register bank for bus A 296183423Smarius * (2) per-PBM PCI configuration space 297183423Smarius * (3) per-PBM interrupt concentrator registers 298183423Smarius */ 299183423Smarius sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 300183423Smarius 20) & 1; 301201199Smarius for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 302201199Smarius i++) { 303201199Smarius rid = i; 304201199Smarius sc->sc_mem_res[i] = bus_alloc_resource_any(dev, 305183423Smarius SYS_RES_MEMORY, &rid, 306183423Smarius (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 307201199Smarius i == STX_PCI) || i == STX_CTRL)) || 308183423Smarius (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 309201199Smarius i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 310201199Smarius if (sc->sc_mem_res[i] == NULL) 311183423Smarius panic("%s: could not allocate register bank %d", 312201199Smarius __func__, i); 313183423Smarius } 314183423Smarius 315183423Smarius /* 316183423Smarius * Match other Schizos that are already configured against 317183423Smarius * the controller base physical address. This will be the 318183423Smarius * same for a pair of devices that share register space. 319183423Smarius */ 320183423Smarius osc = NULL; 321183423Smarius SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 322183423Smarius if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 323183423Smarius rman_get_start(sc->sc_mem_res[STX_CTRL])) { 324183423Smarius /* Found partner. */ 325183423Smarius osc = asc; 326183423Smarius break; 327183423Smarius } 328183423Smarius } 329183423Smarius if (osc == NULL) { 330183423Smarius sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 331183423Smarius M_NOWAIT | M_ZERO); 332183423Smarius if (sc->sc_mtx == NULL) 333183423Smarius panic("%s: could not malloc mutex", __func__); 334183423Smarius mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 335183423Smarius } else { 336185133Smarius if (sc->sc_mode != SCHIZO_MODE_SCZ) 337185133Smarius panic("%s: no partner expected", __func__); 338183423Smarius if (mtx_initialized(osc->sc_mtx) == 0) 339183423Smarius panic("%s: mutex not initialized", __func__); 340183423Smarius sc->sc_mtx = osc->sc_mtx; 341183423Smarius } 342292789Smarius SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 343183423Smarius 344183423Smarius if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 345183423Smarius panic("%s: could not determine IGN", __func__); 346201199Smarius if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == 347201199Smarius -1) 348183423Smarius panic("%s: could not determine version", __func__); 349220038Smarius if (mode == SCHIZO_MODE_XMS && OF_getprop(node, "module-revision#", 350220038Smarius &sc->sc_mrev, sizeof(sc->sc_mrev)) == -1) 351220038Smarius panic("%s: could not determine module-revision", __func__); 352183423Smarius if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 353183423Smarius prop = 33000000; 354183423Smarius 355220038Smarius if (mode == SCHIZO_MODE_XMS && (SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL) & 356220038Smarius XMS_PCI_CTRL_X_MODE) != 0) { 357220038Smarius if (sc->sc_mrev < 1) 358220038Smarius panic("PCI-X mode unsupported"); 359220038Smarius sc->sc_flags |= SCHIZO_FLAGS_XMODE; 360220038Smarius } 361183423Smarius 362220038Smarius device_printf(dev, "%s, version %d, ", desc->sd_name, sc->sc_ver); 363220038Smarius if (mode == SCHIZO_MODE_XMS) 364220038Smarius printf("module-revision %d, ", sc->sc_mrev); 365220038Smarius printf("IGN %#x, bus %c, PCI%s mode, %dMHz\n", sc->sc_ign, 366220038Smarius 'A' + sc->sc_half, (sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 367220038Smarius "-X" : "", prop / 1000 / 1000); 368220038Smarius 369183423Smarius /* Set up the PCI interrupt retry timer. */ 370220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_INTR_RETRY_TIM, 5); 371183423Smarius 372183423Smarius /* Set up the PCI control register. */ 373183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 374220038Smarius reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK | 375220038Smarius STX_PCI_CTRL_ARB_MASK); 376183423Smarius reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 377220038Smarius STX_PCI_CTRL_ERR_IEN; 378183423Smarius if (OF_getproplen(node, "no-bus-parking") < 0) 379183423Smarius reg |= STX_PCI_CTRL_ARB_PARK; 380220038Smarius if (mode == SCHIZO_MODE_XMS && sc->sc_mrev == 1) 381220038Smarius reg |= XMS_PCI_CTRL_XMITS10_ARB_MASK; 382220038Smarius else 383220038Smarius reg |= STX_PCI_CTRL_ARB_MASK; 384183423Smarius if (mode == SCHIZO_MODE_TOM) { 385183423Smarius reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 386183423Smarius if (sc->sc_ver <= 1) /* revision <= 2.0 */ 387183423Smarius reg |= TOM_PCI_CTRL_DTO_IEN; 388183423Smarius else 389183423Smarius reg |= STX_PCI_CTRL_PTO; 390220038Smarius } else if (mode == SCHIZO_MODE_XMS) { 391220038Smarius SCHIZO_PCI_SET(sc, XMS_PCI_PARITY_DETECT, 0x3fff); 392220038Smarius SCHIZO_PCI_SET(sc, XMS_PCI_UPPER_RETRY_COUNTER, 0x3e8); 393220038Smarius reg |= XMS_PCI_CTRL_X_ERRINT_EN; 394183423Smarius } 395220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_CTRL, reg); 396183423Smarius 397183423Smarius /* Set up the PCI diagnostic register. */ 398183423Smarius reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 399183423Smarius reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 400183423Smarius STX_PCI_DIAG_INTRSYNC_DIS); 401220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_DIAG, reg); 402183423Smarius 403183423Smarius /* 404208097Smarius * Enable DMA write parity error interrupts of version >= 7 (i.e. 405220038Smarius * revision >= 2.5) Schizo and XMITS (enabling it on XMITS < 3.0 has 406220038Smarius * no effect though). 407208097Smarius */ 408220038Smarius if ((mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 7) || 409220038Smarius mode == SCHIZO_MODE_XMS) { 410208097Smarius reg = SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD); 411208097Smarius reg |= SX_PCI_CFG_ICD_DMAW_PERR_IEN; 412220038Smarius SCHIZO_PCI_SET(sc, SX_PCI_CFG_ICD, reg); 413208097Smarius } 414208097Smarius 415208097Smarius /* 416183423Smarius * On Tomatillo clear the I/O prefetch lengths (workaround for a 417183423Smarius * Jalapeno bug). 418183423Smarius */ 419183423Smarius if (mode == SCHIZO_MODE_TOM) 420220038Smarius SCHIZO_PCI_SET(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 421183423Smarius (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 422183423Smarius TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 423183423Smarius 424183423Smarius /* 425183423Smarius * Hunt through all the interrupt mapping regs and register 426186290Smarius * the interrupt controller for our interrupt vectors. We do 427186290Smarius * this early in order to be able to catch stray interrupts. 428186290Smarius * This is complicated by the fact that a pair of Schizo PBMs 429186290Smarius * shares one IGN. 430183423Smarius */ 431201199Smarius i = OF_getprop(node, "ino-bitmap", (void *)prop_array, 432183423Smarius sizeof(prop_array)); 433205254Smarius if (i != -1) 434205254Smarius ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 435205254Smarius else { 436205254Smarius /* 437205254Smarius * If the ino-bitmap property is missing, just provide the 438205254Smarius * default set of interrupts for this controller and let 439205254Smarius * schizo_setup_intr() take care of child interrupts. 440205254Smarius */ 441205254Smarius if (sc->sc_half == 0) 442205254Smarius ino_bitmap = (1ULL << STX_UE_INO) | 443205254Smarius (1ULL << STX_CE_INO) | 444205254Smarius (1ULL << STX_PCIERR_A_INO) | 445205254Smarius (1ULL << STX_BUS_INO); 446205254Smarius else 447205254Smarius ino_bitmap = 1ULL << STX_PCIERR_B_INO; 448205254Smarius } 449201199Smarius for (i = 0; i <= STX_MAX_INO; i++) { 450201199Smarius if ((ino_bitmap & (1ULL << i)) == 0) 451183423Smarius continue; 452201199Smarius if (i == STX_FB0_INO || i == STX_FB1_INO) 453183423Smarius /* Leave for upa(4). */ 454183423Smarius continue; 455201199Smarius j = schizo_intr_register(sc, i); 456201199Smarius if (j != 0) 457186290Smarius device_printf(dev, "could not register interrupt " 458201199Smarius "controller for INO %d (%d)\n", i, j); 459183423Smarius } 460183423Smarius 461183423Smarius /* 462183423Smarius * Setup Safari/JBus performance counter 0 in bus cycle counting 463183423Smarius * mode as timecounter. Unfortunately, this is broken with at 464183423Smarius * least the version 4 Tomatillos found in Fire V120 and Blade 465183423Smarius * 1500, which apparently actually count some different event at 466183423Smarius * ~0.5 and 3MHz respectively instead (also when running in full 467183423Smarius * power mode). Besides, one counter seems to be shared by a 468183423Smarius * "pair" of Tomatillos, too. 469183423Smarius */ 470183423Smarius if (sc->sc_half == 0) { 471220038Smarius SCHIZO_CTRL_SET(sc, STX_CTRL_PERF, 472183423Smarius (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 473183423Smarius (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 474183423Smarius tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 475183423Smarius if (tc == NULL) 476183423Smarius panic("%s: could not malloc timecounter", __func__); 477183423Smarius tc->tc_get_timecount = schizo_get_timecount; 478183423Smarius tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 479183423Smarius if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 480183423Smarius sizeof(prop)) == -1) 481183423Smarius panic("%s: could not determine clock frequency", 482183423Smarius __func__); 483183423Smarius tc->tc_frequency = prop; 484183423Smarius tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 485183423Smarius if (mode == SCHIZO_MODE_SCZ) 486183423Smarius tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 487183423Smarius else 488183423Smarius tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 489183423Smarius tc->tc_priv = sc; 490183423Smarius tc_init(tc); 491183423Smarius } 492183423Smarius 493190108Smarius /* 494190108Smarius * Set up the IOMMU. Schizo, Tomatillo and XMITS all have 495190108Smarius * one per PBM. Schizo and XMITS additionally have a streaming 496190108Smarius * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's 497225891Smarius * affected by several errata though. However, except for context 498225891Smarius * flushes, taking advantage of it should be okay even with those. 499190108Smarius */ 500220038Smarius memcpy(&sc->sc_dma_methods, &iommu_dma_methods, 501220038Smarius sizeof(sc->sc_dma_methods)); 502220038Smarius sc->sc_is.sis_sc = sc; 503220038Smarius sc->sc_is.sis_is.is_flags = IOMMU_PRESERVE_PROM; 504220038Smarius sc->sc_is.sis_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 505220038Smarius sc->sc_is.sis_is.is_sb[0] = sc->sc_is.sis_is.is_sb[1] = 0; 506225891Smarius if (OF_getproplen(node, "no-streaming-cache") < 0) 507220038Smarius sc->sc_is.sis_is.is_sb[0] = STX_PCI_STRBUF; 508183423Smarius 509183423Smarius#define TSBCASE(x) \ 510183423Smarius case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 511183423Smarius tsbsize = (x); \ 512183423Smarius break; \ 513183423Smarius 514201199Smarius i = OF_getprop(node, "virtual-dma", (void *)prop_array, 515183423Smarius sizeof(prop_array)); 516201199Smarius if (i == -1 || i != sizeof(prop_array)) 517183423Smarius schizo_iommu_init(sc, 7, -1); 518183423Smarius else { 519183423Smarius switch (prop_array[1]) { 520183423Smarius TSBCASE(1); 521183423Smarius TSBCASE(2); 522183423Smarius TSBCASE(3); 523183423Smarius TSBCASE(4); 524183423Smarius TSBCASE(5); 525183423Smarius TSBCASE(6); 526183423Smarius TSBCASE(7); 527183423Smarius TSBCASE(8); 528183423Smarius default: 529183423Smarius panic("%s: unsupported DVMA size 0x%x", 530183423Smarius __func__, prop_array[1]); 531183423Smarius /* NOTREACHED */ 532183423Smarius } 533183423Smarius schizo_iommu_init(sc, tsbsize, prop_array[0]); 534183423Smarius } 535185133Smarius 536183423Smarius#undef TSBCASE 537183423Smarius 538292789Smarius /* Create our DMA tag. */ 539183423Smarius if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 540220038Smarius sc->sc_is.sis_is.is_pmaxaddr, ~0, NULL, NULL, 541220038Smarius sc->sc_is.sis_is.is_pmaxaddr, 0xff, 0xffffffff, 0, NULL, NULL, 542292789Smarius &dmat) != 0) 543225931Smarius panic("%s: could not create PCI DMA tag", __func__); 544292789Smarius dmat->dt_cookie = &sc->sc_is; 545292789Smarius dmat->dt_mt = &sc->sc_dma_methods; 546183423Smarius 547292789Smarius if (ofw_pci_attach_common(dev, dmat, STX_IO_SIZE, STX_MEM_SIZE) != 0) 548292789Smarius panic("%s: ofw_pci_attach_common() failed", __func__); 549183423Smarius 550183423Smarius /* Clear any pending PCI error bits. */ 551292789Smarius PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE, 552292789Smarius STX_CS_FUNC, PCIR_STATUS, PCIB_READ_CONFIG(dev, 553292789Smarius sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 554292789Smarius 2), 2); 555220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 556220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_AFSR, SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 557183423Smarius 558183423Smarius /* 559183423Smarius * Establish handlers for interesting interrupts... 560183423Smarius * Someone at Sun clearly was smoking crack; with Schizos PCI 561183423Smarius * bus error interrupts for one PBM can be routed to the other 562183423Smarius * PBM though we obviously need to use the softc of the former 563183423Smarius * as the argument for the interrupt handler and the softc of 564183423Smarius * the latter as the argument for the interrupt controller. 565183423Smarius */ 566183423Smarius if (sc->sc_half == 0) { 567183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 568183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 569183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 570183423Smarius sica_sc == osc)) 571183423Smarius /* 572183423Smarius * We are the driver for PBM A and either also 573183423Smarius * registered the interrupt controller for us or 574183423Smarius * the driver for PBM B has probed first and 575183423Smarius * registered it for us. 576183423Smarius */ 577183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 578183423Smarius schizo_pci_bus); 579183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 580183423Smarius osc != NULL) 581183423Smarius /* 582183423Smarius * We are the driver for PBM A but registered 583183423Smarius * the interrupt controller for PBM B, i.e. the 584183423Smarius * driver for PBM B attached first but couldn't 585183423Smarius * set up a handler for PBM B. 586183423Smarius */ 587183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 588183423Smarius schizo_pci_bus); 589183423Smarius } else { 590183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 591183423Smarius (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 592183423Smarius INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 593183423Smarius sica_sc == osc)) 594183423Smarius /* 595183423Smarius * We are the driver for PBM B and either also 596183423Smarius * registered the interrupt controller for us or 597183423Smarius * the driver for PBM A has probed first and 598183423Smarius * registered it for us. 599183423Smarius */ 600183423Smarius schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 601183423Smarius schizo_pci_bus); 602183423Smarius if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 603183423Smarius osc != NULL) 604183423Smarius /* 605183423Smarius * We are the driver for PBM B but registered 606183423Smarius * the interrupt controller for PBM A, i.e. the 607183423Smarius * driver for PBM A attached first but couldn't 608183423Smarius * set up a handler for PBM A. 609183423Smarius */ 610183423Smarius schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 611183423Smarius schizo_pci_bus); 612183423Smarius } 613183423Smarius if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 614183423Smarius schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 615183423Smarius if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 616183423Smarius schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 617183423Smarius if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 618183423Smarius schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 619183423Smarius 620183423Smarius /* 621185133Smarius * According to the Schizo Errata I-13, consistent DMA flushing/ 622185133Smarius * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 623201126Smarius * so we can't use it and need to live with the consequences. With 624201126Smarius * Schizo version >= 5, CDMA flushing/syncing is usable but requires 625201126Smarius * the workaround described in Schizo Errata I-23. With Tomatillo 626201126Smarius * and XMITS, CDMA flushing/syncing works as expected, Tomatillo 627201126Smarius * version <= 4 (i.e. revision <= 2.3) bridges additionally require 628201126Smarius * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though. 629185133Smarius */ 630185133Smarius if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 631201199Smarius sc->sc_mode == SCHIZO_MODE_TOM || 632201199Smarius sc->sc_mode == SCHIZO_MODE_XMS) { 633185133Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ) { 634220038Smarius sc->sc_dma_methods.dm_dmamap_sync = 635220038Smarius schizo_dmamap_sync; 636220038Smarius sc->sc_cdma_state = SCHIZO_CDMA_STATE_IDLE; 637201126Smarius /* 638201126Smarius * Some firmware versions include the CDMA interrupt 639201126Smarius * at RID 4 but most don't. With the latter we add 640201126Smarius * it ourselves at the spare RID 5. 641201126Smarius */ 642201199Smarius i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ, 643201126Smarius 4)); 644201199Smarius if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) { 645230664Smarius sc->sc_cdma_vec = INTMAP_VEC(sc->sc_ign, i); 646230664Smarius (void)schizo_get_intrmap(sc, i, 647230664Smarius &sc->sc_cdma_map, &sc->sc_cdma_clr); 648201199Smarius schizo_set_intr(sc, 4, i, schizo_cdma); 649201126Smarius } else { 650201199Smarius i = STX_CDMA_A_INO + sc->sc_half; 651230664Smarius sc->sc_cdma_vec = INTMAP_VEC(sc->sc_ign, i); 652201126Smarius if (bus_set_resource(dev, SYS_RES_IRQ, 5, 653230664Smarius sc->sc_cdma_vec, 1) != 0) 654201126Smarius panic("%s: failed to add CDMA " 655201126Smarius "interrupt", __func__); 656201199Smarius j = schizo_intr_register(sc, i); 657201199Smarius if (j != 0) 658201126Smarius panic("%s: could not register " 659201126Smarius "interrupt controller for CDMA " 660201199Smarius "(%d)", __func__, j); 661230664Smarius (void)schizo_get_intrmap(sc, i, 662230664Smarius &sc->sc_cdma_map, &sc->sc_cdma_clr); 663201199Smarius schizo_set_intr(sc, 5, i, schizo_cdma); 664201126Smarius } 665220038Smarius } else { 666220038Smarius if (sc->sc_mode == SCHIZO_MODE_XMS) 667220038Smarius mtx_init(&sc->sc_sync_mtx, "pcib_sync_mtx", 668220038Smarius NULL, MTX_SPIN); 669220038Smarius sc->sc_sync_val = 1ULL << (STX_PCIERR_A_INO + 670220038Smarius sc->sc_half); 671220038Smarius sc->sc_dma_methods.dm_dmamap_sync = 672220038Smarius ichip_dmamap_sync; 673185133Smarius } 674185133Smarius if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 675185133Smarius sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 676185133Smarius } 677185133Smarius 678185133Smarius /* 679183423Smarius * Set the latency timer register as this isn't always done by the 680183423Smarius * firmware. 681183423Smarius */ 682292789Smarius PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE, 683292789Smarius STX_CS_FUNC, PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 684183423Smarius 685208097Smarius#define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \ 686208097Smarius SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \ 687208097Smarius SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, \ 688208097Smarius (name), CTLFLAG_RD, (arg), 0, (desc)) 689208097Smarius 690208097Smarius SCHIZO_SYSCTL_ADD_UINT("dma_ce", &sc->sc_stats_dma_ce, 691208097Smarius "DMA correctable errors"); 692208097Smarius SCHIZO_SYSCTL_ADD_UINT("pci_non_fatal", &sc->sc_stats_pci_non_fatal, 693208097Smarius "PCI bus non-fatal errors"); 694208097Smarius 695208097Smarius#undef SCHIZO_SYSCTL_ADD_UINT 696208097Smarius 697183423Smarius device_add_child(dev, "pci", -1); 698183423Smarius return (bus_generic_attach(dev)); 699183423Smarius} 700183423Smarius 701183423Smariusstatic void 702183423Smariusschizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 703183423Smarius driver_filter_t handler) 704183423Smarius{ 705183423Smarius u_long vec; 706183423Smarius int rid; 707183423Smarius 708183423Smarius rid = index; 709201199Smarius sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 710201199Smarius SYS_RES_IRQ, &rid, RF_ACTIVE); 711183423Smarius if (sc->sc_irq_res[index] == NULL || 712201199Smarius INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino || 713201199Smarius INTIGN(vec) != sc->sc_ign || 714183423Smarius intr_vectors[vec].iv_ic != &schizo_ic || 715185133Smarius bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 716216961Smarius INTR_TYPE_MISC | INTR_BRIDGE, handler, NULL, sc, 717185133Smarius &sc->sc_ihand[index]) != 0) 718183423Smarius panic("%s: failed to set up interrupt %d", __func__, index); 719183423Smarius} 720183423Smarius 721183423Smariusstatic int 722185133Smariusschizo_intr_register(struct schizo_softc *sc, u_int ino) 723185133Smarius{ 724185133Smarius struct schizo_icarg *sica; 725185133Smarius bus_addr_t intrclr, intrmap; 726185133Smarius int error; 727185133Smarius 728185133Smarius if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 729185133Smarius return (ENXIO); 730185133Smarius sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 731185133Smarius if (sica == NULL) 732185133Smarius return (ENOMEM); 733185133Smarius sica->sica_sc = sc; 734185133Smarius sica->sica_map = intrmap; 735185133Smarius sica->sica_clr = intrclr; 736185133Smarius#ifdef SCHIZO_DEBUG 737185133Smarius device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 738185133Smarius ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 739185133Smarius (u_long)intrclr); 740185133Smarius#endif 741185133Smarius error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 742185133Smarius &schizo_ic, sica)); 743185133Smarius if (error != 0) 744185133Smarius free(sica, M_DEVBUF); 745185133Smarius return (error); 746185133Smarius} 747185133Smarius 748185133Smariusstatic int 749201199Smariusschizo_get_intrmap(struct schizo_softc *sc, u_int ino, 750201199Smarius bus_addr_t *intrmapptr, bus_addr_t *intrclrptr) 751183423Smarius{ 752183423Smarius bus_addr_t intrclr, intrmap; 753183423Smarius uint64_t mr; 754183423Smarius 755183423Smarius /* 756183423Smarius * XXX we only look for INOs rather than INRs since the firmware 757183423Smarius * may not provide the IGN and the IGN is constant for all devices 758183423Smarius * on that PCI controller. 759183423Smarius */ 760183423Smarius 761183423Smarius if (ino > STX_MAX_INO) { 762183423Smarius device_printf(sc->sc_dev, "out of range INO %d requested\n", 763183423Smarius ino); 764183423Smarius return (0); 765183423Smarius } 766183423Smarius 767183423Smarius intrmap = STX_PCI_IMAP_BASE + (ino << 3); 768183423Smarius intrclr = STX_PCI_ICLR_BASE + (ino << 3); 769183423Smarius mr = SCHIZO_PCI_READ_8(sc, intrmap); 770183423Smarius if (INTINO(mr) != ino) { 771183423Smarius device_printf(sc->sc_dev, 772183423Smarius "interrupt map entry does not match INO (%d != %d)\n", 773183423Smarius (int)INTINO(mr), ino); 774183423Smarius return (0); 775183423Smarius } 776183423Smarius 777183423Smarius if (intrmapptr != NULL) 778183423Smarius *intrmapptr = intrmap; 779183423Smarius if (intrclrptr != NULL) 780183423Smarius *intrclrptr = intrclr; 781183423Smarius return (1); 782183423Smarius} 783183423Smarius 784183423Smarius/* 785183423Smarius * Interrupt handlers 786183423Smarius */ 787183423Smariusstatic int 788183423Smariusschizo_pci_bus(void *arg) 789183423Smarius{ 790183423Smarius struct schizo_softc *sc = arg; 791220038Smarius uint64_t afar, afsr, csr, iommu, xstat; 792183423Smarius uint32_t status; 793208097Smarius u_int fatal; 794183423Smarius 795208097Smarius fatal = 0; 796208097Smarius 797208097Smarius mtx_lock_spin(sc->sc_mtx); 798208097Smarius 799183423Smarius afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 800183423Smarius afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 801183423Smarius csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 802183423Smarius iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 803220038Smarius if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 804220038Smarius xstat = SCHIZO_PCI_READ_8(sc, XMS_PCI_X_ERR_STAT); 805220038Smarius else 806220038Smarius xstat = 0; 807292789Smarius status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_ops.sc_pci_secbus, 808183423Smarius STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 809183423Smarius 810208097Smarius /* 811208097Smarius * IOMMU errors are only fatal on Tomatillo and there also only if 812208097Smarius * target abort was not signaled. 813208097Smarius */ 814208097Smarius if ((csr & STX_PCI_CTRL_MMU_ERR) != 0 && 815208097Smarius (iommu & TOM_PCI_IOMMU_ERR) != 0 && 816208097Smarius ((status & PCIM_STATUS_STABORT) == 0 || 817208097Smarius ((iommu & TOM_PCI_IOMMU_ERRMASK) != TOM_PCI_IOMMU_INVALID_ERR && 818208097Smarius (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) == 0 && 819208097Smarius (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) == 0))) 820208097Smarius fatal = 1; 821208097Smarius else if ((status & PCIM_STATUS_STABORT) != 0) 822208097Smarius fatal = 1; 823208097Smarius if ((status & (PCIM_STATUS_PERR | PCIM_STATUS_SERR | 824208097Smarius PCIM_STATUS_RMABORT | PCIM_STATUS_RTABORT | 825212378Sjhb PCIM_STATUS_MDPERR)) != 0 || 826208097Smarius (csr & (SCZ_PCI_CTRL_BUS_UNUS | TOM_PCI_CTRL_DTO_ERR | 827208097Smarius STX_PCI_CTRL_TTO_ERR | STX_PCI_CTRL_RTRY_ERR | 828208097Smarius SCZ_PCI_CTRL_SBH_ERR | STX_PCI_CTRL_SERR)) != 0 || 829208097Smarius (afsr & (STX_PCI_AFSR_P_MA | STX_PCI_AFSR_P_TA | 830208097Smarius STX_PCI_AFSR_P_RTRY | STX_PCI_AFSR_P_PERR | STX_PCI_AFSR_P_TTO | 831208097Smarius STX_PCI_AFSR_P_UNUS)) != 0) 832208097Smarius fatal = 1; 833220038Smarius if (xstat & (XMS_PCI_X_ERR_STAT_P_SC_DSCRD | 834220038Smarius XMS_PCI_X_ERR_STAT_P_SC_TTO | XMS_PCI_X_ERR_STAT_P_SDSTAT | 835220038Smarius XMS_PCI_X_ERR_STAT_P_SMMU | XMS_PCI_X_ERR_STAT_P_CDSTAT | 836220038Smarius XMS_PCI_X_ERR_STAT_P_CMMU | XMS_PCI_X_ERR_STAT_PERR_RCV)) 837220038Smarius fatal = 1; 838208097Smarius if (fatal == 0) 839208097Smarius sc->sc_stats_pci_non_fatal++; 840183423Smarius 841208097Smarius device_printf(sc->sc_dev, "PCI bus %c error AFAR %#llx AFSR %#llx " 842220038Smarius "PCI CSR %#llx IOMMU %#llx PCI-X %#llx STATUS %#x\n", 843220038Smarius 'A' + sc->sc_half, (unsigned long long)afar, 844220038Smarius (unsigned long long)afsr, (unsigned long long)csr, 845220038Smarius (unsigned long long)iommu, (unsigned long long)xstat, status); 846183423Smarius 847183423Smarius /* Clear the error bits that we caught. */ 848292789Smarius PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE, 849183423Smarius STX_CS_FUNC, PCIR_STATUS, status, 2); 850183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 851183423Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 852208097Smarius SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 853220038Smarius if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 854220038Smarius SCHIZO_PCI_WRITE_8(sc, XMS_PCI_X_ERR_STAT, xstat); 855208097Smarius 856208097Smarius mtx_unlock_spin(sc->sc_mtx); 857208097Smarius 858208097Smarius if (fatal != 0) 859208097Smarius panic("%s: fatal PCI bus error", 860208097Smarius device_get_nameunit(sc->sc_dev)); 861183423Smarius return (FILTER_HANDLED); 862183423Smarius} 863183423Smarius 864183423Smariusstatic int 865183423Smariusschizo_ue(void *arg) 866183423Smarius{ 867183423Smarius struct schizo_softc *sc = arg; 868183423Smarius uint64_t afar, afsr; 869183423Smarius int i; 870183423Smarius 871183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 872183423Smarius for (i = 0; i < 1000; i++) 873183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 874183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 875183423Smarius break; 876183423Smarius panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 877206020Smarius device_get_nameunit(sc->sc_dev), (unsigned long long)afar, 878183423Smarius (unsigned long long)afsr); 879183423Smarius return (FILTER_HANDLED); 880183423Smarius} 881183423Smarius 882183423Smariusstatic int 883183423Smariusschizo_ce(void *arg) 884183423Smarius{ 885183423Smarius struct schizo_softc *sc = arg; 886183423Smarius uint64_t afar, afsr; 887183423Smarius int i; 888183423Smarius 889183423Smarius mtx_lock_spin(sc->sc_mtx); 890208097Smarius 891183423Smarius afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 892183423Smarius for (i = 0; i < 1000; i++) 893183423Smarius if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 894183423Smarius STX_CTRL_CE_AFSR_ERRPNDG) == 0) 895183423Smarius break; 896208097Smarius sc->sc_stats_dma_ce++; 897183423Smarius device_printf(sc->sc_dev, 898183423Smarius "correctable DMA error AFAR %#llx AFSR %#llx\n", 899183423Smarius (unsigned long long)afar, (unsigned long long)afsr); 900208097Smarius 901183423Smarius /* Clear the error bits that we caught. */ 902183423Smarius SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 903208097Smarius 904183423Smarius mtx_unlock_spin(sc->sc_mtx); 905208097Smarius 906183423Smarius return (FILTER_HANDLED); 907183423Smarius} 908183423Smarius 909183423Smariusstatic int 910183423Smariusschizo_host_bus(void *arg) 911183423Smarius{ 912183423Smarius struct schizo_softc *sc = arg; 913183423Smarius uint64_t errlog; 914183423Smarius 915183423Smarius errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 916206020Smarius panic("%s: %s error %#llx", device_get_nameunit(sc->sc_dev), 917183423Smarius sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 918183423Smarius (unsigned long long)errlog); 919183423Smarius return (FILTER_HANDLED); 920183423Smarius} 921183423Smarius 922185133Smariusstatic int 923185133Smariusschizo_cdma(void *arg) 924185133Smarius{ 925185133Smarius struct schizo_softc *sc = arg; 926185133Smarius 927230664Smarius atomic_cmpset_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_PENDING, 928230664Smarius SCHIZO_CDMA_STATE_RECEIVED); 929185133Smarius return (FILTER_HANDLED); 930185133Smarius} 931185133Smarius 932183423Smariusstatic void 933183423Smariusschizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 934183423Smarius{ 935183423Smarius 936183423Smarius /* Punch in our copies. */ 937220038Smarius sc->sc_is.sis_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 938220038Smarius sc->sc_is.sis_is.is_bushandle = 939220038Smarius rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 940220038Smarius sc->sc_is.sis_is.is_iommu = STX_PCI_IOMMU; 941220038Smarius sc->sc_is.sis_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 942220038Smarius sc->sc_is.sis_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 943220038Smarius sc->sc_is.sis_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 944220038Smarius sc->sc_is.sis_is.is_dva = STX_PCI_IOMMU_SVADIAG; 945220038Smarius sc->sc_is.sis_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 946183423Smarius 947220038Smarius iommu_init(device_get_nameunit(sc->sc_dev), 948220038Smarius (struct iommu_state *)&sc->sc_is, tsbsize, dvmabase, 0); 949183423Smarius} 950183423Smarius 951183423Smariusstatic int 952183423Smariusschizo_maxslots(device_t dev) 953183423Smarius{ 954183423Smarius struct schizo_softc *sc; 955183423Smarius 956183423Smarius sc = device_get_softc(dev); 957183423Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ) 958183423Smarius return (sc->sc_half == 0 ? 4 : 6); 959183423Smarius 960183423Smarius /* XXX: is this correct? */ 961183423Smarius return (PCI_SLOTMAX); 962183423Smarius} 963183423Smarius 964183423Smariusstatic uint32_t 965183423Smariusschizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 966183423Smarius int width) 967183423Smarius{ 968183423Smarius struct schizo_softc *sc; 969183423Smarius 970183423Smarius sc = device_get_softc(dev); 971183423Smarius /* 972183423Smarius * The Schizo bridges contain a dupe of their header at 0x80. 973183423Smarius */ 974292789Smarius if (sc->sc_mode == SCHIZO_MODE_SCZ && 975292789Smarius bus == sc->sc_ops.sc_pci_secbus && slot == STX_CS_DEVICE && 976292789Smarius func == STX_CS_FUNC && reg + width > 0x80) 977183423Smarius return (0); 978183423Smarius 979292789Smarius return (ofw_pci_read_config_common(dev, PCI_REGMAX, STX_CONF_OFF(bus, 980292789Smarius slot, func, reg), bus, slot, func, reg, width)); 981183423Smarius} 982183423Smarius 983183423Smariusstatic void 984201199Smariusschizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, 985201199Smarius u_int reg, uint32_t val, int width) 986183423Smarius{ 987183423Smarius 988292789Smarius ofw_pci_write_config_common(dev, PCI_REGMAX, STX_CONF_OFF(bus, slot, 989292789Smarius func, reg), bus, slot, func, reg, val, width); 990183423Smarius} 991183423Smarius 992183423Smariusstatic int 993183423Smariusschizo_route_interrupt(device_t bridge, device_t dev, int pin) 994183423Smarius{ 995292789Smarius ofw_pci_intr_t mintr; 996183423Smarius 997292789Smarius mintr = ofw_pci_route_interrupt_common(bridge, dev, pin); 998292789Smarius if (!PCI_INTERRUPT_VALID(mintr)) 999292789Smarius device_printf(bridge, 1000292789Smarius "could not route pin %d for device %d.%d\n", 1001292789Smarius pin, pci_get_slot(dev), pci_get_function(dev)); 1002292789Smarius return (mintr); 1003183423Smarius} 1004183423Smarius 1005220038Smariusstatic void 1006220038Smariusschizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1007185133Smarius{ 1008185133Smarius struct timeval cur, end; 1009220038Smarius struct schizo_iommu_state *sis = dt->dt_cookie; 1010220038Smarius struct schizo_softc *sc = sis->sis_sc; 1011230664Smarius int i, res; 1012230664Smarius#ifdef INVARIANTS 1013230664Smarius register_t pil; 1014230664Smarius#endif 1015185133Smarius 1016220038Smarius if ((map->dm_flags & DMF_STREAMED) != 0) { 1017220038Smarius iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1018220038Smarius return; 1019220038Smarius } 1020220038Smarius 1021220038Smarius if ((map->dm_flags & DMF_LOADED) == 0) 1022220038Smarius return; 1023220038Smarius 1024220038Smarius if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1025220038Smarius /* 1026225931Smarius * Note that in order to allow this function to be called from 1027220038Smarius * filters we would need to use a spin mutex for serialization 1028220038Smarius * but given that these disable interrupts we have to emulate 1029220038Smarius * one. 1030220038Smarius */ 1031230664Smarius critical_enter(); 1032230664Smarius KASSERT((rdpr(pstate) & PSTATE_IE) != 0, 1033230664Smarius ("%s: interrupts disabled", __func__)); 1034230664Smarius KASSERT((pil = rdpr(pil)) <= PIL_BRIDGE, 1035230664Smarius ("%s: PIL too low (%ld)", __func__, pil)); 1036220038Smarius for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, 1037220038Smarius SCHIZO_CDMA_STATE_IDLE, SCHIZO_CDMA_STATE_PENDING) == 0;) 1038220038Smarius ; 1039230664Smarius SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_map, 1040230664Smarius INTMAP_ENABLE(sc->sc_cdma_vec, PCPU_GET(mid))); 1041230664Smarius for (i = 0; i < SCHIZO_CDMA_TRIES; i++) { 1042230664Smarius if (i > 0) 1043230664Smarius printf("%s: try %d\n", __func__, i); 1044230664Smarius SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, 1045230664Smarius INTCLR_RECEIVED); 1046220038Smarius microuptime(&cur); 1047230664Smarius end.tv_sec = SCHIZO_CDMA_TIMEOUT; 1048230664Smarius end.tv_usec = 0; 1049230664Smarius timevaladd(&end, &cur); 1050230664Smarius for (; (res = atomic_cmpset_rel_32(&sc->sc_cdma_state, 1051230664Smarius SCHIZO_CDMA_STATE_RECEIVED, 1052230664Smarius SCHIZO_CDMA_STATE_IDLE)) == 0 && 1053230664Smarius timevalcmp(&cur, &end, <=);) 1054230664Smarius microuptime(&cur); 1055230664Smarius if (res != 0) 1056230664Smarius break; 1057230664Smarius } 1058220038Smarius if (res == 0) 1059220038Smarius panic("%s: DMA does not sync", __func__); 1060230664Smarius critical_exit(); 1061220038Smarius } 1062220038Smarius 1063220038Smarius if ((op & BUS_DMASYNC_PREWRITE) != 0) 1064220038Smarius membar(Sync); 1065185133Smarius} 1066185133Smarius 1067220038Smariusstatic void 1068220038Smariusichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1069183423Smarius{ 1070185133Smarius struct timeval cur, end; 1071220038Smarius struct schizo_iommu_state *sis = dt->dt_cookie; 1072220038Smarius struct schizo_softc *sc = sis->sis_sc; 1073292789Smarius uint64_t reg; 1074183423Smarius 1075220038Smarius if ((map->dm_flags & DMF_STREAMED) != 0) { 1076220038Smarius iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1077220038Smarius return; 1078220038Smarius } 1079220038Smarius 1080220038Smarius if ((map->dm_flags & DMF_LOADED) == 0) 1081220038Smarius return; 1082220038Smarius 1083220038Smarius if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1084220038Smarius if (sc->sc_mode == SCHIZO_MODE_XMS) 1085220038Smarius mtx_lock_spin(&sc->sc_sync_mtx); 1086220038Smarius SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, 1087220038Smarius sc->sc_sync_val); 1088185133Smarius microuptime(&cur); 1089220038Smarius end.tv_sec = 1; 1090220038Smarius end.tv_usec = 0; 1091220038Smarius timevaladd(&end, &cur); 1092220038Smarius for (; ((reg = SCHIZO_PCI_READ_8(sc, 1093220038Smarius TOMXMS_PCI_DMA_SYNC_PEND)) & sc->sc_sync_val) != 0 && 1094220038Smarius timevalcmp(&cur, &end, <=);) 1095220038Smarius microuptime(&cur); 1096220038Smarius if ((reg & sc->sc_sync_val) != 0) 1097220038Smarius panic("%s: DMA does not sync", __func__); 1098220038Smarius if (sc->sc_mode == SCHIZO_MODE_XMS) 1099220038Smarius mtx_unlock_spin(&sc->sc_sync_mtx); 1100220038Smarius else if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1101292789Smarius ofw_pci_dmamap_sync_stst_order_common(); 1102220038Smarius return; 1103220038Smarius } 1104220038Smarius } 1105183423Smarius 1106220038Smarius if ((op & BUS_DMASYNC_PREWRITE) != 0) 1107184428Smarius membar(Sync); 1108183423Smarius} 1109183423Smarius 1110183423Smariusstatic void 1111183423Smariusschizo_intr_enable(void *arg) 1112183423Smarius{ 1113183423Smarius struct intr_vector *iv = arg; 1114183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1115183423Smarius 1116183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1117183423Smarius INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1118183423Smarius} 1119183423Smarius 1120183423Smariusstatic void 1121183423Smariusschizo_intr_disable(void *arg) 1122183423Smarius{ 1123183423Smarius struct intr_vector *iv = arg; 1124183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1125183423Smarius 1126183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1127183423Smarius} 1128183423Smarius 1129183423Smariusstatic void 1130183423Smariusschizo_intr_assign(void *arg) 1131183423Smarius{ 1132183423Smarius struct intr_vector *iv = arg; 1133183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1134183423Smarius 1135183423Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1136183423Smarius SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1137183423Smarius} 1138183423Smarius 1139183423Smariusstatic void 1140183423Smariusschizo_intr_clear(void *arg) 1141183423Smarius{ 1142183423Smarius struct intr_vector *iv = arg; 1143183423Smarius struct schizo_icarg *sica = iv->iv_icarg; 1144183423Smarius 1145206018Smarius SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE); 1146183423Smarius} 1147183423Smarius 1148183423Smariusstatic int 1149183423Smariusschizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1150183423Smarius int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1151183423Smarius void **cookiep) 1152183423Smarius{ 1153183423Smarius struct schizo_softc *sc; 1154183423Smarius u_long vec; 1155220038Smarius int error; 1156183423Smarius 1157183423Smarius sc = device_get_softc(dev); 1158183423Smarius /* 1159186290Smarius * Make sure the vector is fully specified. 1160183423Smarius */ 1161183423Smarius vec = rman_get_start(ires); 1162186290Smarius if (INTIGN(vec) != sc->sc_ign) { 1163183423Smarius device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1164183423Smarius return (EINVAL); 1165183423Smarius } 1166183423Smarius 1167186290Smarius if (intr_vectors[vec].iv_ic == &schizo_ic) { 1168186290Smarius /* 1169186290Smarius * Ensure we use the right softc in case the interrupt 1170186290Smarius * is routed to our companion PBM for some odd reason. 1171186290Smarius */ 1172186290Smarius sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 1173186290Smarius sica_sc; 1174186290Smarius } else if (intr_vectors[vec].iv_ic == NULL) { 1175186290Smarius /* 1176186290Smarius * Work around broken firmware which misses entries in 1177186290Smarius * the ino-bitmap. 1178186290Smarius */ 1179186290Smarius error = schizo_intr_register(sc, INTINO(vec)); 1180186290Smarius if (error != 0) { 1181186290Smarius device_printf(dev, "could not register interrupt " 1182186290Smarius "controller for vector 0x%lx (%d)\n", vec, error); 1183186290Smarius return (error); 1184186290Smarius } 1185190108Smarius if (bootverbose) 1186190108Smarius device_printf(dev, "belatedly registered as " 1187190108Smarius "interrupt controller for vector 0x%lx\n", vec); 1188186290Smarius } else { 1189186290Smarius device_printf(dev, 1190186290Smarius "invalid interrupt controller for vector 0x%lx\n", vec); 1191186290Smarius return (EINVAL); 1192186290Smarius } 1193183423Smarius return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1194183423Smarius arg, cookiep)); 1195183423Smarius} 1196183423Smarius 1197183423Smariusstatic struct resource * 1198183423Smariusschizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1199183423Smarius u_long start, u_long end, u_long count, u_int flags) 1200183423Smarius{ 1201183423Smarius struct schizo_softc *sc; 1202183423Smarius 1203292789Smarius if (type == SYS_RES_IRQ) { 1204292789Smarius sc = device_get_softc(bus); 1205183423Smarius start = end = INTMAP_VEC(sc->sc_ign, end); 1206183423Smarius } 1207292789Smarius return (ofw_pci_alloc_resource(bus, child, type, rid, start, end, 1208292789Smarius count, flags)); 1209183423Smarius} 1210183423Smarius 1211220038Smariusstatic void 1212220038Smariusschizo_setup_device(device_t bus, device_t child) 1213220038Smarius{ 1214220038Smarius struct schizo_softc *sc; 1215220038Smarius uint64_t reg; 1216220038Smarius int capreg; 1217220038Smarius 1218220038Smarius sc = device_get_softc(bus); 1219220038Smarius /* 1220220038Smarius * Disable bus parking in order to work around a bus hang caused by 1221220038Smarius * Casinni/Skyhawk combinations. 1222225931Smarius */ 1223220038Smarius if (OF_getproplen(ofw_bus_get_node(child), "pci-req-removal") >= 0) 1224220038Smarius SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, 1225220038Smarius STX_PCI_CTRL) & ~STX_PCI_CTRL_ARB_PARK); 1226220038Smarius 1227220038Smarius if (sc->sc_mode == SCHIZO_MODE_XMS) { 1228220038Smarius /* XMITS NCPQ WAR: set outstanding split transactions to 1. */ 1229220038Smarius if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 && 1230220038Smarius (pci_read_config(child, PCIR_HDRTYPE, 1) & 1231220038Smarius PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE && 1232220038Smarius pci_find_cap(child, PCIY_PCIX, &capreg) == 0) 1233220038Smarius pci_write_config(child, capreg + PCIXR_COMMAND, 1234220038Smarius pci_read_config(child, capreg + PCIXR_COMMAND, 1235220038Smarius 2) & 0x7c, 2); 1236220038Smarius /* XMITS 3.x WAR: set BUGCNTL iff value is unexpected. */ 1237220038Smarius if (sc->sc_mrev >= 4) { 1238220038Smarius reg = ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 1239220038Smarius 0xa0UL : 0xffUL) << XMS_PCI_X_DIAG_BUGCNTL_SHIFT; 1240220038Smarius if ((SCHIZO_PCI_READ_8(sc, XMS_PCI_X_DIAG) & 1241220038Smarius XMS_PCI_X_DIAG_BUGCNTL_MASK) != reg) 1242220038Smarius SCHIZO_PCI_SET(sc, XMS_PCI_X_DIAG, reg); 1243220038Smarius } 1244220038Smarius } 1245220038Smarius} 1246220038Smarius 1247183423Smariusstatic u_int 1248183423Smariusschizo_get_timecount(struct timecounter *tc) 1249183423Smarius{ 1250183423Smarius struct schizo_softc *sc; 1251183423Smarius 1252183423Smarius sc = tc->tc_priv; 1253223959Smarius return ((SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1254223959Smarius (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)) >> 1255223959Smarius STX_CTRL_PERF_CNT_CNT0_SHIFT); 1256183423Smarius} 1257