1139825Simp/*- 286230Stmm * Copyright (c) 1992, 1993 386230Stmm * The Regents of the University of California. All rights reserved. 486230Stmm * 586230Stmm * This software was developed by the Computer Systems Engineering group 686230Stmm * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 786230Stmm * contributed to Berkeley. 886230Stmm * 986230Stmm * Redistribution and use in source and binary forms, with or without 1086230Stmm * modification, are permitted provided that the following conditions 1186230Stmm * are met: 1286230Stmm * 1. Redistributions of source code must retain the above copyright 1386230Stmm * notice, this list of conditions and the following disclaimer. 1486230Stmm * 2. Redistributions in binary form must reproduce the above copyright 1586230Stmm * notice, this list of conditions and the following disclaimer in the 1686230Stmm * documentation and/or other materials provided with the distribution. 1786230Stmm * 4. Neither the name of the University nor the names of its contributors 1886230Stmm * may be used to endorse or promote products derived from this software 1986230Stmm * without specific prior written permission. 2086230Stmm * 2186230Stmm * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 2286230Stmm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2386230Stmm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2486230Stmm * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 2586230Stmm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2686230Stmm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2786230Stmm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2886230Stmm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2986230Stmm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3086230Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3186230Stmm * SUCH DAMAGE. 3286230Stmm * 3386230Stmm * from: @(#)sbusreg.h 8.1 (Berkeley) 6/11/93 3486230Stmm * from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp 3586230Stmm * 3686230Stmm * $FreeBSD: releng/10.3/sys/sparc64/include/iommureg.h 218909 2011-02-21 09:01:34Z brucec $ 3786230Stmm */ 3886230Stmm 3986230Stmm#ifndef _MACHINE_IOMMUREG_H_ 40200922Smarius#define _MACHINE_IOMMUREG_H_ 4186230Stmm 4286230Stmm/* 43167308Smarius * UltraSPARC IOMMU registers, common to both the PCI and SBus 4486230Stmm * controllers. 4586230Stmm */ 4686230Stmm 47200923Smarius/* IOMMU registers */ 4890705Stmm#define IMR_CTL 0x0000 /* IOMMU control register */ 4990705Stmm#define IMR_TSB 0x0008 /* IOMMU TSB base register */ 5090705Stmm#define IMR_FLUSH 0x0010 /* IOMMU flush register */ 51200923Smarius/* The TTE Cache is Fire and Oberon only. */ 52200923Smarius#define IMR_CACHE_FLUSH 0x0100 /* IOMMU TTE cache flush address register */ 53200923Smarius#define IMR_CACHE_INVAL 0x0108 /* IOMMU TTE cache invalidate register */ 5486230Stmm 5586230Stmm/* streaming buffer registers */ 5690705Stmm#define ISR_CTL 0x0000 /* streaming buffer control reg */ 5790705Stmm#define ISR_PGFLUSH 0x0008 /* streaming buffer page flush */ 5890705Stmm#define ISR_FLUSHSYNC 0x0010 /* streaming buffer flush sync */ 5986230Stmm 60185008Smarius/* streaming buffer diagnostics registers */ 6190705Stmm#define ISD_DATA_DIAG 0x0000 /* streaming buffer data RAM diag 0..127 */ 6290705Stmm#define ISD_ERROR_DIAG 0x0400 /* streaming buffer error status diag 0..127 */ 6390705Stmm#define ISD_PG_TAG_DIAG 0x0800 /* streaming buffer page tag diag 0..15 */ 6490705Stmm#define ISD_LN_TAG_DIAG 0x0900 /* streaming buffer line tag diag 0..15 */ 6590705Stmm 6686230Stmm/* streaming buffer control register */ 67200922Smarius#define STRBUF_EN 0x0000000000000001UL 68200922Smarius#define STRBUF_D 0x0000000000000002UL 69200922Smarius#define STRBUF_RR_DIS 0x0000000000000004UL 7086230Stmm 71171730Smarius#define IOMMU_MAXADDR(bits) ((1UL << (bits)) - 1) 7286230Stmm 7386230Stmm/* 7486230Stmm * control register bits 7586230Stmm */ 76200923Smarius/* Nummber of entries in the IOTSB - pre-Fire only */ 77200923Smarius#define IOMMUCR_TSBSZ_MASK 0x0000000000070000UL 7890705Stmm#define IOMMUCR_TSBSZ_SHIFT 16 79200923Smarius/* TSB cache snoop enable */ 80200923Smarius#define IOMMUCR_SE 0x0000000000000400UL 81200923Smarius/* Cache modes - Fire and Oberon */ 82200923Smarius#define IOMMUCR_CM_NC_TLB_TBW 0x0000000000000000UL 83200923Smarius#define IOMMUCR_CM_LC_NTLB_NTBW 0x0000000000000100UL 84200923Smarius#define IOMMUCR_CM_LC_TLB_TBW 0x0000000000000200UL 85200923Smarius#define IOMMUCR_CM_C_TLB_TBW 0x0000000000000300UL 86200923Smarius/* IOMMU page size - pre-Fire only */ 87200922Smarius#define IOMMUCR_8KPG 0x0000000000000000UL 88200922Smarius#define IOMMUCR_64KPG 0x0000000000000004UL 89200923Smarius/* Bypass enable - Fire and Oberon */ 90200923Smarius#define IOMMUCR_BE 0x0000000000000002UL 91200923Smarius/* Diagnostic mode enable - pre-Fire only */ 92200922Smarius#define IOMMUCR_DE 0x0000000000000002UL 93200923Smarius/* IOMMU/translation enable */ 94200922Smarius#define IOMMUCR_EN 0x0000000000000001UL 9586230Stmm 9686230Stmm/* 97200923Smarius * TSB base register bits 98200923Smarius */ 99200923Smarius /* TSB base address */ 100200923Smarius#define IOMMUTB_TB_MASK 0x000007ffffffe000UL 101200923Smarius#define IOMMUTB_TB_SHIFT 13 102200923Smarius/* IOMMU page size - Fire and Oberon */ 103200923Smarius#define IOMMUTB_8KPG 0x0000000000000000UL 104200923Smarius#define IOMMUTB_64KPG 0x0000000000000100UL 105200923Smarius/* Nummber of entries in the IOTSB - Fire and Oberon */ 106200923Smarius#define IOMMUTB_TSBSZ_MASK 0x0000000000000004UL 107200923Smarius#define IOMMUTB_TSBSZ_SHIFT 0 108200923Smarius 109200923Smarius/* 110200923Smarius * TSB size definitions for both control and TSB base register */ 111200923Smarius#define IOMMU_TSB1K 0 112200923Smarius#define IOMMU_TSB2K 1 113200923Smarius#define IOMMU_TSB4K 2 114200923Smarius#define IOMMU_TSB8K 3 115200923Smarius#define IOMMU_TSB16K 4 116200923Smarius#define IOMMU_TSB32K 5 117200923Smarius#define IOMMU_TSB64K 6 118200923Smarius#define IOMMU_TSB128K 7 119200923Smarius/* Fire and Oberon */ 120200923Smarius#define IOMMU_TSB256K 8 121200923Smarius/* Fire and Oberon */ 122200923Smarius#define IOMMU_TSB512K 9 123200923Smarius#define IOMMU_TSBENTRIES(tsbsz) \ 124200923Smarius ((1 << (tsbsz)) << (IO_PAGE_SHIFT - IOTTE_SHIFT)) 125200923Smarius 126200923Smarius/* 127185008Smarius * Diagnostic register definitions 128108802Stmm */ 129108802Stmm#define IOMMU_DTAG_VPNBITS 19 130108802Stmm#define IOMMU_DTAG_VPNMASK ((1 << IOMMU_DTAG_VPNBITS) - 1) 131108802Stmm#define IOMMU_DTAG_VPNSHIFT 13 132200922Smarius#define IOMMU_DTAG_ERRBITS 3 133108802Stmm#define IOMMU_DTAG_ERRSHIFT 22 134200922Smarius#define IOMMU_DTAG_ERRMASK \ 135108802Stmm (((1 << IOMMU_DTAG_ERRBITS) - 1) << IOMMU_DTAG_ERRSHIFT) 136108802Stmm 137108802Stmm#define IOMMU_DDATA_PGBITS 21 138108802Stmm#define IOMMU_DDATA_PGMASK ((1 << IOMMU_DDATA_PGBITS) - 1) 139108802Stmm#define IOMMU_DDATA_PGSHIFT 13 140108802Stmm#define IOMMU_DDATA_C (1 << 28) 141108802Stmm#define IOMMU_DDATA_V (1 << 30) 142108802Stmm 143108802Stmm/* 14486230Stmm * IOMMU stuff 14586230Stmm */ 14686230Stmm/* Entry valid */ 14786230Stmm#define IOTTE_V 0x8000000000000000UL 148200923Smarius/* Page size - pre-Fire only */ 149200922Smarius#define IOTTE_64K 0x2000000000000000UL 150200922Smarius#define IOTTE_8K 0x0000000000000000UL 151200923Smarius/* Streamable page - streaming buffer equipped variants only */ 152200922Smarius#define IOTTE_STREAM 0x1000000000000000UL 153200923Smarius/* Accesses to the same bus segment - SBus only */ 15486230Stmm#define IOTTE_LOCAL 0x0800000000000000UL 155200923Smarius/* Physical address mask (based on Oberon) */ 156200923Smarius#define IOTTE_PAMASK 0x00007fffffffe000UL 157200923Smarius/* Accesses to cacheable space - pre-Fire only */ 158200922Smarius#define IOTTE_C 0x0000000000000010UL 15986230Stmm/* Writeable */ 160200922Smarius#define IOTTE_W 0x0000000000000002UL 16186230Stmm 162185008Smarius/* log2 of the IOMMU TTE size */ 16390705Stmm#define IOTTE_SHIFT 3 16490705Stmm 165185008Smarius/* Streaming buffer line size */ 166108802Stmm#define STRBUF_LINESZ 64 167108802Stmm 16886230Stmm/* 16990705Stmm * Number of bytes written by a stream buffer flushsync operation to indicate 17090705Stmm * completion. 17190705Stmm */ 172108802Stmm#define STRBUF_FLUSHSYNC_NBYTES STRBUF_LINESZ 17390705Stmm 17490705Stmm/* 175167308Smarius * On sun4u each bus controller has a separate IOMMU. The IOMMU has 17686230Stmm * a TSB which must be page aligned and physically contiguous. Mappings 17786230Stmm * can be of 8K IOMMU pages or 64K IOMMU pages. We use 8K for compatibility 17886230Stmm * with the CPU's MMU. 17986230Stmm * 18086230Stmm * On sysio, psycho, and psycho+, IOMMU TSBs using 8K pages can map the 18186230Stmm * following size segments: 18286230Stmm * 18386230Stmm * VA size VA base TSB size tsbsize 18486230Stmm * -------- -------- --------- ------- 18586230Stmm * 8MB ff800000 8K 0 18686230Stmm * 16MB ff000000 16K 1 18786230Stmm * 32MB fe000000 32K 2 18886230Stmm * 64MB fc000000 64K 3 18986230Stmm * 128MB f8000000 128K 4 19086230Stmm * 256MB f0000000 256K 5 19186230Stmm * 512MB e0000000 512K 6 19286230Stmm * 1GB c0000000 1MB 7 19386230Stmm * 19486230Stmm * Unfortunately, sabres on UltraSPARC IIi and IIe processors does not use 19586230Stmm * this scheme to determine the IOVA base address. Instead, bits 31-29 are 19686230Stmm * used to check against the Target Address Space register in the IIi and 197218909Sbrucec * the IOMMU is used if they hit. God knows what goes on in the IIe. 19886230Stmm * 19986230Stmm */ 20086230Stmm 201108802Stmm#define IOTSB_BASESZ (1024 << IOTTE_SHIFT) 202200922Smarius#define IOTSB_VEND (~IO_PAGE_MASK) 203200922Smarius#define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz) + 10)) 20486230Stmm 205200922Smarius#define MAKEIOTTE(pa, w, c, s) \ 20686230Stmm (((pa) & IOTTE_PAMASK) | ((w) ? IOTTE_W : 0) | \ 20786230Stmm ((c) ? IOTTE_C : 0) | ((s) ? IOTTE_STREAM : 0) | \ 20886230Stmm (IOTTE_V | IOTTE_8K)) 209200922Smarius#define IOTSBSLOT(va) \ 21090705Stmm ((u_int)(((vm_offset_t)(va)) - (is->is_dvmabase)) >> IO_PAGE_SHIFT) 21186230Stmm 21286230Stmm#endif /* !_MACHINE_IOMMUREG_H_ */ 213