if_glcreg.h revision 217044
1249423Sdim/*- 2243789Sdim * Copyright (C) 2010 Nathan Whitehorn 3243789Sdim * All rights reserved. 4243789Sdim * 5243789Sdim * Redistribution and use in source and binary forms, with or without 6243789Sdim * modification, are permitted provided that the following conditions 7243789Sdim * are met: 8243789Sdim * 1. Redistributions of source code must retain the above copyright 9243789Sdim * notice, this list of conditions and the following disclaimer. 10243789Sdim * 2. Redistributions in binary form must reproduce the above copyright 11243789Sdim * notice, this list of conditions and the following disclaimer in the 12243789Sdim * documentation and/or other materials provided with the distribution. 13243789Sdim * 14243789Sdim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15243789Sdim * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16249423Sdim * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17249423Sdim * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 18243789Sdim * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 19249423Sdim * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 20243789Sdim * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21243789Sdim * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 22243789Sdim * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 23243789Sdim * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24243789Sdim * 25243789Sdim * $FreeBSD: head/sys/powerpc/ps3/if_glcreg.h 217044 2011-01-06 04:12:29Z nwhitehorn $ 26243789Sdim */ 27243789Sdim 28243789Sdim#ifndef _POWERPC_PS3_IF_GLCREG_H 29243789Sdim#define _POWERPC_PS3_IF_GLCREG_H 30243789Sdim 31243789Sdim#define GLC_MAX_TX_PACKETS 128 32243789Sdim#define GLC_MAX_RX_PACKETS 128 33243789Sdim 34243789Sdimstruct glc_dmadesc; 35243789Sdim 36243789Sdim/* 37243789Sdim * software state for transmit job mbufs (may be elements of mbuf chains) 38243789Sdim */ 39243789Sdim 40243789Sdimstruct glc_txsoft { 41243789Sdim struct mbuf *txs_mbuf; /* head of our mbuf chain */ 42243789Sdim bus_dmamap_t txs_dmamap; /* our DMA map */ 43243789Sdim int txs_firstdesc; /* first descriptor in packet */ 44243789Sdim int txs_lastdesc; /* last descriptor in packet */ 45243789Sdim 46243789Sdim int txs_ndescs; /* number of descriptors */ 47243789Sdim STAILQ_ENTRY(glc_txsoft) txs_q; 48243789Sdim}; 49243789Sdim 50243789SdimSTAILQ_HEAD(glc_txsq, glc_txsoft); 51243789Sdim 52243789Sdim/* 53243789Sdim * software state for receive jobs 54243789Sdim */ 55243789Sdimstruct glc_rxsoft { 56243789Sdim struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 57243789Sdim bus_dmamap_t rxs_dmamap; /* our DMA map */ 58243789Sdim 59243789Sdim int rxs_desc_slot; /* DMA descriptor for this packet */ 60243789Sdim bus_addr_t rxs_desc; 61243789Sdim 62243789Sdim bus_dma_segment_t segment; 63243789Sdim}; 64243789Sdim 65243789Sdimstruct glc_softc { 66243789Sdim struct ifnet *sc_ifp; 67243789Sdim device_t sc_self; 68243789Sdim struct mtx sc_mtx; 69243789Sdim u_char sc_enaddr[ETHER_ADDR_LEN]; 70243789Sdim int sc_tx_vlan, sc_rx_vlan; 71243789Sdim int sc_ifpflags; 72243789Sdim 73243789Sdim uint64_t sc_dma_base[5]; 74243789Sdim bus_dma_tag_t sc_dmadesc_tag; 75243789Sdim 76243789Sdim int sc_irqid; 77243789Sdim struct resource *sc_irq; 78243789Sdim void *sc_irqctx; 79243789Sdim uint64_t *sc_hwirq_status; 80243789Sdim volatile uint64_t sc_interrupt_status; 81243789Sdim 82243789Sdim struct ifmedia sc_media; 83243789Sdim 84243789Sdim /* Transmission */ 85243789Sdim 86243789Sdim bus_dma_tag_t sc_txdma_tag; 87243789Sdim struct glc_txsoft sc_txsoft[GLC_MAX_TX_PACKETS]; 88243789Sdim struct glc_dmadesc *sc_txdmadesc; 89243789Sdim int next_txdma_slot, first_used_txdma_slot, bsy_txdma_slots; 90243789Sdim bus_dmamap_t sc_txdmadesc_map; 91243789Sdim bus_addr_t sc_txdmadesc_phys; 92243789Sdim 93243789Sdim struct glc_txsq sc_txfreeq; 94243789Sdim struct glc_txsq sc_txdirtyq; 95243789Sdim 96243789Sdim /* Reception */ 97243789Sdim 98243789Sdim bus_dma_tag_t sc_rxdma_tag; 99243789Sdim struct glc_rxsoft sc_rxsoft[GLC_MAX_RX_PACKETS]; 100243789Sdim struct glc_dmadesc *sc_rxdmadesc; 101243789Sdim int sc_next_rxdma_slot; 102243789Sdim bus_dmamap_t sc_rxdmadesc_map; 103243789Sdim bus_addr_t sc_rxdmadesc_phys; 104243789Sdim 105243789Sdim int sc_bus, sc_dev; 106243789Sdim int sc_wdog_timer; 107243789Sdim struct callout sc_tick_ch; 108243789Sdim}; 109243789Sdim 110243789Sdim#define GELIC_GET_MAC_ADDRESS 0x0001 111243789Sdim#define GELIC_GET_LINK_STATUS 0x0002 112243789Sdim#define GELIC_SET_LINK_MODE 0x0003 113243789Sdim#define GELIC_LINK_UP 0x0001 114243789Sdim#define GELIC_FULL_DUPLEX 0x0002 115243789Sdim#define GELIC_AUTO_NEG 0x0004 116243789Sdim#define GELIC_SPEED_10 0x0010 117243789Sdim#define GELIC_SPEED_100 0x0020 118243789Sdim#define GELIC_SPEED_1000 0x0040 119243789Sdim#define GELIC_GET_VLAN_ID 0x0004 120243789Sdim#define GELIC_VLAN_TX_ETHERNET 0x0002 121243789Sdim#define GELIC_VLAN_RX_ETHERNET 0x0012 122243789Sdim#define GELIC_VLAN_TX_WIRELESS 0x0003 123243789Sdim#define GELIC_VLAN_RX_WIRELESS 0x0013 124243789Sdim 125243789Sdim/* Command status code */ 126243789Sdim#define GELIC_DESCR_OWNED 0xa0000000 127243789Sdim#define GELIC_CMDSTAT_DMA_DONE 0x00000000 128243789Sdim#define GELIC_CMDSTAT_CHAIN_END 0x00000002 129243789Sdim#define GELIC_CMDSTAT_CSUM_TCP 0x00020000 130243789Sdim#define GELIC_CMDSTAT_CSUM_UDP 0x00030000 131243789Sdim#define GELIC_CMDSTAT_NOIPSEC 0x00080000 132243789Sdim#define GELIC_CMDSTAT_LAST 0x00040000 133243789Sdim#define GELIC_RXERRORS 0x7def8000 134243789Sdim 135243789Sdim/* RX Data Status codes */ 136243789Sdim#define GELIC_RX_IPCSUM 0x20000000 137243789Sdim#define GELIC_RX_TCPUDPCSUM 0x10000000 138243789Sdim 139243789Sdim/* Interrupt options */ 140243789Sdim#define GELIC_INT_RXDONE 0x0000000000004000UL 141243789Sdim#define GELIC_INT_RXFRAME 0x1000000000000000UL 142243789Sdim#define GELIC_INT_TXDONE 0x0080000000000000UL 143243789Sdim#define GELIC_INT_TX_CHAIN_END 0x0100000000000000UL 144243789Sdim#define GELIC_INT_PHY 0x0000000020000000UL 145243789Sdim 146243789Sdim/* Hardware DMA descriptor. Must be 32-byte aligned */ 147243789Sdim 148243789Sdimstruct glc_dmadesc { 149243789Sdim uint32_t paddr; /* Must be 128 byte aligned for receive */ 150243789Sdim uint32_t len; 151243789Sdim uint32_t next; 152243789Sdim uint32_t cmd_stat; 153263508Sdim uint32_t result_size; 154243789Sdim uint32_t valid_size; 155243789Sdim uint32_t data_stat; 156243789Sdim uint32_t rxerror; 157243789Sdim}; 158243789Sdim 159243789Sdim#endif /* _POWERPC_PS3_IF_GLCREG_H */ 160243789Sdim 161243789Sdim