1217044Snwhitehorn/*- 2217044Snwhitehorn * Copyright (C) 2010 Nathan Whitehorn 3217044Snwhitehorn * All rights reserved. 4217044Snwhitehorn * 5217044Snwhitehorn * Redistribution and use in source and binary forms, with or without 6217044Snwhitehorn * modification, are permitted provided that the following conditions 7217044Snwhitehorn * are met: 8217044Snwhitehorn * 1. Redistributions of source code must retain the above copyright 9217044Snwhitehorn * notice, this list of conditions and the following disclaimer. 10217044Snwhitehorn * 2. Redistributions in binary form must reproduce the above copyright 11217044Snwhitehorn * notice, this list of conditions and the following disclaimer in the 12217044Snwhitehorn * documentation and/or other materials provided with the distribution. 13217044Snwhitehorn * 14217044Snwhitehorn * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15217044Snwhitehorn * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16217044Snwhitehorn * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17217044Snwhitehorn * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 18217044Snwhitehorn * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 19217044Snwhitehorn * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 20217044Snwhitehorn * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21217044Snwhitehorn * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 22217044Snwhitehorn * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 23217044Snwhitehorn * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24217044Snwhitehorn * 25217044Snwhitehorn * $FreeBSD: releng/10.3/sys/powerpc/ps3/if_glcreg.h 217044 2011-01-06 04:12:29Z nwhitehorn $ 26217044Snwhitehorn */ 27217044Snwhitehorn 28217044Snwhitehorn#ifndef _POWERPC_PS3_IF_GLCREG_H 29217044Snwhitehorn#define _POWERPC_PS3_IF_GLCREG_H 30217044Snwhitehorn 31217044Snwhitehorn#define GLC_MAX_TX_PACKETS 128 32217044Snwhitehorn#define GLC_MAX_RX_PACKETS 128 33217044Snwhitehorn 34217044Snwhitehornstruct glc_dmadesc; 35217044Snwhitehorn 36217044Snwhitehorn/* 37217044Snwhitehorn * software state for transmit job mbufs (may be elements of mbuf chains) 38217044Snwhitehorn */ 39217044Snwhitehorn 40217044Snwhitehornstruct glc_txsoft { 41217044Snwhitehorn struct mbuf *txs_mbuf; /* head of our mbuf chain */ 42217044Snwhitehorn bus_dmamap_t txs_dmamap; /* our DMA map */ 43217044Snwhitehorn int txs_firstdesc; /* first descriptor in packet */ 44217044Snwhitehorn int txs_lastdesc; /* last descriptor in packet */ 45217044Snwhitehorn 46217044Snwhitehorn int txs_ndescs; /* number of descriptors */ 47217044Snwhitehorn STAILQ_ENTRY(glc_txsoft) txs_q; 48217044Snwhitehorn}; 49217044Snwhitehorn 50217044SnwhitehornSTAILQ_HEAD(glc_txsq, glc_txsoft); 51217044Snwhitehorn 52217044Snwhitehorn/* 53217044Snwhitehorn * software state for receive jobs 54217044Snwhitehorn */ 55217044Snwhitehornstruct glc_rxsoft { 56217044Snwhitehorn struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 57217044Snwhitehorn bus_dmamap_t rxs_dmamap; /* our DMA map */ 58217044Snwhitehorn 59217044Snwhitehorn int rxs_desc_slot; /* DMA descriptor for this packet */ 60217044Snwhitehorn bus_addr_t rxs_desc; 61217044Snwhitehorn 62217044Snwhitehorn bus_dma_segment_t segment; 63217044Snwhitehorn}; 64217044Snwhitehorn 65217044Snwhitehornstruct glc_softc { 66217044Snwhitehorn struct ifnet *sc_ifp; 67217044Snwhitehorn device_t sc_self; 68217044Snwhitehorn struct mtx sc_mtx; 69217044Snwhitehorn u_char sc_enaddr[ETHER_ADDR_LEN]; 70217044Snwhitehorn int sc_tx_vlan, sc_rx_vlan; 71217044Snwhitehorn int sc_ifpflags; 72217044Snwhitehorn 73217044Snwhitehorn uint64_t sc_dma_base[5]; 74217044Snwhitehorn bus_dma_tag_t sc_dmadesc_tag; 75217044Snwhitehorn 76217044Snwhitehorn int sc_irqid; 77217044Snwhitehorn struct resource *sc_irq; 78217044Snwhitehorn void *sc_irqctx; 79217044Snwhitehorn uint64_t *sc_hwirq_status; 80217044Snwhitehorn volatile uint64_t sc_interrupt_status; 81217044Snwhitehorn 82217044Snwhitehorn struct ifmedia sc_media; 83217044Snwhitehorn 84217044Snwhitehorn /* Transmission */ 85217044Snwhitehorn 86217044Snwhitehorn bus_dma_tag_t sc_txdma_tag; 87217044Snwhitehorn struct glc_txsoft sc_txsoft[GLC_MAX_TX_PACKETS]; 88217044Snwhitehorn struct glc_dmadesc *sc_txdmadesc; 89217044Snwhitehorn int next_txdma_slot, first_used_txdma_slot, bsy_txdma_slots; 90217044Snwhitehorn bus_dmamap_t sc_txdmadesc_map; 91217044Snwhitehorn bus_addr_t sc_txdmadesc_phys; 92217044Snwhitehorn 93217044Snwhitehorn struct glc_txsq sc_txfreeq; 94217044Snwhitehorn struct glc_txsq sc_txdirtyq; 95217044Snwhitehorn 96217044Snwhitehorn /* Reception */ 97217044Snwhitehorn 98217044Snwhitehorn bus_dma_tag_t sc_rxdma_tag; 99217044Snwhitehorn struct glc_rxsoft sc_rxsoft[GLC_MAX_RX_PACKETS]; 100217044Snwhitehorn struct glc_dmadesc *sc_rxdmadesc; 101217044Snwhitehorn int sc_next_rxdma_slot; 102217044Snwhitehorn bus_dmamap_t sc_rxdmadesc_map; 103217044Snwhitehorn bus_addr_t sc_rxdmadesc_phys; 104217044Snwhitehorn 105217044Snwhitehorn int sc_bus, sc_dev; 106217044Snwhitehorn int sc_wdog_timer; 107217044Snwhitehorn struct callout sc_tick_ch; 108217044Snwhitehorn}; 109217044Snwhitehorn 110217044Snwhitehorn#define GELIC_GET_MAC_ADDRESS 0x0001 111217044Snwhitehorn#define GELIC_GET_LINK_STATUS 0x0002 112217044Snwhitehorn#define GELIC_SET_LINK_MODE 0x0003 113217044Snwhitehorn#define GELIC_LINK_UP 0x0001 114217044Snwhitehorn#define GELIC_FULL_DUPLEX 0x0002 115217044Snwhitehorn#define GELIC_AUTO_NEG 0x0004 116217044Snwhitehorn#define GELIC_SPEED_10 0x0010 117217044Snwhitehorn#define GELIC_SPEED_100 0x0020 118217044Snwhitehorn#define GELIC_SPEED_1000 0x0040 119217044Snwhitehorn#define GELIC_GET_VLAN_ID 0x0004 120217044Snwhitehorn#define GELIC_VLAN_TX_ETHERNET 0x0002 121217044Snwhitehorn#define GELIC_VLAN_RX_ETHERNET 0x0012 122217044Snwhitehorn#define GELIC_VLAN_TX_WIRELESS 0x0003 123217044Snwhitehorn#define GELIC_VLAN_RX_WIRELESS 0x0013 124217044Snwhitehorn 125217044Snwhitehorn/* Command status code */ 126217044Snwhitehorn#define GELIC_DESCR_OWNED 0xa0000000 127217044Snwhitehorn#define GELIC_CMDSTAT_DMA_DONE 0x00000000 128217044Snwhitehorn#define GELIC_CMDSTAT_CHAIN_END 0x00000002 129217044Snwhitehorn#define GELIC_CMDSTAT_CSUM_TCP 0x00020000 130217044Snwhitehorn#define GELIC_CMDSTAT_CSUM_UDP 0x00030000 131217044Snwhitehorn#define GELIC_CMDSTAT_NOIPSEC 0x00080000 132217044Snwhitehorn#define GELIC_CMDSTAT_LAST 0x00040000 133217044Snwhitehorn#define GELIC_RXERRORS 0x7def8000 134217044Snwhitehorn 135217044Snwhitehorn/* RX Data Status codes */ 136217044Snwhitehorn#define GELIC_RX_IPCSUM 0x20000000 137217044Snwhitehorn#define GELIC_RX_TCPUDPCSUM 0x10000000 138217044Snwhitehorn 139217044Snwhitehorn/* Interrupt options */ 140217044Snwhitehorn#define GELIC_INT_RXDONE 0x0000000000004000UL 141217044Snwhitehorn#define GELIC_INT_RXFRAME 0x1000000000000000UL 142217044Snwhitehorn#define GELIC_INT_TXDONE 0x0080000000000000UL 143217044Snwhitehorn#define GELIC_INT_TX_CHAIN_END 0x0100000000000000UL 144217044Snwhitehorn#define GELIC_INT_PHY 0x0000000020000000UL 145217044Snwhitehorn 146217044Snwhitehorn/* Hardware DMA descriptor. Must be 32-byte aligned */ 147217044Snwhitehorn 148217044Snwhitehornstruct glc_dmadesc { 149217044Snwhitehorn uint32_t paddr; /* Must be 128 byte aligned for receive */ 150217044Snwhitehorn uint32_t len; 151217044Snwhitehorn uint32_t next; 152217044Snwhitehorn uint32_t cmd_stat; 153217044Snwhitehorn uint32_t result_size; 154217044Snwhitehorn uint32_t valid_size; 155217044Snwhitehorn uint32_t data_stat; 156217044Snwhitehorn uint32_t rxerror; 157217044Snwhitehorn}; 158217044Snwhitehorn 159217044Snwhitehorn#endif /* _POWERPC_PS3_IF_GLCREG_H */ 160217044Snwhitehorn 161