uninorthpci.c revision 266019
1184902Srwatson/*- 2186647Srwatson * Copyright (C) 2002 Benno Rice. 3184902Srwatson * All rights reserved. 4184902Srwatson * 5184902Srwatson * Redistribution and use in source and binary forms, with or without 6184902Srwatson * modification, are permitted provided that the following conditions 7184902Srwatson * are met: 8184902Srwatson * 1. Redistributions of source code must retain the above copyright 9184902Srwatson * notice, this list of conditions and the following disclaimer. 10184902Srwatson * 2. Redistributions in binary form must reproduce the above copyright 11184902Srwatson * notice, this list of conditions and the following disclaimer in the 12184902Srwatson * documentation and/or other materials provided with the distribution. 13184902Srwatson * 14184902Srwatson * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 15184902Srwatson * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16184902Srwatson * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17184902Srwatson * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 18243750Srwatson * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 19184902Srwatson * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 20184902Srwatson * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21184902Srwatson * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 22184902Srwatson * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 23184902Srwatson * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24184902Srwatson */ 25184902Srwatson 26184902Srwatson#include <sys/cdefs.h> 27184902Srwatson__FBSDID("$FreeBSD: stable/10/sys/powerpc/powermac/uninorthpci.c 266019 2014-05-14 14:08:45Z ian $"); 28184902Srwatson 29184902Srwatson#include <sys/param.h> 30184902Srwatson#include <sys/systm.h> 31184902Srwatson#include <sys/module.h> 32184902Srwatson#include <sys/bus.h> 33184902Srwatson#include <sys/conf.h> 34184902Srwatson#include <sys/kernel.h> 35184902Srwatson 36184902Srwatson#include <dev/ofw/openfirm.h> 37184902Srwatson#include <dev/ofw/ofw_pci.h> 38184902Srwatson#include <dev/ofw/ofw_bus.h> 39184902Srwatson#include <dev/ofw/ofw_bus_subr.h> 40184902Srwatson 41184902Srwatson#include <dev/pci/pcivar.h> 42184902Srwatson#include <dev/pci/pcireg.h> 43184902Srwatson 44184902Srwatson#include <machine/bus.h> 45184902Srwatson#include <machine/intr_machdep.h> 46184902Srwatson#include <machine/md_var.h> 47184902Srwatson#include <machine/pio.h> 48184902Srwatson#include <machine/resource.h> 49184902Srwatson 50184902Srwatson#include <sys/rman.h> 51184902Srwatson 52184902Srwatson#include <powerpc/ofw/ofw_pci.h> 53184902Srwatson#include <powerpc/powermac/uninorthvar.h> 54184902Srwatson 55184902Srwatson#include <vm/vm.h> 56184902Srwatson#include <vm/pmap.h> 57184902Srwatson 58184902Srwatson#include "pcib_if.h" 59184902Srwatson 60184902Srwatson#define UNINORTH_DEBUG 0 61184902Srwatson 62184902Srwatson/* 63184902Srwatson * Device interface. 64184902Srwatson */ 65184902Srwatsonstatic int uninorth_probe(device_t); 66184902Srwatsonstatic int uninorth_attach(device_t); 67184902Srwatson 68184902Srwatson/* 69184902Srwatson * pcib interface. 70184902Srwatson */ 71184902Srwatsonstatic u_int32_t uninorth_read_config(device_t, u_int, u_int, u_int, 72184902Srwatson u_int, int); 73184902Srwatsonstatic void uninorth_write_config(device_t, u_int, u_int, u_int, 74184902Srwatson u_int, u_int32_t, int); 75184902Srwatson 76184902Srwatson/* 77184902Srwatson * Local routines. 78184902Srwatson */ 79184902Srwatsonstatic int uninorth_enable_config(struct uninorth_softc *, u_int, 80184902Srwatson u_int, u_int, u_int); 81184902Srwatson 82184902Srwatson/* 83184902Srwatson * Driver methods. 84184902Srwatson */ 85184902Srwatsonstatic device_method_t uninorth_methods[] = { 86184902Srwatson /* Device interface */ 87184902Srwatson DEVMETHOD(device_probe, uninorth_probe), 88184902Srwatson DEVMETHOD(device_attach, uninorth_attach), 89184902Srwatson 90184902Srwatson /* pcib interface */ 91184902Srwatson DEVMETHOD(pcib_read_config, uninorth_read_config), 92184902Srwatson DEVMETHOD(pcib_write_config, uninorth_write_config), 93184902Srwatson 94184902Srwatson DEVMETHOD_END 95184902Srwatson}; 96184902Srwatson 97184902Srwatsonstatic devclass_t uninorth_devclass; 98184902Srwatson 99184902SrwatsonDEFINE_CLASS_1(pcib, uninorth_driver, uninorth_methods, 100184902Srwatson sizeof(struct uninorth_softc), ofw_pci_driver); 101184902SrwatsonDRIVER_MODULE(uninorth, nexus, uninorth_driver, uninorth_devclass, 0, 0); 102184902Srwatson 103184902Srwatsonstatic int 104184902Srwatsonuninorth_probe(device_t dev) 105184902Srwatson{ 106184902Srwatson const char *type, *compatible; 107184902Srwatson 108184902Srwatson type = ofw_bus_get_type(dev); 109184902Srwatson compatible = ofw_bus_get_compat(dev); 110184902Srwatson 111184902Srwatson if (type == NULL || compatible == NULL) 112184902Srwatson return (ENXIO); 113184902Srwatson 114184902Srwatson if (strcmp(type, "pci") != 0) 115184902Srwatson return (ENXIO); 116 117 if (strcmp(compatible, "uni-north") == 0) { 118 device_set_desc(dev, "Apple UniNorth Host-PCI bridge"); 119 return (0); 120 } else if (strcmp(compatible, "u3-agp") == 0) { 121 device_set_desc(dev, "Apple U3 Host-AGP bridge"); 122 return (0); 123 } else if (strcmp(compatible, "u4-pcie") == 0) { 124 device_set_desc(dev, "IBM CPC945 PCI Express Root"); 125 return (0); 126 } 127 128 return (ENXIO); 129} 130 131static int 132uninorth_attach(device_t dev) 133{ 134 struct uninorth_softc *sc; 135 const char *compatible; 136 phandle_t node; 137 uint32_t reg[3]; 138 uint64_t regbase; 139 cell_t acells; 140 141 node = ofw_bus_get_node(dev); 142 sc = device_get_softc(dev); 143 144 if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8) 145 return (ENXIO); 146 147 sc->sc_ver = 0; 148 compatible = ofw_bus_get_compat(dev); 149 if (strcmp(compatible, "u3-agp") == 0) 150 sc->sc_ver = 3; 151 if (strcmp(compatible, "u4-pcie") == 0) 152 sc->sc_ver = 4; 153 154 acells = 1; 155 OF_getprop(OF_parent(node), "#address-cells", &acells, sizeof(acells)); 156 157 regbase = reg[0]; 158 if (acells == 2) { 159 regbase <<= 32; 160 regbase |= reg[1]; 161 } 162 163 sc->sc_addr = (vm_offset_t)pmap_mapdev(regbase + 0x800000, PAGE_SIZE); 164 sc->sc_data = (vm_offset_t)pmap_mapdev(regbase + 0xc00000, PAGE_SIZE); 165 166 return (ofw_pci_attach(dev)); 167} 168 169static u_int32_t 170uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 171 int width) 172{ 173 struct uninorth_softc *sc; 174 vm_offset_t caoff; 175 176 sc = device_get_softc(dev); 177 caoff = sc->sc_data + (reg & 0x07); 178 179 if (uninorth_enable_config(sc, bus, slot, func, reg) != 0) { 180 switch (width) { 181 case 1: 182 return (in8rb(caoff)); 183 break; 184 case 2: 185 return (in16rb(caoff)); 186 break; 187 case 4: 188 return (in32rb(caoff)); 189 break; 190 } 191 } 192 193 return (0xffffffff); 194} 195 196static void 197uninorth_write_config(device_t dev, u_int bus, u_int slot, u_int func, 198 u_int reg, u_int32_t val, int width) 199{ 200 struct uninorth_softc *sc; 201 vm_offset_t caoff; 202 203 sc = device_get_softc(dev); 204 caoff = sc->sc_data + (reg & 0x07); 205 206 if (uninorth_enable_config(sc, bus, slot, func, reg)) { 207 switch (width) { 208 case 1: 209 out8rb(caoff, val); 210 break; 211 case 2: 212 out16rb(caoff, val); 213 break; 214 case 4: 215 out32rb(caoff, val); 216 break; 217 } 218 } 219} 220 221static int 222uninorth_enable_config(struct uninorth_softc *sc, u_int bus, u_int slot, 223 u_int func, u_int reg) 224{ 225 uint32_t cfgval; 226 uint32_t pass; 227 228 if (resource_int_value(device_get_name(sc->pci_sc.sc_dev), 229 device_get_unit(sc->pci_sc.sc_dev), "skipslot", &pass) == 0) { 230 if (pass == slot) 231 return (0); 232 } 233 234 /* 235 * Issue type 0 configuration space accesses for the root bus. 236 * 237 * NOTE: On U4, issue only type 1 accesses. There is a secret 238 * PCI Express <-> PCI Express bridge not present in the device tree, 239 * and we need to route all of our configuration space through it. 240 */ 241 if (sc->pci_sc.sc_bus == bus && sc->sc_ver < 4) { 242 /* 243 * No slots less than 11 on the primary bus on U3 and lower 244 */ 245 if (slot < 11) 246 return (0); 247 248 cfgval = (1 << slot) | (func << 8) | (reg & 0xfc); 249 } else { 250 cfgval = (bus << 16) | (slot << 11) | (func << 8) | 251 (reg & 0xfc) | 1; 252 } 253 254 /* Set extended register bits on U4 */ 255 if (sc->sc_ver == 4) 256 cfgval |= (reg >> 8) << 28; 257 258 do { 259 out32rb(sc->sc_addr, cfgval); 260 } while (in32rb(sc->sc_addr) != cfgval); 261 262 return (1); 263} 264 265