1176770Sraj/*- 2236141Sraj * Copyright (C) 2006-2012 Semihalf. 3176770Sraj * All rights reserved. 4176770Sraj * 5176770Sraj * Redistribution and use in source and binary forms, with or without 6176770Sraj * modification, are permitted provided that the following conditions 7176770Sraj * are met: 8176770Sraj * 1. Redistributions of source code must retain the above copyright 9176770Sraj * notice, this list of conditions and the following disclaimer. 10176770Sraj * 2. Redistributions in binary form must reproduce the above copyright 11176770Sraj * notice, this list of conditions and the following disclaimer in the 12176770Sraj * documentation and/or other materials provided with the distribution. 13176770Sraj * 3. The name of the author may not be used to endorse or promote products 14176770Sraj * derived from this software without specific prior written permission. 15176770Sraj * 16176770Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17176770Sraj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18176770Sraj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 19176770Sraj * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20176770Sraj * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 21176770Sraj * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 22176770Sraj * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 23176770Sraj * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 24176770Sraj * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25176770Sraj * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26176770Sraj * 27176770Sraj * $FreeBSD: releng/10.3/sys/powerpc/include/tlb.h 265996 2014-05-14 00:51:26Z ian $ 28176770Sraj */ 29176770Sraj 30176770Sraj#ifndef _MACHINE_TLB_H_ 31176770Sraj#define _MACHINE_TLB_H_ 32176770Sraj 33236141Sraj#if defined(BOOKE_E500) 34236141Sraj 35176770Sraj/* PowerPC E500 MAS registers */ 36176770Sraj#define MAS0_TLBSEL(x) ((x << 28) & 0x10000000) 37176770Sraj#define MAS0_ESEL(x) ((x << 16) & 0x000F0000) 38176770Sraj 39176770Sraj#define MAS0_TLBSEL1 0x10000000 40176770Sraj#define MAS0_TLBSEL0 0x00000000 41176770Sraj#define MAS0_ESEL_TLB1MASK 0x000F0000 42176770Sraj#define MAS0_ESEL_TLB0MASK 0x00030000 43176770Sraj#define MAS0_ESEL_SHIFT 16 44176770Sraj#define MAS0_NV_MASK 0x00000003 45176770Sraj#define MAS0_NV_SHIFT 0 46176770Sraj 47176770Sraj#define MAS1_VALID 0x80000000 48176770Sraj#define MAS1_IPROT 0x40000000 49176770Sraj#define MAS1_TID_MASK 0x00FF0000 50176770Sraj#define MAS1_TID_SHIFT 16 51187149Sraj#define MAS1_TS_MASK 0x00001000 52187149Sraj#define MAS1_TS_SHIFT 12 53176770Sraj#define MAS1_TSIZE_MASK 0x00000F00 54176770Sraj#define MAS1_TSIZE_SHIFT 8 55176770Sraj 56176770Sraj#define TLB_SIZE_4K 1 57176770Sraj#define TLB_SIZE_16K 2 58176770Sraj#define TLB_SIZE_64K 3 59176770Sraj#define TLB_SIZE_256K 4 60176770Sraj#define TLB_SIZE_1M 5 61176770Sraj#define TLB_SIZE_4M 6 62176770Sraj#define TLB_SIZE_16M 7 63176770Sraj#define TLB_SIZE_64M 8 64176770Sraj#define TLB_SIZE_256M 9 65176770Sraj#define TLB_SIZE_1G 10 66176770Sraj#define TLB_SIZE_4G 11 67176770Sraj 68187149Sraj#define MAS2_EPN_MASK 0xFFFFF000 69176770Sraj#define MAS2_EPN_SHIFT 12 70176770Sraj#define MAS2_X0 0x00000040 71176770Sraj#define MAS2_X1 0x00000020 72176770Sraj#define MAS2_W 0x00000010 73176770Sraj#define MAS2_I 0x00000008 74176770Sraj#define MAS2_M 0x00000004 75176770Sraj#define MAS2_G 0x00000002 76176770Sraj#define MAS2_E 0x00000001 77176770Sraj 78176770Sraj#define MAS3_RPN 0xFFFFF000 79176770Sraj#define MAS3_RPN_SHIFT 12 80176770Sraj#define MAS3_U0 0x00000200 81176770Sraj#define MAS3_U1 0x00000100 82176770Sraj#define MAS3_U2 0x00000080 83176770Sraj#define MAS3_U3 0x00000040 84176770Sraj#define MAS3_UX 0x00000020 85176770Sraj#define MAS3_SX 0x00000010 86176770Sraj#define MAS3_UW 0x00000008 87176770Sraj#define MAS3_SW 0x00000004 88176770Sraj#define MAS3_UR 0x00000002 89176770Sraj#define MAS3_SR 0x00000001 90176770Sraj 91176770Sraj#define MAS4_TLBSELD1 0x10000000 92176770Sraj#define MAS4_TLBSELD0 0x00000000 93176770Sraj#define MAS4_TIDSELD_MASK 0x00030000 94176770Sraj#define MAS4_TIDSELD_SHIFT 16 95176770Sraj#define MAS4_TSIZED_MASK 0x00000F00 96176770Sraj#define MAS4_TSIZED_SHIFT 8 97176770Sraj#define MAS4_X0D 0x00000040 98176770Sraj#define MAS4_X1D 0x00000020 99176770Sraj#define MAS4_WD 0x00000010 100176770Sraj#define MAS4_ID 0x00000008 101176770Sraj#define MAS4_MD 0x00000004 102176770Sraj#define MAS4_GD 0x00000002 103176770Sraj#define MAS4_ED 0x00000001 104176770Sraj 105176770Sraj#define MAS6_SPID0_MASK 0x00FF0000 106176770Sraj#define MAS6_SPID0_SHIFT 16 107176770Sraj#define MAS6_SAS 0x00000001 108176770Sraj 109176770Sraj#define MAS1_GETTID(mas1) (((mas1) & MAS1_TID_MASK) >> MAS1_TID_SHIFT) 110176770Sraj 111176770Sraj#define MAS2_TLB0_ENTRY_IDX_MASK 0x0007f000 112176770Sraj#define MAS2_TLB0_ENTRY_IDX_SHIFT 12 113176770Sraj 114176770Sraj/* 115187149Sraj * Maximum number of TLB1 entries used for a permanent mapping of kernel 116187149Sraj * region (kernel image plus statically allocated data). 117176770Sraj */ 118176770Sraj#define KERNEL_REGION_MAX_TLB_ENTRIES 4 119176770Sraj 120176770Sraj#define _TLB_ENTRY_IO (MAS2_I | MAS2_G) 121187149Sraj#ifdef SMP 122187149Sraj#define _TLB_ENTRY_MEM (MAS2_M) 123187149Sraj#else 124176770Sraj#define _TLB_ENTRY_MEM (0) 125187149Sraj#endif 126176770Sraj 127236141Sraj#if !defined(LOCORE) 128236141Srajtypedef struct tlb_entry { 129265996Sian vm_paddr_t phys; 130265996Sian vm_offset_t virt; 131265996Sian vm_size_t size; 132236141Sraj uint32_t mas1; 133236141Sraj uint32_t mas2; 134236141Sraj uint32_t mas3; 135236141Sraj} tlb_entry_t; 136236141Sraj 137236141Srajvoid tlb0_print_tlbentries(void); 138236141Sraj 139236141Srajvoid tlb1_inval_entry(unsigned int); 140265996Sianvoid tlb1_init(void); 141236141Srajvoid tlb1_print_entries(void); 142236141Srajvoid tlb1_print_tlbentries(void); 143236141Sraj#endif /* !LOCORE */ 144236141Sraj 145236141Sraj#elif defined(BOOKE_PPC4XX) 146236141Sraj 147236141Sraj/* TLB Words */ 148236141Sraj#define TLB_PAGEID 0 149236141Sraj#define TLB_XLAT 1 150236141Sraj#define TLB_ATTRIB 2 151236141Sraj 152236141Sraj/* Page identification fields */ 153236141Sraj#define TLB_EPN_MASK (0xFFFFFC00 >> 0) 154236141Sraj#define TLB_VALID (0x80000000 >> 22) 155236141Sraj#define TLB_TS (0x80000000 >> 23) 156236141Sraj#define TLB_SIZE_1K (0x00000000 >> 24) 157236141Sraj#define TLB_SIZE_MASK (0xF0000000 >> 24) 158236141Sraj 159236141Sraj/* Translation fields */ 160236141Sraj#define TLB_RPN_MASK (0xFFFFFC00 >> 0) 161236141Sraj#define TLB_ERPN_MASK (0xF0000000 >> 28) 162236141Sraj 163236141Sraj/* Storage attribute and access control fields */ 164236141Sraj#define TLB_WL1 (0x80000000 >> 11) 165236141Sraj#define TLB_IL1I (0x80000000 >> 12) 166236141Sraj#define TLB_IL1D (0x80000000 >> 13) 167236141Sraj#define TLB_IL2I (0x80000000 >> 14) 168236141Sraj#define TLB_IL2D (0x80000000 >> 15) 169236141Sraj#define TLB_U0 (0x80000000 >> 16) 170236141Sraj#define TLB_U1 (0x80000000 >> 17) 171236141Sraj#define TLB_U2 (0x80000000 >> 18) 172236141Sraj#define TLB_U3 (0x80000000 >> 19) 173236141Sraj#define TLB_W (0x80000000 >> 20) 174236141Sraj#define TLB_I (0x80000000 >> 21) 175236141Sraj#define TLB_M (0x80000000 >> 22) 176236141Sraj#define TLB_G (0x80000000 >> 23) 177236141Sraj#define TLB_E (0x80000000 >> 24) 178236141Sraj#define TLB_UX (0x80000000 >> 26) 179236141Sraj#define TLB_UW (0x80000000 >> 27) 180236141Sraj#define TLB_UR (0x80000000 >> 28) 181236141Sraj#define TLB_SX (0x80000000 >> 29) 182236141Sraj#define TLB_SW (0x80000000 >> 30) 183236141Sraj#define TLB_SR (0x80000000 >> 31) 184236141Sraj#define TLB_SIZE 64 185236141Sraj 186236141Sraj#define TLB_SIZE_4K (0x10000000 >> 24) 187236141Sraj#define TLB_SIZE_16K (0x20000000 >> 24) 188236141Sraj#define TLB_SIZE_64K (0x30000000 >> 24) 189236141Sraj#define TLB_SIZE_256K (0x40000000 >> 24) 190236141Sraj#define TLB_SIZE_1M (0x50000000 >> 24) 191236141Sraj#define TLB_SIZE_16M (0x70000000 >> 24) 192236141Sraj#define TLB_SIZE_256M (0x90000000 >> 24) 193236141Sraj#define TLB_SIZE_1G (0xA0000000 >> 24) 194236141Sraj 195236141Sraj#endif /* BOOKE_E500 */ 196236141Sraj 197187149Sraj#define TID_KERNEL 0 /* TLB TID to use for kernel (shared) translations */ 198176770Sraj#define TID_KRESERVED 1 /* Number of TIDs reserved for kernel */ 199187149Sraj#define TID_URESERVED 0 /* Number of TIDs reserved for user */ 200176770Sraj#define TID_MIN (TID_KRESERVED + TID_URESERVED) 201176770Sraj#define TID_MAX 255 202187149Sraj#define TID_NONE -1 203176770Sraj 204215119Sraj#define TLB_UNLOCKED 0 205215119Sraj 206176770Sraj#if !defined(LOCORE) 207176770Sraj 208187149Srajtypedef int tlbtid_t; 209236141Sraj 210176770Srajstruct pmap; 211176770Sraj 212215119Srajvoid tlb_lock(uint32_t *); 213215119Srajvoid tlb_unlock(uint32_t *); 214215119Sraj 215176770Sraj#endif /* !LOCORE */ 216176770Sraj 217176770Sraj#endif /* _MACHINE_TLB_H_ */ 218