pmap.c revision 184244
1176771Sraj/*- 2176771Sraj * Copyright (C) 2007 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3176771Sraj * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4176771Sraj * All rights reserved. 5176771Sraj * 6176771Sraj * Redistribution and use in source and binary forms, with or without 7176771Sraj * modification, are permitted provided that the following conditions 8176771Sraj * are met: 9176771Sraj * 1. Redistributions of source code must retain the above copyright 10176771Sraj * notice, this list of conditions and the following disclaimer. 11176771Sraj * 2. Redistributions in binary form must reproduce the above copyright 12176771Sraj * notice, this list of conditions and the following disclaimer in the 13176771Sraj * documentation and/or other materials provided with the distribution. 14176771Sraj * 3. The name of the author may not be used to endorse or promote products 15176771Sraj * derived from this software without specific prior written permission. 16176771Sraj * 17176771Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18176771Sraj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19176771Sraj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 20176771Sraj * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21176771Sraj * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 22176771Sraj * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 23176771Sraj * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 24176771Sraj * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 25176771Sraj * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 26176771Sraj * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27176771Sraj * 28176771Sraj * Some hw specific parts of this pmap were derived or influenced 29176771Sraj * by NetBSD's ibm4xx pmap module. More generic code is shared with 30176771Sraj * a few other pmap modules from the FreeBSD tree. 31176771Sraj */ 32176771Sraj 33176771Sraj /* 34176771Sraj * VM layout notes: 35176771Sraj * 36176771Sraj * Kernel and user threads run within one common virtual address space 37176771Sraj * defined by AS=0. 38176771Sraj * 39176771Sraj * Virtual address space layout: 40176771Sraj * ----------------------------- 41176771Sraj * 0x0000_0000 - 0xbfff_efff : user process 42179729Swkoszek * 0xc000_0000 - 0xc1ff_ffff : kernel reserved 43176771Sraj * 0xc000_0000 - kernelend : kernel code &data 44176771Sraj * 0xc1ff_c000 - 0xc200_0000 : kstack0 45176771Sraj * 0xc200_0000 - 0xffef_ffff : KVA 46176771Sraj * 0xc200_0000 - 0xc200_3fff : reserved for page zero/copy 47176771Sraj * 0xc200_4000 - ptbl buf end: reserved for ptbl bufs 48176771Sraj * ptbl buf end- 0xffef_ffff : actual free KVA space 49176771Sraj * 0xfff0_0000 - 0xffff_ffff : I/O devices region 50176771Sraj */ 51176771Sraj 52176771Sraj#include <sys/cdefs.h> 53176771Sraj__FBSDID("$FreeBSD: head/sys/powerpc/booke/pmap.c 184244 2008-10-25 03:36:21Z marcel $"); 54176771Sraj 55176771Sraj#include <sys/types.h> 56176771Sraj#include <sys/param.h> 57176771Sraj#include <sys/malloc.h> 58176771Sraj#include <sys/proc.h> 59176771Sraj#include <sys/user.h> 60176771Sraj#include <sys/queue.h> 61176771Sraj#include <sys/systm.h> 62176771Sraj#include <sys/kernel.h> 63176771Sraj#include <sys/msgbuf.h> 64176771Sraj#include <sys/lock.h> 65176771Sraj#include <sys/mutex.h> 66176771Sraj#include <sys/vmmeter.h> 67176771Sraj 68176771Sraj#include <vm/vm.h> 69176771Sraj#include <vm/vm_page.h> 70176771Sraj#include <vm/vm_kern.h> 71176771Sraj#include <vm/vm_pageout.h> 72176771Sraj#include <vm/vm_extern.h> 73176771Sraj#include <vm/vm_object.h> 74176771Sraj#include <vm/vm_param.h> 75176771Sraj#include <vm/vm_map.h> 76176771Sraj#include <vm/vm_pager.h> 77176771Sraj#include <vm/uma.h> 78176771Sraj 79176771Sraj#include <machine/cpu.h> 80176771Sraj#include <machine/pcb.h> 81176771Sraj#include <machine/powerpc.h> 82176771Sraj 83176771Sraj#include <machine/tlb.h> 84176771Sraj#include <machine/spr.h> 85176771Sraj#include <machine/vmparam.h> 86176771Sraj#include <machine/md_var.h> 87176771Sraj#include <machine/mmuvar.h> 88176771Sraj#include <machine/pmap.h> 89176771Sraj#include <machine/pte.h> 90176771Sraj 91176771Sraj#include "mmu_if.h" 92176771Sraj 93176771Sraj#define DEBUG 94176771Sraj#undef DEBUG 95176771Sraj 96176771Sraj#ifdef DEBUG 97176771Sraj#define debugf(fmt, args...) printf(fmt, ##args) 98176771Sraj#else 99176771Sraj#define debugf(fmt, args...) 100176771Sraj#endif 101176771Sraj 102176771Sraj#define TODO panic("%s: not implemented", __func__); 103176771Sraj#define memmove(d, s, l) bcopy(s, d, l) 104176771Sraj 105176771Sraj#include "opt_sched.h" 106176771Sraj#ifndef SCHED_4BSD 107176771Sraj#error "e500 only works with SCHED_4BSD which uses a global scheduler lock." 108176771Sraj#endif 109176771Srajextern struct mtx sched_lock; 110176771Sraj 111176771Sraj/* Kernel physical load address. */ 112176771Srajextern uint32_t kernload; 113176771Sraj 114176771Srajstruct mem_region availmem_regions[MEM_REGIONS]; 115176771Srajint availmem_regions_sz; 116176771Sraj 117176771Sraj/* Reserved KVA space and mutex for mmu_booke_zero_page. */ 118176771Srajstatic vm_offset_t zero_page_va; 119176771Srajstatic struct mtx zero_page_mutex; 120176771Sraj 121176771Sraj/* 122176771Sraj * Reserved KVA space for mmu_booke_zero_page_idle. This is used 123176771Sraj * by idle thred only, no lock required. 124176771Sraj */ 125176771Srajstatic vm_offset_t zero_page_idle_va; 126176771Sraj 127176771Sraj/* Reserved KVA space and mutex for mmu_booke_copy_page. */ 128176771Srajstatic vm_offset_t copy_page_src_va; 129176771Srajstatic vm_offset_t copy_page_dst_va; 130176771Srajstatic struct mtx copy_page_mutex; 131176771Sraj 132176771Sraj/**************************************************************************/ 133176771Sraj/* PMAP */ 134176771Sraj/**************************************************************************/ 135176771Sraj 136176771Srajstatic void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 137176771Sraj vm_prot_t, boolean_t); 138176771Sraj 139176771Srajunsigned int kptbl_min; /* Index of the first kernel ptbl. */ 140176771Srajunsigned int kernel_ptbls; /* Number of KVA ptbls. */ 141176771Sraj 142176771Srajstatic int pagedaemon_waken; 143176771Sraj 144176771Sraj/* 145176771Sraj * If user pmap is processed with mmu_booke_remove and the resident count 146176771Sraj * drops to 0, there are no more pages to remove, so we need not continue. 147176771Sraj */ 148176771Sraj#define PMAP_REMOVE_DONE(pmap) \ 149176771Sraj ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 150176771Sraj 151176771Srajextern void load_pid0(tlbtid_t); 152176771Sraj 153176771Sraj/**************************************************************************/ 154176771Sraj/* TLB and TID handling */ 155176771Sraj/**************************************************************************/ 156176771Sraj 157176771Sraj/* Translation ID busy table */ 158176771Srajstatic volatile pmap_t tidbusy[TID_MAX + 1]; 159176771Sraj 160176771Sraj/* 161176771Sraj * Actual maximum number of TLB0 entries. 162176771Sraj * This number differs between e500 core revisions. 163176771Sraj */ 164176771Sraju_int32_t tlb0_size; 165176771Sraju_int32_t tlb0_nways; 166176771Sraju_int32_t tlb0_nentries_per_way; 167176771Sraj 168176771Sraj#define TLB0_SIZE (tlb0_size) 169176771Sraj#define TLB0_NWAYS (tlb0_nways) 170176771Sraj#define TLB0_ENTRIES_PER_WAY (tlb0_nentries_per_way) 171176771Sraj 172176771Sraj/* Pointer to kernel tlb0 table, allocated in mmu_booke_bootstrap() */ 173176771Srajtlb_entry_t *tlb0; 174176771Sraj 175176771Sraj/* 176176771Sraj * Spinlock to assure proper locking between threads and 177176771Sraj * between tlb miss handler and kernel. 178176771Sraj */ 179176771Srajstatic struct mtx tlb0_mutex; 180176771Sraj 181176771Sraj#define TLB1_SIZE 16 182176771Sraj 183176771Sraj/* In-ram copy of the TLB1 */ 184176771Srajstatic tlb_entry_t tlb1[TLB1_SIZE]; 185176771Sraj 186176771Sraj/* Next free entry in the TLB1 */ 187176771Srajstatic unsigned int tlb1_idx; 188176771Sraj 189176771Srajstatic tlbtid_t tid_alloc(struct pmap *); 190176771Srajstatic void tid_flush(tlbtid_t); 191176771Sraj 192176771Srajextern void tlb1_inval_va(vm_offset_t); 193176771Srajextern void tlb0_inval_va(vm_offset_t); 194176771Sraj 195176771Srajstatic void tlb_print_entry(int, u_int32_t, u_int32_t, u_int32_t, u_int32_t); 196176771Sraj 197176771Srajstatic int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, u_int32_t); 198176771Srajstatic void __tlb1_set_entry(unsigned int, vm_offset_t, vm_offset_t, 199176771Sraj vm_size_t, u_int32_t, unsigned int, unsigned int); 200176771Srajstatic void tlb1_write_entry(unsigned int); 201176771Srajstatic int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 202176771Srajstatic vm_size_t tlb1_mapin_region(vm_offset_t, vm_offset_t, vm_size_t); 203176771Sraj 204176771Srajstatic vm_size_t tsize2size(unsigned int); 205176771Srajstatic unsigned int size2tsize(vm_size_t); 206176771Srajstatic unsigned int ilog2(unsigned int); 207176771Sraj 208176771Srajstatic void set_mas4_defaults(void); 209176771Sraj 210176771Srajstatic void tlb0_inval_entry(vm_offset_t, unsigned int); 211176771Srajstatic inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 212176771Srajstatic void tlb0_write_entry(unsigned int, unsigned int); 213176771Srajstatic void tlb0_flush_entry(pmap_t, vm_offset_t); 214176771Srajstatic void tlb0_init(void); 215176771Sraj 216176771Sraj/**************************************************************************/ 217176771Sraj/* Page table management */ 218176771Sraj/**************************************************************************/ 219176771Sraj 220176771Sraj/* Data for the pv entry allocation mechanism */ 221176771Srajstatic uma_zone_t pvzone; 222176771Srajstatic struct vm_object pvzone_obj; 223176771Srajstatic int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 224176771Sraj 225176771Sraj#define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 226176771Sraj 227176771Sraj#ifndef PMAP_SHPGPERPROC 228176771Sraj#define PMAP_SHPGPERPROC 200 229176771Sraj#endif 230176771Sraj 231176771Srajstatic void ptbl_init(void); 232176771Srajstatic struct ptbl_buf *ptbl_buf_alloc(void); 233176771Srajstatic void ptbl_buf_free(struct ptbl_buf *); 234176771Srajstatic void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 235176771Sraj 236176771Srajstatic void ptbl_alloc(mmu_t, pmap_t, unsigned int); 237176771Srajstatic void ptbl_free(mmu_t, pmap_t, unsigned int); 238176771Srajstatic void ptbl_hold(mmu_t, pmap_t, unsigned int); 239176771Srajstatic int ptbl_unhold(mmu_t, pmap_t, unsigned int); 240176771Sraj 241176771Srajstatic vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 242176771Srajstatic pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 243176771Srajvoid pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, u_int32_t); 244176771Srajstatic int pte_remove(mmu_t, pmap_t, vm_offset_t, u_int8_t); 245176771Sraj 246176771Srajpv_entry_t pv_alloc(void); 247176771Srajstatic void pv_free(pv_entry_t); 248176771Srajstatic void pv_insert(pmap_t, vm_offset_t, vm_page_t); 249176771Srajstatic void pv_remove(pmap_t, vm_offset_t, vm_page_t); 250176771Sraj 251176771Sraj/* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 252176771Sraj#define PTBL_BUFS (128 * 16) 253176771Sraj 254176771Srajstruct ptbl_buf { 255176771Sraj TAILQ_ENTRY(ptbl_buf) link; /* list link */ 256176771Sraj vm_offset_t kva; /* va of mapping */ 257176771Sraj}; 258176771Sraj 259176771Sraj/* ptbl free list and a lock used for access synchronization. */ 260176771Srajstatic TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 261176771Srajstatic struct mtx ptbl_buf_freelist_lock; 262176771Sraj 263176771Sraj/* Base address of kva space allocated fot ptbl bufs. */ 264176771Srajstatic vm_offset_t ptbl_buf_pool_vabase; 265176771Sraj 266176771Sraj/* Pointer to ptbl_buf structures. */ 267176771Srajstatic struct ptbl_buf *ptbl_bufs; 268176771Sraj 269176771Sraj/* 270176771Sraj * Kernel MMU interface 271176771Sraj */ 272176771Srajstatic void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 273176771Srajstatic void mmu_booke_clear_modify(mmu_t, vm_page_t); 274176771Srajstatic void mmu_booke_clear_reference(mmu_t, vm_page_t); 275176771Srajstatic void mmu_booke_copy(pmap_t, pmap_t, vm_offset_t, vm_size_t, 276176771Sraj vm_offset_t); 277176771Srajstatic void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 278176771Srajstatic void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 279176771Sraj vm_prot_t, boolean_t); 280176771Srajstatic void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 281176771Sraj vm_page_t, vm_prot_t); 282176771Srajstatic void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 283176771Sraj vm_prot_t); 284176771Srajstatic vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 285176771Srajstatic vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 286176771Sraj vm_prot_t); 287176771Srajstatic void mmu_booke_init(mmu_t); 288176771Srajstatic boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 289176771Srajstatic boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 290176771Srajstatic boolean_t mmu_booke_ts_referenced(mmu_t, vm_page_t); 291176771Srajstatic vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, 292176771Sraj int); 293176771Srajstatic int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t); 294176771Srajstatic void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 295176771Sraj vm_object_t, vm_pindex_t, vm_size_t); 296176771Srajstatic boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 297176771Srajstatic void mmu_booke_page_init(mmu_t, vm_page_t); 298176771Srajstatic int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 299176771Srajstatic void mmu_booke_pinit(mmu_t, pmap_t); 300176771Srajstatic void mmu_booke_pinit0(mmu_t, pmap_t); 301176771Srajstatic void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 302176771Sraj vm_prot_t); 303176771Srajstatic void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 304176771Srajstatic void mmu_booke_qremove(mmu_t, vm_offset_t, int); 305176771Srajstatic void mmu_booke_release(mmu_t, pmap_t); 306176771Srajstatic void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 307176771Srajstatic void mmu_booke_remove_all(mmu_t, vm_page_t); 308176771Srajstatic void mmu_booke_remove_write(mmu_t, vm_page_t); 309176771Srajstatic void mmu_booke_zero_page(mmu_t, vm_page_t); 310176771Srajstatic void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 311176771Srajstatic void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 312176771Srajstatic void mmu_booke_activate(mmu_t, struct thread *); 313176771Srajstatic void mmu_booke_deactivate(mmu_t, struct thread *); 314176771Srajstatic void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 315176771Srajstatic void *mmu_booke_mapdev(mmu_t, vm_offset_t, vm_size_t); 316176771Srajstatic void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 317176771Srajstatic vm_offset_t mmu_booke_kextract(mmu_t, vm_offset_t); 318176771Srajstatic void mmu_booke_kenter(mmu_t, vm_offset_t, vm_offset_t); 319176771Srajstatic void mmu_booke_kremove(mmu_t, vm_offset_t); 320176771Srajstatic boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 321176771Srajstatic boolean_t mmu_booke_page_executable(mmu_t, vm_page_t); 322176771Sraj 323176771Srajstatic mmu_method_t mmu_booke_methods[] = { 324176771Sraj /* pmap dispatcher interface */ 325176771Sraj MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring), 326176771Sraj MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 327176771Sraj MMUMETHOD(mmu_clear_reference, mmu_booke_clear_reference), 328176771Sraj MMUMETHOD(mmu_copy, mmu_booke_copy), 329176771Sraj MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 330176771Sraj MMUMETHOD(mmu_enter, mmu_booke_enter), 331176771Sraj MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 332176771Sraj MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 333176771Sraj MMUMETHOD(mmu_extract, mmu_booke_extract), 334176771Sraj MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 335176771Sraj MMUMETHOD(mmu_init, mmu_booke_init), 336176771Sraj MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 337176771Sraj MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 338176771Sraj MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 339176771Sraj MMUMETHOD(mmu_map, mmu_booke_map), 340176771Sraj MMUMETHOD(mmu_mincore, mmu_booke_mincore), 341176771Sraj MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 342176771Sraj MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 343176771Sraj MMUMETHOD(mmu_page_init, mmu_booke_page_init), 344176771Sraj MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 345176771Sraj MMUMETHOD(mmu_pinit, mmu_booke_pinit), 346176771Sraj MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 347176771Sraj MMUMETHOD(mmu_protect, mmu_booke_protect), 348176771Sraj MMUMETHOD(mmu_qenter, mmu_booke_qenter), 349176771Sraj MMUMETHOD(mmu_qremove, mmu_booke_qremove), 350176771Sraj MMUMETHOD(mmu_release, mmu_booke_release), 351176771Sraj MMUMETHOD(mmu_remove, mmu_booke_remove), 352176771Sraj MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 353176771Sraj MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 354176771Sraj MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 355176771Sraj MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 356176771Sraj MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 357176771Sraj MMUMETHOD(mmu_activate, mmu_booke_activate), 358176771Sraj MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 359176771Sraj 360176771Sraj /* Internal interfaces */ 361176771Sraj MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 362176771Sraj MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 363176771Sraj MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 364176771Sraj MMUMETHOD(mmu_kenter, mmu_booke_kenter), 365176771Sraj MMUMETHOD(mmu_kextract, mmu_booke_kextract), 366176771Sraj/* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 367176771Sraj MMUMETHOD(mmu_page_executable, mmu_booke_page_executable), 368176771Sraj MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 369176771Sraj 370176771Sraj { 0, 0 } 371176771Sraj}; 372176771Sraj 373176771Srajstatic mmu_def_t booke_mmu = { 374176771Sraj MMU_TYPE_BOOKE, 375176771Sraj mmu_booke_methods, 376176771Sraj 0 377176771Sraj}; 378176771SrajMMU_DEF(booke_mmu); 379176771Sraj 380176771Sraj/* Return number of entries in TLB0. */ 381176771Srajstatic __inline void 382176771Srajtlb0_get_tlbconf(void) 383176771Sraj{ 384176771Sraj uint32_t tlb0_cfg; 385176771Sraj 386176771Sraj tlb0_cfg = mfspr(SPR_TLB0CFG); 387176771Sraj tlb0_size = tlb0_cfg & TLBCFG_NENTRY_MASK; 388176771Sraj tlb0_nways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 389176771Sraj tlb0_nentries_per_way = tlb0_size/tlb0_nways; 390176771Sraj} 391176771Sraj 392176771Sraj/* Initialize pool of kva ptbl buffers. */ 393176771Srajstatic void 394176771Srajptbl_init(void) 395176771Sraj{ 396176771Sraj int i; 397176771Sraj 398176771Sraj //debugf("ptbl_init: s (ptbl_bufs = 0x%08x size 0x%08x)\n", 399176771Sraj // (u_int32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 400176771Sraj //debugf("ptbl_init: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)\n", 401176771Sraj // ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 402176771Sraj 403176771Sraj mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 404176771Sraj TAILQ_INIT(&ptbl_buf_freelist); 405176771Sraj 406176771Sraj for (i = 0; i < PTBL_BUFS; i++) { 407176771Sraj ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 408176771Sraj TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 409176771Sraj } 410176771Sraj 411176771Sraj //debugf("ptbl_init: e\n"); 412176771Sraj} 413176771Sraj 414182362Sraj/* Get a ptbl_buf from the freelist. */ 415176771Srajstatic struct ptbl_buf * 416176771Srajptbl_buf_alloc(void) 417176771Sraj{ 418176771Sraj struct ptbl_buf *buf; 419176771Sraj 420176771Sraj //debugf("ptbl_buf_alloc: s\n"); 421176771Sraj 422176771Sraj mtx_lock(&ptbl_buf_freelist_lock); 423176771Sraj buf = TAILQ_FIRST(&ptbl_buf_freelist); 424176771Sraj if (buf != NULL) 425176771Sraj TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 426176771Sraj mtx_unlock(&ptbl_buf_freelist_lock); 427176771Sraj 428176771Sraj //debugf("ptbl_buf_alloc: e (buf = 0x%08x)\n", (u_int32_t)buf); 429176771Sraj return (buf); 430176771Sraj} 431176771Sraj 432176771Sraj/* Return ptbl buff to free pool. */ 433176771Srajstatic void 434176771Srajptbl_buf_free(struct ptbl_buf *buf) 435176771Sraj{ 436176771Sraj 437176771Sraj //debugf("ptbl_buf_free: s (buf = 0x%08x)\n", (u_int32_t)buf); 438176771Sraj 439176771Sraj mtx_lock(&ptbl_buf_freelist_lock); 440176771Sraj TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 441176771Sraj mtx_unlock(&ptbl_buf_freelist_lock); 442176771Sraj 443176771Sraj //debugf("ptbl_buf_free: e\n"); 444176771Sraj} 445176771Sraj 446176771Sraj/* 447176771Sraj * Search the list of allocated ptbl bufs and find 448176771Sraj * on list of allocated ptbls 449176771Sraj */ 450176771Srajstatic void 451176771Srajptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 452176771Sraj{ 453176771Sraj struct ptbl_buf *pbuf; 454176771Sraj 455176771Sraj //debugf("ptbl_free_pmap_ptbl: s (pmap = 0x%08x ptbl = 0x%08x)\n", 456176771Sraj // (u_int32_t)pmap, (u_int32_t)ptbl); 457176771Sraj 458176771Sraj TAILQ_FOREACH(pbuf, &pmap->ptbl_list, link) { 459176771Sraj if (pbuf->kva == (vm_offset_t)ptbl) { 460176771Sraj /* Remove from pmap ptbl buf list. */ 461176771Sraj TAILQ_REMOVE(&pmap->ptbl_list, pbuf, link); 462176771Sraj 463176771Sraj /* Free correspondig ptbl buf. */ 464176771Sraj ptbl_buf_free(pbuf); 465176771Sraj 466176771Sraj break; 467176771Sraj } 468176771Sraj } 469176771Sraj 470176771Sraj //debugf("ptbl_free_pmap_ptbl: e\n"); 471176771Sraj} 472176771Sraj 473176771Sraj/* Allocate page table. */ 474176771Srajstatic void 475176771Srajptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 476176771Sraj{ 477176771Sraj vm_page_t mtbl[PTBL_PAGES]; 478176771Sraj vm_page_t m; 479176771Sraj struct ptbl_buf *pbuf; 480176771Sraj unsigned int pidx; 481176771Sraj int i; 482176771Sraj 483176771Sraj //int su = (pmap == kernel_pmap); 484176771Sraj //debugf("ptbl_alloc: s (pmap = 0x%08x su = %d pdir_idx = %d)\n", (u_int32_t)pmap, su, pdir_idx); 485176771Sraj 486176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 487176771Sraj ("ptbl_alloc: invalid pdir_idx")); 488176771Sraj KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 489176771Sraj ("pte_alloc: valid ptbl entry exists!")); 490176771Sraj 491176771Sraj pbuf = ptbl_buf_alloc(); 492176771Sraj if (pbuf == NULL) 493176771Sraj panic("pte_alloc: couldn't alloc kernel virtual memory"); 494176771Sraj pmap->pm_pdir[pdir_idx] = (pte_t *)pbuf->kva; 495176771Sraj //debugf("ptbl_alloc: kva = 0x%08x\n", (u_int32_t)pmap->pm_pdir[pdir_idx]); 496176771Sraj 497176771Sraj /* Allocate ptbl pages, this will sleep! */ 498176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 499176771Sraj pidx = (PTBL_PAGES * pdir_idx) + i; 500176771Sraj while ((m = vm_page_alloc(NULL, pidx, VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 501176771Sraj PMAP_UNLOCK(pmap); 502176771Sraj vm_page_unlock_queues(); 503176771Sraj VM_WAIT; 504176771Sraj vm_page_lock_queues(); 505176771Sraj PMAP_LOCK(pmap); 506176771Sraj } 507176771Sraj mtbl[i] = m; 508176771Sraj } 509176771Sraj 510176771Sraj /* Map in allocated pages into kernel_pmap. */ 511176771Sraj mmu_booke_qenter(mmu, (vm_offset_t)pmap->pm_pdir[pdir_idx], mtbl, PTBL_PAGES); 512176771Sraj 513176771Sraj /* Zero whole ptbl. */ 514176771Sraj bzero((caddr_t)pmap->pm_pdir[pdir_idx], PTBL_PAGES * PAGE_SIZE); 515176771Sraj 516176771Sraj /* Add pbuf to the pmap ptbl bufs list. */ 517176771Sraj TAILQ_INSERT_TAIL(&pmap->ptbl_list, pbuf, link); 518176771Sraj 519176771Sraj //debugf("ptbl_alloc: e\n"); 520176771Sraj} 521176771Sraj 522176771Sraj/* Free ptbl pages and invalidate pdir entry. */ 523176771Srajstatic void 524176771Srajptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 525176771Sraj{ 526176771Sraj pte_t *ptbl; 527176771Sraj vm_paddr_t pa; 528176771Sraj vm_offset_t va; 529176771Sraj vm_page_t m; 530176771Sraj int i; 531176771Sraj 532176771Sraj //int su = (pmap == kernel_pmap); 533176771Sraj //debugf("ptbl_free: s (pmap = 0x%08x su = %d pdir_idx = %d)\n", (u_int32_t)pmap, su, pdir_idx); 534176771Sraj 535176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 536176771Sraj ("ptbl_free: invalid pdir_idx")); 537176771Sraj 538176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 539176771Sraj 540176771Sraj //debugf("ptbl_free: ptbl = 0x%08x\n", (u_int32_t)ptbl); 541176771Sraj KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 542176771Sraj 543176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 544176771Sraj va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 545176771Sraj pa = pte_vatopa(mmu, kernel_pmap, va); 546176771Sraj m = PHYS_TO_VM_PAGE(pa); 547176771Sraj vm_page_free_zero(m); 548176771Sraj atomic_subtract_int(&cnt.v_wire_count, 1); 549176771Sraj mmu_booke_kremove(mmu, va); 550176771Sraj } 551176771Sraj 552176771Sraj ptbl_free_pmap_ptbl(pmap, ptbl); 553176771Sraj pmap->pm_pdir[pdir_idx] = NULL; 554176771Sraj 555176771Sraj //debugf("ptbl_free: e\n"); 556176771Sraj} 557176771Sraj 558176771Sraj/* 559176771Sraj * Decrement ptbl pages hold count and attempt to free ptbl pages. 560176771Sraj * Called when removing pte entry from ptbl. 561176771Sraj * 562176771Sraj * Return 1 if ptbl pages were freed. 563176771Sraj */ 564176771Srajstatic int 565176771Srajptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 566176771Sraj{ 567176771Sraj pte_t *ptbl; 568176771Sraj vm_paddr_t pa; 569176771Sraj vm_page_t m; 570176771Sraj int i; 571176771Sraj 572176771Sraj //int su = (pmap == kernel_pmap); 573176771Sraj //debugf("ptbl_unhold: s (pmap = %08x su = %d pdir_idx = %d)\n", 574176771Sraj // (u_int32_t)pmap, su, pdir_idx); 575176771Sraj 576176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 577176771Sraj ("ptbl_unhold: invalid pdir_idx")); 578176771Sraj KASSERT((pmap != kernel_pmap), 579176771Sraj ("ptbl_unhold: unholding kernel ptbl!")); 580176771Sraj 581176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 582176771Sraj 583176771Sraj //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 584176771Sraj KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 585176771Sraj ("ptbl_unhold: non kva ptbl")); 586176771Sraj 587176771Sraj /* decrement hold count */ 588176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 589176771Sraj pa = pte_vatopa(mmu, kernel_pmap, (vm_offset_t)ptbl + (i * PAGE_SIZE)); 590176771Sraj m = PHYS_TO_VM_PAGE(pa); 591176771Sraj m->wire_count--; 592176771Sraj } 593176771Sraj 594176771Sraj /* 595176771Sraj * Free ptbl pages if there are no pte etries in this ptbl. 596176771Sraj * wire_count has the same value for all ptbl pages, so check 597176771Sraj * the last page. 598176771Sraj */ 599176771Sraj if (m->wire_count == 0) { 600176771Sraj ptbl_free(mmu, pmap, pdir_idx); 601176771Sraj 602176771Sraj //debugf("ptbl_unhold: e (freed ptbl)\n"); 603176771Sraj return (1); 604176771Sraj } 605176771Sraj 606176771Sraj //debugf("ptbl_unhold: e\n"); 607176771Sraj return (0); 608176771Sraj} 609176771Sraj 610176771Sraj/* 611176771Sraj * Increment hold count for ptbl pages. This routine is used when 612176771Sraj * new pte entry is being inserted into ptbl. 613176771Sraj */ 614176771Srajstatic void 615176771Srajptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 616176771Sraj{ 617176771Sraj vm_paddr_t pa; 618176771Sraj pte_t *ptbl; 619176771Sraj vm_page_t m; 620176771Sraj int i; 621176771Sraj 622176771Sraj //debugf("ptbl_hold: s (pmap = 0x%08x pdir_idx = %d)\n", (u_int32_t)pmap, pdir_idx); 623176771Sraj 624176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 625176771Sraj ("ptbl_hold: invalid pdir_idx")); 626176771Sraj KASSERT((pmap != kernel_pmap), 627176771Sraj ("ptbl_hold: holding kernel ptbl!")); 628176771Sraj 629176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 630176771Sraj 631176771Sraj KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 632176771Sraj 633176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 634176771Sraj pa = pte_vatopa(mmu, kernel_pmap, (vm_offset_t)ptbl + (i * PAGE_SIZE)); 635176771Sraj m = PHYS_TO_VM_PAGE(pa); 636176771Sraj m->wire_count++; 637176771Sraj } 638176771Sraj 639176771Sraj //debugf("ptbl_hold: e\n"); 640176771Sraj} 641176771Sraj 642176771Sraj/* Allocate pv_entry structure. */ 643176771Srajpv_entry_t 644176771Srajpv_alloc(void) 645176771Sraj{ 646176771Sraj pv_entry_t pv; 647176771Sraj 648176771Sraj debugf("pv_alloc: s\n"); 649176771Sraj 650176771Sraj pv_entry_count++; 651176771Sraj if ((pv_entry_count > pv_entry_high_water) && (pagedaemon_waken == 0)) { 652176771Sraj pagedaemon_waken = 1; 653176771Sraj wakeup (&vm_pages_needed); 654176771Sraj } 655176771Sraj pv = uma_zalloc(pvzone, M_NOWAIT); 656176771Sraj 657176771Sraj debugf("pv_alloc: e\n"); 658176771Sraj return (pv); 659176771Sraj} 660176771Sraj 661176771Sraj/* Free pv_entry structure. */ 662176771Srajstatic __inline void 663176771Srajpv_free(pv_entry_t pve) 664176771Sraj{ 665176771Sraj //debugf("pv_free: s\n"); 666176771Sraj 667176771Sraj pv_entry_count--; 668176771Sraj uma_zfree(pvzone, pve); 669176771Sraj 670176771Sraj //debugf("pv_free: e\n"); 671176771Sraj} 672176771Sraj 673176771Sraj 674176771Sraj/* Allocate and initialize pv_entry structure. */ 675176771Srajstatic void 676176771Srajpv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 677176771Sraj{ 678176771Sraj pv_entry_t pve; 679176771Sraj 680176771Sraj //int su = (pmap == kernel_pmap); 681176771Sraj //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 682176771Sraj // (u_int32_t)pmap, va, (u_int32_t)m); 683176771Sraj 684176771Sraj pve = pv_alloc(); 685176771Sraj if (pve == NULL) 686176771Sraj panic("pv_insert: no pv entries!"); 687176771Sraj 688176771Sraj pve->pv_pmap = pmap; 689176771Sraj pve->pv_va = va; 690176771Sraj 691176771Sraj /* add to pv_list */ 692176771Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 693176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 694176771Sraj 695176771Sraj TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 696176771Sraj 697176771Sraj //debugf("pv_insert: e\n"); 698176771Sraj} 699176771Sraj 700176771Sraj/* Destroy pv entry. */ 701176771Srajstatic void 702176771Srajpv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 703176771Sraj{ 704176771Sraj pv_entry_t pve; 705176771Sraj 706176771Sraj //int su = (pmap == kernel_pmap); 707176771Sraj //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 708176771Sraj 709176771Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 710176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 711176771Sraj 712176771Sraj /* find pv entry */ 713176771Sraj TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 714176771Sraj if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 715176771Sraj /* remove from pv_list */ 716176771Sraj TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 717176771Sraj if (TAILQ_EMPTY(&m->md.pv_list)) 718176771Sraj vm_page_flag_clear(m, PG_WRITEABLE); 719176771Sraj 720176771Sraj /* free pv entry struct */ 721176771Sraj pv_free(pve); 722176771Sraj 723176771Sraj break; 724176771Sraj } 725176771Sraj } 726176771Sraj 727176771Sraj //debugf("pv_remove: e\n"); 728176771Sraj} 729176771Sraj 730176771Sraj/* 731176771Sraj * Clean pte entry, try to free page table page if requested. 732176771Sraj * 733176771Sraj * Return 1 if ptbl pages were freed, otherwise return 0. 734176771Sraj */ 735176771Srajstatic int 736176771Srajpte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, u_int8_t flags) 737176771Sraj{ 738176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 739176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 740176771Sraj vm_page_t m; 741176771Sraj pte_t *ptbl; 742176771Sraj pte_t *pte; 743176771Sraj 744176771Sraj //int su = (pmap == kernel_pmap); 745176771Sraj //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 746176771Sraj // su, (u_int32_t)pmap, va, flags); 747176771Sraj 748176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 749176771Sraj KASSERT(ptbl, ("pte_remove: null ptbl")); 750176771Sraj 751176771Sraj pte = &ptbl[ptbl_idx]; 752176771Sraj 753176771Sraj if (pte == NULL || !PTE_ISVALID(pte)) 754176771Sraj return (0); 755176771Sraj 756176771Sraj /* Get vm_page_t for mapped pte. */ 757176771Sraj m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 758176771Sraj 759176771Sraj if (PTE_ISWIRED(pte)) 760176771Sraj pmap->pm_stats.wired_count--; 761176771Sraj 762176771Sraj if (!PTE_ISFAKE(pte)) { 763176771Sraj /* Handle managed entry. */ 764176771Sraj if (PTE_ISMANAGED(pte)) { 765176771Sraj 766176771Sraj /* Handle modified pages. */ 767178626Smarcel if (PTE_ISMODIFIED(pte)) 768178626Smarcel vm_page_dirty(m); 769176771Sraj 770176771Sraj /* Referenced pages. */ 771176771Sraj if (PTE_ISREFERENCED(pte)) 772176771Sraj vm_page_flag_set(m, PG_REFERENCED); 773176771Sraj 774176771Sraj /* Remove pv_entry from pv_list. */ 775176771Sraj pv_remove(pmap, va, m); 776176771Sraj } 777176771Sraj } 778176771Sraj 779176771Sraj pte->flags = 0; 780176771Sraj pte->rpn = 0; 781176771Sraj pmap->pm_stats.resident_count--; 782176771Sraj 783176771Sraj if (flags & PTBL_UNHOLD) { 784176771Sraj //debugf("pte_remove: e (unhold)\n"); 785176771Sraj return (ptbl_unhold(mmu, pmap, pdir_idx)); 786176771Sraj } 787176771Sraj 788176771Sraj //debugf("pte_remove: e\n"); 789176771Sraj return (0); 790176771Sraj} 791176771Sraj 792176771Sraj/* 793176771Sraj * Insert PTE for a given page and virtual address. 794176771Sraj */ 795176771Srajvoid 796176771Srajpte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, u_int32_t flags) 797176771Sraj{ 798176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 799176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 800176771Sraj pte_t *ptbl; 801176771Sraj pte_t *pte; 802176771Sraj 803176771Sraj //int su = (pmap == kernel_pmap); 804176771Sraj //debugf("pte_enter: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 805176771Sraj 806176771Sraj /* Get the page table pointer. */ 807176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 808176771Sraj 809176771Sraj if (ptbl) { 810176771Sraj /* 811176771Sraj * Check if there is valid mapping for requested 812176771Sraj * va, if there is, remove it. 813176771Sraj */ 814176771Sraj pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 815176771Sraj if (PTE_ISVALID(pte)) { 816176771Sraj pte_remove(mmu, pmap, va, PTBL_HOLD); 817176771Sraj } else { 818176771Sraj /* 819176771Sraj * pte is not used, increment hold count 820176771Sraj * for ptbl pages. 821176771Sraj */ 822176771Sraj if (pmap != kernel_pmap) 823176771Sraj ptbl_hold(mmu, pmap, pdir_idx); 824176771Sraj } 825176771Sraj } else { 826176771Sraj /* Allocate page table pages. */ 827176771Sraj ptbl_alloc(mmu, pmap, pdir_idx); 828176771Sraj } 829176771Sraj 830176771Sraj /* Flush entry from TLB. */ 831176771Sraj tlb0_flush_entry(pmap, va); 832176771Sraj 833176771Sraj pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 834176771Sraj 835176771Sraj /* 836176771Sraj * Insert pv_entry into pv_list for mapped page 837176771Sraj * if part of managed memory. 838176771Sraj */ 839176771Sraj if ((m->flags & PG_FICTITIOUS) == 0) { 840176771Sraj if ((m->flags & PG_UNMANAGED) == 0) { 841176771Sraj pte->flags |= PTE_MANAGED; 842176771Sraj 843176771Sraj /* Create and insert pv entry. */ 844176771Sraj pv_insert(pmap, va, m); 845176771Sraj } 846176771Sraj } else { 847176771Sraj pte->flags |= PTE_FAKE; 848176771Sraj } 849176771Sraj 850176771Sraj pmap->pm_stats.resident_count++; 851176771Sraj pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 852176771Sraj pte->flags |= (PTE_VALID | flags); 853176771Sraj 854176771Sraj //debugf("pte_enter: e\n"); 855176771Sraj} 856176771Sraj 857176771Sraj/* Return the pa for the given pmap/va. */ 858176771Srajstatic vm_paddr_t 859176771Srajpte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 860176771Sraj{ 861176771Sraj vm_paddr_t pa = 0; 862176771Sraj pte_t *pte; 863176771Sraj 864176771Sraj pte = pte_find(mmu, pmap, va); 865176771Sraj if ((pte != NULL) && PTE_ISVALID(pte)) 866176771Sraj pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 867176771Sraj return (pa); 868176771Sraj} 869176771Sraj 870176771Sraj/* Get a pointer to a PTE in a page table. */ 871176771Srajstatic pte_t * 872176771Srajpte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 873176771Sraj{ 874176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 875176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 876176771Sraj 877176771Sraj KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 878176771Sraj 879176771Sraj if (pmap->pm_pdir[pdir_idx]) 880176771Sraj return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 881176771Sraj 882176771Sraj return (NULL); 883176771Sraj} 884176771Sraj 885176771Sraj/**************************************************************************/ 886176771Sraj/* PMAP related */ 887176771Sraj/**************************************************************************/ 888176771Sraj 889176771Sraj/* 890176771Sraj * This is called during e500_init, before the system is really initialized. 891176771Sraj */ 892176771Srajstatic void 893176771Srajmmu_booke_bootstrap(mmu_t mmu, vm_offset_t kernelstart, vm_offset_t kernelend) 894176771Sraj{ 895176771Sraj vm_offset_t phys_kernelend; 896176771Sraj struct mem_region *mp, *mp1; 897176771Sraj int cnt, i, j; 898176771Sraj u_int s, e, sz; 899176771Sraj u_int phys_avail_count; 900182198Sraj vm_size_t physsz, hwphyssz, kstack0_sz; 901182198Sraj vm_offset_t kernel_pdir, kstack0; 902182198Sraj vm_paddr_t kstack0_phys; 903176771Sraj 904176771Sraj debugf("mmu_booke_bootstrap: entered\n"); 905176771Sraj 906176771Sraj /* Align kernel start and end address (kernel image). */ 907176771Sraj kernelstart = trunc_page(kernelstart); 908176771Sraj kernelend = round_page(kernelend); 909176771Sraj 910176771Sraj /* Allocate space for the message buffer. */ 911176771Sraj msgbufp = (struct msgbuf *)kernelend; 912176771Sraj kernelend += MSGBUF_SIZE; 913176771Sraj debugf(" msgbufp at 0x%08x end = 0x%08x\n", (u_int32_t)msgbufp, 914176771Sraj kernelend); 915176771Sraj 916176771Sraj kernelend = round_page(kernelend); 917176771Sraj 918176771Sraj /* Allocate space for tlb0 table. */ 919176771Sraj tlb0_get_tlbconf(); /* Read TLB0 size and associativity. */ 920176771Sraj tlb0 = (tlb_entry_t *)kernelend; 921176771Sraj kernelend += sizeof(tlb_entry_t) * tlb0_size; 922176771Sraj debugf(" tlb0 at 0x%08x end = 0x%08x\n", (u_int32_t)tlb0, kernelend); 923176771Sraj 924176771Sraj kernelend = round_page(kernelend); 925176771Sraj 926176771Sraj /* Allocate space for ptbl_bufs. */ 927176771Sraj ptbl_bufs = (struct ptbl_buf *)kernelend; 928176771Sraj kernelend += sizeof(struct ptbl_buf) * PTBL_BUFS; 929176771Sraj debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (u_int32_t)ptbl_bufs, 930176771Sraj kernelend); 931176771Sraj 932176771Sraj kernelend = round_page(kernelend); 933176771Sraj 934176771Sraj /* Allocate PTE tables for kernel KVA. */ 935176771Sraj kernel_pdir = kernelend; 936176771Sraj kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 937176771Sraj PDIR_SIZE - 1) / PDIR_SIZE; 938176771Sraj kernelend += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 939176771Sraj debugf(" kernel ptbls: %d\n", kernel_ptbls); 940176771Sraj debugf(" kernel pdir at 0x%08x\n", kernel_pdir); 941176771Sraj 942176771Sraj if (kernelend - kernelstart > 0x1000000) { 943176771Sraj kernelend = (kernelend + 0x3fffff) & ~0x3fffff; 944176771Sraj tlb1_mapin_region(kernelstart + 0x1000000, 945176771Sraj kernload + 0x1000000, kernelend - kernelstart - 0x1000000); 946176771Sraj } else 947176771Sraj kernelend = (kernelend + 0xffffff) & ~0xffffff; 948176771Sraj 949182362Sraj /* 950182362Sraj * Clear the structures - note we can only do it safely after the 951182362Sraj * possible additional TLB1 translations are in place so that 952182362Sraj * all range up to the currently calculated 'kernelend' is covered. 953182362Sraj */ 954182362Sraj memset((void *)tlb0, 0, sizeof(tlb_entry_t) * tlb0_size); 955182362Sraj memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 956182362Sraj memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 957182362Sraj 958176771Sraj /*******************************************************/ 959176771Sraj /* Set the start and end of kva. */ 960176771Sraj /*******************************************************/ 961176771Sraj virtual_avail = kernelend; 962176771Sraj virtual_end = VM_MAX_KERNEL_ADDRESS; 963176771Sraj 964176771Sraj /* Allocate KVA space for page zero/copy operations. */ 965176771Sraj zero_page_va = virtual_avail; 966176771Sraj virtual_avail += PAGE_SIZE; 967176771Sraj zero_page_idle_va = virtual_avail; 968176771Sraj virtual_avail += PAGE_SIZE; 969176771Sraj copy_page_src_va = virtual_avail; 970176771Sraj virtual_avail += PAGE_SIZE; 971176771Sraj copy_page_dst_va = virtual_avail; 972176771Sraj virtual_avail += PAGE_SIZE; 973176771Sraj 974176771Sraj /* Initialize page zero/copy mutexes. */ 975176771Sraj mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 976176771Sraj mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 977176771Sraj 978176771Sraj /* Initialize tlb0 table mutex. */ 979176771Sraj mtx_init(&tlb0_mutex, "tlb0", NULL, MTX_SPIN | MTX_RECURSE); 980176771Sraj 981176771Sraj /* Allocate KVA space for ptbl bufs. */ 982176771Sraj ptbl_buf_pool_vabase = virtual_avail; 983176771Sraj virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 984176771Sraj 985176771Sraj debugf("ptbl_buf_pool_vabase = 0x%08x\n", ptbl_buf_pool_vabase); 986176771Sraj debugf("virtual_avail = %08x\n", virtual_avail); 987176771Sraj debugf("virtual_end = %08x\n", virtual_end); 988176771Sraj 989176771Sraj /* Calculate corresponding physical addresses for the kernel region. */ 990176771Sraj phys_kernelend = kernload + (kernelend - kernelstart); 991176771Sraj 992176771Sraj debugf("kernel image and allocated data:\n"); 993176771Sraj debugf(" kernload = 0x%08x\n", kernload); 994176771Sraj debugf(" kernelstart = 0x%08x\n", kernelstart); 995176771Sraj debugf(" kernelend = 0x%08x\n", kernelend); 996176771Sraj debugf(" kernel size = 0x%08x\n", kernelend - kernelstart); 997176771Sraj 998176771Sraj if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 999176771Sraj panic("mmu_booke_bootstrap: phys_avail too small"); 1000176771Sraj 1001176771Sraj /* 1002176771Sraj * Removed kernel physical address range from avail 1003176771Sraj * regions list. Page align all regions. 1004176771Sraj * Non-page aligned memory isn't very interesting to us. 1005176771Sraj * Also, sort the entries for ascending addresses. 1006176771Sraj */ 1007176771Sraj sz = 0; 1008176771Sraj cnt = availmem_regions_sz; 1009176771Sraj debugf("processing avail regions:\n"); 1010176771Sraj for (mp = availmem_regions; mp->mr_size; mp++) { 1011176771Sraj s = mp->mr_start; 1012176771Sraj e = mp->mr_start + mp->mr_size; 1013176771Sraj debugf(" %08x-%08x -> ", s, e); 1014176771Sraj /* Check whether this region holds all of the kernel. */ 1015176771Sraj if (s < kernload && e > phys_kernelend) { 1016176771Sraj availmem_regions[cnt].mr_start = phys_kernelend; 1017176771Sraj availmem_regions[cnt++].mr_size = e - phys_kernelend; 1018176771Sraj e = kernload; 1019176771Sraj } 1020176771Sraj /* Look whether this regions starts within the kernel. */ 1021176771Sraj if (s >= kernload && s < phys_kernelend) { 1022176771Sraj if (e <= phys_kernelend) 1023176771Sraj goto empty; 1024176771Sraj s = phys_kernelend; 1025176771Sraj } 1026176771Sraj /* Now look whether this region ends within the kernel. */ 1027176771Sraj if (e > kernload && e <= phys_kernelend) { 1028176771Sraj if (s >= kernload) 1029176771Sraj goto empty; 1030176771Sraj e = kernload; 1031176771Sraj } 1032176771Sraj /* Now page align the start and size of the region. */ 1033176771Sraj s = round_page(s); 1034176771Sraj e = trunc_page(e); 1035176771Sraj if (e < s) 1036176771Sraj e = s; 1037176771Sraj sz = e - s; 1038176771Sraj debugf("%08x-%08x = %x\n", s, e, sz); 1039176771Sraj 1040176771Sraj /* Check whether some memory is left here. */ 1041176771Sraj if (sz == 0) { 1042176771Sraj empty: 1043176771Sraj memmove(mp, mp + 1, 1044176771Sraj (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1045176771Sraj cnt--; 1046176771Sraj mp--; 1047176771Sraj continue; 1048176771Sraj } 1049176771Sraj 1050176771Sraj /* Do an insertion sort. */ 1051176771Sraj for (mp1 = availmem_regions; mp1 < mp; mp1++) 1052176771Sraj if (s < mp1->mr_start) 1053176771Sraj break; 1054176771Sraj if (mp1 < mp) { 1055176771Sraj memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1056176771Sraj mp1->mr_start = s; 1057176771Sraj mp1->mr_size = sz; 1058176771Sraj } else { 1059176771Sraj mp->mr_start = s; 1060176771Sraj mp->mr_size = sz; 1061176771Sraj } 1062176771Sraj } 1063176771Sraj availmem_regions_sz = cnt; 1064176771Sraj 1065176771Sraj /*******************************************************/ 1066182198Sraj /* Steal physical memory for kernel stack from the end */ 1067182198Sraj /* of the first avail region */ 1068182198Sraj /*******************************************************/ 1069182198Sraj kstack0_sz = KSTACK_PAGES * PAGE_SIZE; 1070182198Sraj kstack0_phys = availmem_regions[0].mr_start + 1071182198Sraj availmem_regions[0].mr_size; 1072182198Sraj kstack0_phys -= kstack0_sz; 1073182198Sraj availmem_regions[0].mr_size -= kstack0_sz; 1074182198Sraj 1075182198Sraj /*******************************************************/ 1076176771Sraj /* Fill in phys_avail table, based on availmem_regions */ 1077176771Sraj /*******************************************************/ 1078176771Sraj phys_avail_count = 0; 1079176771Sraj physsz = 0; 1080176771Sraj hwphyssz = 0; 1081176771Sraj TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1082176771Sraj 1083176771Sraj debugf("fill in phys_avail:\n"); 1084176771Sraj for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1085176771Sraj 1086176771Sraj debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1087176771Sraj availmem_regions[i].mr_start, 1088176771Sraj availmem_regions[i].mr_start + availmem_regions[i].mr_size, 1089176771Sraj availmem_regions[i].mr_size); 1090176771Sraj 1091182362Sraj if (hwphyssz != 0 && 1092182362Sraj (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1093176771Sraj debugf(" hw.physmem adjust\n"); 1094176771Sraj if (physsz < hwphyssz) { 1095176771Sraj phys_avail[j] = availmem_regions[i].mr_start; 1096182362Sraj phys_avail[j + 1] = 1097182362Sraj availmem_regions[i].mr_start + 1098176771Sraj hwphyssz - physsz; 1099176771Sraj physsz = hwphyssz; 1100176771Sraj phys_avail_count++; 1101176771Sraj } 1102176771Sraj break; 1103176771Sraj } 1104176771Sraj 1105176771Sraj phys_avail[j] = availmem_regions[i].mr_start; 1106176771Sraj phys_avail[j + 1] = availmem_regions[i].mr_start + 1107176771Sraj availmem_regions[i].mr_size; 1108176771Sraj phys_avail_count++; 1109176771Sraj physsz += availmem_regions[i].mr_size; 1110176771Sraj } 1111176771Sraj physmem = btoc(physsz); 1112176771Sraj 1113176771Sraj /* Calculate the last available physical address. */ 1114176771Sraj for (i = 0; phys_avail[i + 2] != 0; i += 2) 1115176771Sraj ; 1116176771Sraj Maxmem = powerpc_btop(phys_avail[i + 1]); 1117176771Sraj 1118176771Sraj debugf("Maxmem = 0x%08lx\n", Maxmem); 1119176771Sraj debugf("phys_avail_count = %d\n", phys_avail_count); 1120176771Sraj debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, physmem); 1121176771Sraj 1122176771Sraj /*******************************************************/ 1123176771Sraj /* Initialize (statically allocated) kernel pmap. */ 1124176771Sraj /*******************************************************/ 1125176771Sraj PMAP_LOCK_INIT(kernel_pmap); 1126176771Sraj kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1127176771Sraj 1128176771Sraj debugf("kernel_pmap = 0x%08x\n", (u_int32_t)kernel_pmap); 1129176771Sraj debugf("kptbl_min = %d, kernel_kptbls = %d\n", kptbl_min, kernel_ptbls); 1130176771Sraj debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1131176771Sraj kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1132176771Sraj 1133176771Sraj /* Initialize kernel pdir */ 1134176771Sraj for (i = 0; i < kernel_ptbls; i++) 1135176771Sraj kernel_pmap->pm_pdir[kptbl_min + i] = 1136176771Sraj (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1137176771Sraj 1138176771Sraj kernel_pmap->pm_tid = KERNEL_TID; 1139176771Sraj kernel_pmap->pm_active = ~0; 1140176771Sraj 1141176771Sraj /* Initialize tidbusy with kenel_pmap entry. */ 1142176771Sraj tidbusy[0] = kernel_pmap; 1143176771Sraj 1144176771Sraj /*******************************************************/ 1145176771Sraj /* Final setup */ 1146176771Sraj /*******************************************************/ 1147182198Sraj /* Enter kstack0 into kernel map, provide guard page */ 1148182198Sraj kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1149182198Sraj thread0.td_kstack = kstack0; 1150182198Sraj thread0.td_kstack_pages = KSTACK_PAGES; 1151182198Sraj 1152182198Sraj debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1153182198Sraj debugf("kstack0_phys at 0x%08x - 0x%08x\n", 1154182198Sraj kstack0_phys, kstack0_phys + kstack0_sz); 1155182198Sraj debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1156182198Sraj 1157182198Sraj virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1158182198Sraj for (i = 0; i < KSTACK_PAGES; i++) { 1159182198Sraj mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1160182198Sraj kstack0 += PAGE_SIZE; 1161182198Sraj kstack0_phys += PAGE_SIZE; 1162182198Sraj } 1163182198Sraj 1164176771Sraj /* Initialize TLB0 handling. */ 1165176771Sraj tlb0_init(); 1166176771Sraj 1167176771Sraj debugf("mmu_booke_bootstrap: exit\n"); 1168176771Sraj} 1169176771Sraj 1170176771Sraj/* 1171176771Sraj * Get the physical page address for the given pmap/virtual address. 1172176771Sraj */ 1173176771Srajstatic vm_paddr_t 1174176771Srajmmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1175176771Sraj{ 1176176771Sraj vm_paddr_t pa; 1177176771Sraj 1178176771Sraj PMAP_LOCK(pmap); 1179176771Sraj pa = pte_vatopa(mmu, pmap, va); 1180176771Sraj PMAP_UNLOCK(pmap); 1181176771Sraj 1182176771Sraj return (pa); 1183176771Sraj} 1184176771Sraj 1185176771Sraj/* 1186176771Sraj * Extract the physical page address associated with the given 1187176771Sraj * kernel virtual address. 1188176771Sraj */ 1189176771Srajstatic vm_paddr_t 1190176771Srajmmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1191176771Sraj{ 1192176771Sraj 1193176771Sraj return (pte_vatopa(mmu, kernel_pmap, va)); 1194176771Sraj} 1195176771Sraj 1196176771Sraj/* 1197176771Sraj * Initialize the pmap module. 1198176771Sraj * Called by vm_init, to initialize any structures that the pmap 1199176771Sraj * system needs to map virtual memory. 1200176771Sraj */ 1201176771Srajstatic void 1202176771Srajmmu_booke_init(mmu_t mmu) 1203176771Sraj{ 1204176771Sraj int shpgperproc = PMAP_SHPGPERPROC; 1205176771Sraj 1206176771Sraj //debugf("mmu_booke_init: s\n"); 1207176771Sraj 1208176771Sraj /* 1209176771Sraj * Initialize the address space (zone) for the pv entries. Set a 1210176771Sraj * high water mark so that the system can recover from excessive 1211176771Sraj * numbers of pv entries. 1212176771Sraj */ 1213176771Sraj pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1214176771Sraj NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1215176771Sraj 1216176771Sraj TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1217176771Sraj pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1218176771Sraj 1219176771Sraj TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1220176771Sraj pv_entry_high_water = 9 * (pv_entry_max / 10); 1221176771Sraj 1222176771Sraj uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 1223176771Sraj 1224176771Sraj /* Pre-fill pvzone with initial number of pv entries. */ 1225176771Sraj uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1226176771Sraj 1227176771Sraj /* Initialize ptbl allocation. */ 1228176771Sraj ptbl_init(); 1229176771Sraj 1230176771Sraj //debugf("mmu_booke_init: e\n"); 1231176771Sraj} 1232176771Sraj 1233176771Sraj/* 1234176771Sraj * Map a list of wired pages into kernel virtual address space. This is 1235176771Sraj * intended for temporary mappings which do not need page modification or 1236176771Sraj * references recorded. Existing mappings in the region are overwritten. 1237176771Sraj */ 1238176771Srajstatic void 1239176771Srajmmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1240176771Sraj{ 1241176771Sraj vm_offset_t va; 1242176771Sraj 1243176771Sraj //debugf("mmu_booke_qenter: s (sva = 0x%08x count = %d)\n", sva, count); 1244176771Sraj 1245176771Sraj va = sva; 1246176771Sraj while (count-- > 0) { 1247176771Sraj mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1248176771Sraj va += PAGE_SIZE; 1249176771Sraj m++; 1250176771Sraj } 1251176771Sraj 1252176771Sraj //debugf("mmu_booke_qenter: e\n"); 1253176771Sraj} 1254176771Sraj 1255176771Sraj/* 1256176771Sraj * Remove page mappings from kernel virtual address space. Intended for 1257176771Sraj * temporary mappings entered by mmu_booke_qenter. 1258176771Sraj */ 1259176771Srajstatic void 1260176771Srajmmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1261176771Sraj{ 1262176771Sraj vm_offset_t va; 1263176771Sraj 1264176771Sraj //debugf("mmu_booke_qremove: s (sva = 0x%08x count = %d)\n", sva, count); 1265176771Sraj 1266176771Sraj va = sva; 1267176771Sraj while (count-- > 0) { 1268176771Sraj mmu_booke_kremove(mmu, va); 1269176771Sraj va += PAGE_SIZE; 1270176771Sraj } 1271176771Sraj 1272176771Sraj //debugf("mmu_booke_qremove: e\n"); 1273176771Sraj} 1274176771Sraj 1275176771Sraj/* 1276176771Sraj * Map a wired page into kernel virtual address space. 1277176771Sraj */ 1278176771Srajstatic void 1279176771Srajmmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1280176771Sraj{ 1281176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 1282176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 1283176771Sraj u_int32_t flags; 1284176771Sraj pte_t *pte; 1285176771Sraj 1286176771Sraj //debugf("mmu_booke_kenter: s (pdir_idx = %d ptbl_idx = %d va=0x%08x pa=0x%08x)\n", 1287176771Sraj // pdir_idx, ptbl_idx, va, pa); 1288176771Sraj 1289176771Sraj KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)), 1290176771Sraj ("mmu_booke_kenter: invalid va")); 1291176771Sraj 1292176771Sraj#if 0 1293176771Sraj /* assume IO mapping, set I, G bits */ 1294176771Sraj flags = (PTE_G | PTE_I | PTE_FAKE); 1295176771Sraj 1296176771Sraj /* if mapping is within system memory, do not set I, G bits */ 1297176771Sraj for (i = 0; i < totalmem_regions_sz; i++) { 1298176771Sraj if ((pa >= totalmem_regions[i].mr_start) && 1299176771Sraj (pa < (totalmem_regions[i].mr_start + 1300176771Sraj totalmem_regions[i].mr_size))) { 1301176771Sraj flags &= ~(PTE_I | PTE_G | PTE_FAKE); 1302176771Sraj break; 1303176771Sraj } 1304176771Sraj } 1305176771Sraj#else 1306176771Sraj flags = 0; 1307176771Sraj#endif 1308176771Sraj 1309176771Sraj flags |= (PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID); 1310176771Sraj 1311176771Sraj pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1312176771Sraj 1313176771Sraj if (PTE_ISVALID(pte)) { 1314176771Sraj //debugf("mmu_booke_kenter: replacing entry!\n"); 1315176771Sraj 1316176771Sraj /* Flush entry from TLB0 */ 1317176771Sraj tlb0_flush_entry(kernel_pmap, va); 1318176771Sraj } 1319176771Sraj 1320176771Sraj pte->rpn = pa & ~PTE_PA_MASK; 1321176771Sraj pte->flags = flags; 1322176771Sraj 1323176771Sraj //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1324176771Sraj // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1325176771Sraj // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1326176771Sraj 1327176771Sraj /* Flush the real memory from the instruction cache. */ 1328176771Sraj if ((flags & (PTE_I | PTE_G)) == 0) { 1329176771Sraj __syncicache((void *)va, PAGE_SIZE); 1330176771Sraj } 1331176771Sraj 1332176771Sraj //debugf("mmu_booke_kenter: e\n"); 1333176771Sraj} 1334176771Sraj 1335176771Sraj/* 1336176771Sraj * Remove a page from kernel page table. 1337176771Sraj */ 1338176771Srajstatic void 1339176771Srajmmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1340176771Sraj{ 1341176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 1342176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 1343176771Sraj pte_t *pte; 1344176771Sraj 1345176771Sraj //debugf("mmu_booke_kremove: s (va = 0x%08x)\n", va); 1346176771Sraj 1347176771Sraj KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)), 1348176771Sraj ("mmu_booke_kremove: invalid va")); 1349176771Sraj 1350176771Sraj pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1351176771Sraj 1352176771Sraj if (!PTE_ISVALID(pte)) { 1353176771Sraj //debugf("mmu_booke_kremove: e (invalid pte)\n"); 1354176771Sraj return; 1355176771Sraj } 1356176771Sraj 1357176771Sraj /* Invalidate entry in TLB0. */ 1358176771Sraj tlb0_flush_entry(kernel_pmap, va); 1359176771Sraj 1360176771Sraj pte->flags = 0; 1361176771Sraj pte->rpn = 0; 1362176771Sraj 1363176771Sraj //debugf("mmu_booke_kremove: e\n"); 1364176771Sraj} 1365176771Sraj 1366176771Sraj/* 1367176771Sraj * Initialize pmap associated with process 0. 1368176771Sraj */ 1369176771Srajstatic void 1370176771Srajmmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1371176771Sraj{ 1372176771Sraj //debugf("mmu_booke_pinit0: s (pmap = 0x%08x)\n", (u_int32_t)pmap); 1373176771Sraj mmu_booke_pinit(mmu, pmap); 1374176771Sraj PCPU_SET(curpmap, pmap); 1375176771Sraj //debugf("mmu_booke_pinit0: e\n"); 1376176771Sraj} 1377176771Sraj 1378176771Sraj/* 1379176771Sraj * Initialize a preallocated and zeroed pmap structure, 1380176771Sraj * such as one in a vmspace structure. 1381176771Sraj */ 1382176771Srajstatic void 1383176771Srajmmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1384176771Sraj{ 1385176771Sraj 1386176771Sraj //struct thread *td; 1387176771Sraj //struct proc *p; 1388176771Sraj 1389176771Sraj //td = PCPU_GET(curthread); 1390176771Sraj //p = td->td_proc; 1391176771Sraj //debugf("mmu_booke_pinit: s (pmap = 0x%08x)\n", (u_int32_t)pmap); 1392176771Sraj //printf("mmu_booke_pinit: proc %d '%s'\n", p->p_pid, p->p_comm); 1393176771Sraj 1394176771Sraj KASSERT((pmap != kernel_pmap), ("mmu_booke_pinit: initializing kernel_pmap")); 1395176771Sraj 1396176771Sraj PMAP_LOCK_INIT(pmap); 1397176771Sraj pmap->pm_tid = 0; 1398176771Sraj pmap->pm_active = 0; 1399176771Sraj bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1400176771Sraj bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1401176771Sraj 1402176771Sraj TAILQ_INIT(&pmap->ptbl_list); 1403176771Sraj 1404176771Sraj //debugf("mmu_booke_pinit: e\n"); 1405176771Sraj} 1406176771Sraj 1407176771Sraj/* 1408176771Sraj * Release any resources held by the given physical map. 1409176771Sraj * Called when a pmap initialized by mmu_booke_pinit is being released. 1410176771Sraj * Should only be called if the map contains no valid mappings. 1411176771Sraj */ 1412176771Srajstatic void 1413176771Srajmmu_booke_release(mmu_t mmu, pmap_t pmap) 1414176771Sraj{ 1415176771Sraj 1416176771Sraj //debugf("mmu_booke_release: s\n"); 1417176771Sraj 1418176771Sraj PMAP_LOCK_DESTROY(pmap); 1419176771Sraj 1420176771Sraj //debugf("mmu_booke_release: e\n"); 1421176771Sraj} 1422176771Sraj 1423176771Sraj#if 0 1424176771Sraj/* Not needed, kernel page tables are statically allocated. */ 1425176771Srajvoid 1426176771Srajmmu_booke_growkernel(vm_offset_t maxkvaddr) 1427176771Sraj{ 1428176771Sraj} 1429176771Sraj#endif 1430176771Sraj 1431176771Sraj/* 1432176771Sraj * Insert the given physical page at the specified virtual address in the 1433176771Sraj * target physical map with the protection requested. If specified the page 1434176771Sraj * will be wired down. 1435176771Sraj */ 1436176771Srajstatic void 1437176771Srajmmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1438176771Sraj vm_prot_t prot, boolean_t wired) 1439176771Sraj{ 1440176771Sraj vm_page_lock_queues(); 1441176771Sraj PMAP_LOCK(pmap); 1442176771Sraj mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired); 1443176771Sraj vm_page_unlock_queues(); 1444176771Sraj PMAP_UNLOCK(pmap); 1445176771Sraj} 1446176771Sraj 1447176771Srajstatic void 1448176771Srajmmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1449176771Sraj vm_prot_t prot, boolean_t wired) 1450176771Sraj{ 1451176771Sraj pte_t *pte; 1452176771Sraj vm_paddr_t pa; 1453176771Sraj u_int32_t flags; 1454176771Sraj int su, sync; 1455176771Sraj 1456176771Sraj pa = VM_PAGE_TO_PHYS(m); 1457176771Sraj su = (pmap == kernel_pmap); 1458176771Sraj sync = 0; 1459176771Sraj 1460176771Sraj //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1461176771Sraj // "pa=0x%08x prot=0x%08x wired=%d)\n", 1462176771Sraj // (u_int32_t)pmap, su, pmap->pm_tid, 1463176771Sraj // (u_int32_t)m, va, pa, prot, wired); 1464176771Sraj 1465176771Sraj if (su) { 1466176771Sraj KASSERT(((va >= virtual_avail) && (va <= VM_MAX_KERNEL_ADDRESS)), 1467176771Sraj ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1468176771Sraj } else { 1469176771Sraj KASSERT((va <= VM_MAXUSER_ADDRESS), 1470176771Sraj ("mmu_booke_enter_locked: user pmap, non user va")); 1471176771Sraj } 1472176771Sraj 1473176771Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1474176771Sraj 1475176771Sraj /* 1476176771Sraj * If there is an existing mapping, and the physical address has not 1477176771Sraj * changed, must be protection or wiring change. 1478176771Sraj */ 1479176771Sraj if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1480176771Sraj (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1481176771Sraj 1482176771Sraj //debugf("mmu_booke_enter_locked: update\n"); 1483176771Sraj 1484176771Sraj /* Wiring change, just update stats. */ 1485176771Sraj if (wired) { 1486176771Sraj if (!PTE_ISWIRED(pte)) { 1487176771Sraj pte->flags |= PTE_WIRED; 1488176771Sraj pmap->pm_stats.wired_count++; 1489176771Sraj } 1490176771Sraj } else { 1491176771Sraj if (PTE_ISWIRED(pte)) { 1492176771Sraj pte->flags &= ~PTE_WIRED; 1493176771Sraj pmap->pm_stats.wired_count--; 1494176771Sraj } 1495176771Sraj } 1496176771Sraj 1497176771Sraj /* Save the old bits and clear the ones we're interested in. */ 1498176771Sraj flags = pte->flags; 1499176771Sraj pte->flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1500176771Sraj 1501176771Sraj if (prot & VM_PROT_WRITE) { 1502176771Sraj /* Add write permissions. */ 1503176771Sraj pte->flags |= PTE_SW; 1504176771Sraj if (!su) 1505176771Sraj pte->flags |= PTE_UW; 1506176771Sraj } else { 1507176771Sraj /* Handle modified pages, sense modify status. */ 1508178626Smarcel if (PTE_ISMODIFIED(pte)) 1509178626Smarcel vm_page_dirty(m); 1510176771Sraj } 1511176771Sraj 1512176771Sraj /* If we're turning on execute permissions, flush the icache. */ 1513176771Sraj if (prot & VM_PROT_EXECUTE) { 1514176771Sraj pte->flags |= PTE_SX; 1515176771Sraj if (!su) 1516176771Sraj pte->flags |= PTE_UX; 1517176771Sraj 1518176771Sraj if ((flags & (PTE_UX | PTE_SX)) == 0) 1519176771Sraj sync++; 1520176771Sraj } 1521176771Sraj 1522176771Sraj /* Flush the old mapping from TLB0. */ 1523176771Sraj pte->flags &= ~PTE_REFERENCED; 1524176771Sraj tlb0_flush_entry(pmap, va); 1525176771Sraj } else { 1526176771Sraj /* 1527176771Sraj * If there is an existing mapping, but its for a different 1528176771Sraj * physical address, pte_enter() will delete the old mapping. 1529176771Sraj */ 1530176771Sraj //if ((pte != NULL) && PTE_ISVALID(pte)) 1531176771Sraj // debugf("mmu_booke_enter_locked: replace\n"); 1532176771Sraj //else 1533176771Sraj // debugf("mmu_booke_enter_locked: new\n"); 1534176771Sraj 1535176771Sraj /* Now set up the flags and install the new mapping. */ 1536176771Sraj flags = (PTE_SR | PTE_VALID); 1537176771Sraj 1538176771Sraj if (!su) 1539176771Sraj flags |= PTE_UR; 1540176771Sraj 1541176771Sraj if (prot & VM_PROT_WRITE) { 1542176771Sraj flags |= PTE_SW; 1543176771Sraj if (!su) 1544176771Sraj flags |= PTE_UW; 1545176771Sraj } 1546176771Sraj 1547176771Sraj if (prot & VM_PROT_EXECUTE) { 1548176771Sraj flags |= PTE_SX; 1549176771Sraj if (!su) 1550176771Sraj flags |= PTE_UX; 1551176771Sraj } 1552176771Sraj 1553176771Sraj /* If its wired update stats. */ 1554176771Sraj if (wired) { 1555176771Sraj pmap->pm_stats.wired_count++; 1556176771Sraj flags |= PTE_WIRED; 1557176771Sraj } 1558176771Sraj 1559176771Sraj pte_enter(mmu, pmap, m, va, flags); 1560176771Sraj 1561176771Sraj /* Flush the real memory from the instruction cache. */ 1562176771Sraj if (prot & VM_PROT_EXECUTE) 1563176771Sraj sync++; 1564176771Sraj } 1565176771Sraj 1566176771Sraj if (sync && (su || pmap == PCPU_GET(curpmap))) { 1567176771Sraj __syncicache((void *)va, PAGE_SIZE); 1568176771Sraj sync = 0; 1569176771Sraj } 1570176771Sraj 1571176771Sraj if (sync) { 1572176771Sraj /* Create a temporary mapping. */ 1573176771Sraj pmap = PCPU_GET(curpmap); 1574176771Sraj 1575176771Sraj va = 0; 1576176771Sraj pte = pte_find(mmu, pmap, va); 1577176771Sraj KASSERT(pte == NULL, ("%s:%d", __func__, __LINE__)); 1578176771Sraj 1579176771Sraj flags = PTE_SR | PTE_VALID | PTE_UR; 1580176771Sraj pte_enter(mmu, pmap, m, va, flags); 1581176771Sraj __syncicache((void *)va, PAGE_SIZE); 1582176771Sraj pte_remove(mmu, pmap, va, PTBL_UNHOLD); 1583176771Sraj } 1584176771Sraj 1585176771Sraj //debugf("mmu_booke_enter_locked: e\n"); 1586176771Sraj} 1587176771Sraj 1588176771Sraj/* 1589176771Sraj * Maps a sequence of resident pages belonging to the same object. 1590176771Sraj * The sequence begins with the given page m_start. This page is 1591176771Sraj * mapped at the given virtual address start. Each subsequent page is 1592176771Sraj * mapped at a virtual address that is offset from start by the same 1593176771Sraj * amount as the page is offset from m_start within the object. The 1594176771Sraj * last page in the sequence is the page with the largest offset from 1595176771Sraj * m_start that can be mapped at a virtual address less than the given 1596176771Sraj * virtual address end. Not every virtual page between start and end 1597176771Sraj * is mapped; only those for which a resident page exists with the 1598176771Sraj * corresponding offset from m_start are mapped. 1599176771Sraj */ 1600176771Srajstatic void 1601176771Srajmmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1602176771Sraj vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1603176771Sraj{ 1604176771Sraj vm_page_t m; 1605176771Sraj vm_pindex_t diff, psize; 1606176771Sraj 1607176771Sraj psize = atop(end - start); 1608176771Sraj m = m_start; 1609176771Sraj PMAP_LOCK(pmap); 1610176771Sraj while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1611176771Sraj mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, prot & 1612176771Sraj (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1613176771Sraj m = TAILQ_NEXT(m, listq); 1614176771Sraj } 1615176771Sraj PMAP_UNLOCK(pmap); 1616176771Sraj} 1617176771Sraj 1618176771Srajstatic void 1619176771Srajmmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1620176771Sraj vm_prot_t prot) 1621176771Sraj{ 1622176771Sraj 1623176771Sraj //debugf("mmu_booke_enter_quick: s\n"); 1624176771Sraj 1625176771Sraj PMAP_LOCK(pmap); 1626176771Sraj mmu_booke_enter_locked(mmu, pmap, va, m, 1627176771Sraj prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1628176771Sraj PMAP_UNLOCK(pmap); 1629176771Sraj 1630176771Sraj //debugf("mmu_booke_enter_quick e\n"); 1631176771Sraj} 1632176771Sraj 1633176771Sraj/* 1634176771Sraj * Remove the given range of addresses from the specified map. 1635176771Sraj * 1636176771Sraj * It is assumed that the start and end are properly rounded to the page size. 1637176771Sraj */ 1638176771Srajstatic void 1639176771Srajmmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1640176771Sraj{ 1641176771Sraj pte_t *pte; 1642176771Sraj u_int8_t hold_flag; 1643176771Sraj 1644176771Sraj int su = (pmap == kernel_pmap); 1645176771Sraj 1646176771Sraj //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1647176771Sraj // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1648176771Sraj 1649176771Sraj if (su) { 1650176771Sraj KASSERT(((va >= virtual_avail) && (va <= VM_MAX_KERNEL_ADDRESS)), 1651176771Sraj ("mmu_booke_enter: kernel pmap, non kernel va")); 1652176771Sraj } else { 1653176771Sraj KASSERT((va <= VM_MAXUSER_ADDRESS), 1654176771Sraj ("mmu_booke_enter: user pmap, non user va")); 1655176771Sraj } 1656176771Sraj 1657176771Sraj if (PMAP_REMOVE_DONE(pmap)) { 1658176771Sraj //debugf("mmu_booke_remove: e (empty)\n"); 1659176771Sraj return; 1660176771Sraj } 1661176771Sraj 1662176771Sraj hold_flag = PTBL_HOLD_FLAG(pmap); 1663176771Sraj //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1664176771Sraj 1665176771Sraj vm_page_lock_queues(); 1666176771Sraj PMAP_LOCK(pmap); 1667176771Sraj for (; va < endva; va += PAGE_SIZE) { 1668176771Sraj pte = pte_find(mmu, pmap, va); 1669176771Sraj if ((pte != NULL) && PTE_ISVALID(pte)) { 1670176771Sraj pte_remove(mmu, pmap, va, hold_flag); 1671176771Sraj 1672176771Sraj /* Flush mapping from TLB0. */ 1673176771Sraj tlb0_flush_entry(pmap, va); 1674176771Sraj } 1675176771Sraj } 1676176771Sraj PMAP_UNLOCK(pmap); 1677176771Sraj vm_page_unlock_queues(); 1678176771Sraj 1679176771Sraj //debugf("mmu_booke_remove: e\n"); 1680176771Sraj} 1681176771Sraj 1682176771Sraj/* 1683176771Sraj * Remove physical page from all pmaps in which it resides. 1684176771Sraj */ 1685176771Srajstatic void 1686176771Srajmmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1687176771Sraj{ 1688176771Sraj pv_entry_t pv, pvn; 1689176771Sraj u_int8_t hold_flag; 1690176771Sraj 1691176771Sraj //debugf("mmu_booke_remove_all: s\n"); 1692176771Sraj 1693176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1694176771Sraj 1695176771Sraj for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1696176771Sraj pvn = TAILQ_NEXT(pv, pv_link); 1697176771Sraj 1698176771Sraj PMAP_LOCK(pv->pv_pmap); 1699176771Sraj hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1700176771Sraj pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1701176771Sraj 1702176771Sraj /* Flush mapping from TLB0. */ 1703176771Sraj tlb0_flush_entry(pv->pv_pmap, pv->pv_va); 1704176771Sraj PMAP_UNLOCK(pv->pv_pmap); 1705176771Sraj } 1706176771Sraj vm_page_flag_clear(m, PG_WRITEABLE); 1707176771Sraj 1708176771Sraj //debugf("mmu_booke_remove_all: e\n"); 1709176771Sraj} 1710176771Sraj 1711176771Sraj/* 1712176771Sraj * Map a range of physical addresses into kernel virtual address space. 1713176771Sraj * 1714176771Sraj * The value passed in *virt is a suggested virtual address for the mapping. 1715176771Sraj * Architectures which can support a direct-mapped physical to virtual region 1716176771Sraj * can return the appropriate address within that region, leaving '*virt' 1717176771Sraj * unchanged. We cannot and therefore do not; *virt is updated with the 1718176771Sraj * first usable address after the mapped region. 1719176771Sraj */ 1720176771Srajstatic vm_offset_t 1721176771Srajmmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1722176771Sraj vm_offset_t pa_end, int prot) 1723176771Sraj{ 1724176771Sraj vm_offset_t sva = *virt; 1725176771Sraj vm_offset_t va = sva; 1726176771Sraj 1727176771Sraj //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1728176771Sraj // sva, pa_start, pa_end); 1729176771Sraj 1730176771Sraj while (pa_start < pa_end) { 1731176771Sraj mmu_booke_kenter(mmu, va, pa_start); 1732176771Sraj va += PAGE_SIZE; 1733176771Sraj pa_start += PAGE_SIZE; 1734176771Sraj } 1735176771Sraj *virt = va; 1736176771Sraj 1737176771Sraj //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1738176771Sraj return (sva); 1739176771Sraj} 1740176771Sraj 1741176771Sraj/* 1742176771Sraj * The pmap must be activated before it's address space can be accessed in any 1743176771Sraj * way. 1744176771Sraj */ 1745176771Srajstatic void 1746176771Srajmmu_booke_activate(mmu_t mmu, struct thread *td) 1747176771Sraj{ 1748176771Sraj pmap_t pmap; 1749176771Sraj 1750176771Sraj pmap = &td->td_proc->p_vmspace->vm_pmap; 1751176771Sraj 1752176771Sraj //debugf("mmu_booke_activate: s (proc = '%s', id = %d, pmap = 0x%08x)\n", 1753176771Sraj // td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1754176771Sraj 1755176771Sraj KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1756176771Sraj 1757176771Sraj mtx_lock_spin(&sched_lock); 1758176771Sraj 1759176771Sraj pmap->pm_active |= PCPU_GET(cpumask); 1760176771Sraj PCPU_SET(curpmap, pmap); 1761176771Sraj 1762176771Sraj if (!pmap->pm_tid) 1763176771Sraj tid_alloc(pmap); 1764176771Sraj 1765176771Sraj /* Load PID0 register with pmap tid value. */ 1766176771Sraj load_pid0(pmap->pm_tid); 1767176771Sraj 1768176771Sraj mtx_unlock_spin(&sched_lock); 1769176771Sraj 1770176771Sraj //debugf("mmu_booke_activate: e (tid = %d for '%s')\n", pmap->pm_tid, 1771176771Sraj // td->td_proc->p_comm); 1772176771Sraj} 1773176771Sraj 1774176771Sraj/* 1775176771Sraj * Deactivate the specified process's address space. 1776176771Sraj */ 1777176771Srajstatic void 1778176771Srajmmu_booke_deactivate(mmu_t mmu, struct thread *td) 1779176771Sraj{ 1780176771Sraj pmap_t pmap; 1781176771Sraj 1782176771Sraj pmap = &td->td_proc->p_vmspace->vm_pmap; 1783176771Sraj pmap->pm_active &= ~(PCPU_GET(cpumask)); 1784176771Sraj PCPU_SET(curpmap, NULL); 1785176771Sraj} 1786176771Sraj 1787176771Sraj/* 1788176771Sraj * Copy the range specified by src_addr/len 1789176771Sraj * from the source map to the range dst_addr/len 1790176771Sraj * in the destination map. 1791176771Sraj * 1792176771Sraj * This routine is only advisory and need not do anything. 1793176771Sraj */ 1794176771Srajstatic void 1795176771Srajmmu_booke_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 1796176771Sraj vm_size_t len, vm_offset_t src_addr) 1797176771Sraj{ 1798176771Sraj 1799176771Sraj} 1800176771Sraj 1801176771Sraj/* 1802176771Sraj * Set the physical protection on the specified range of this map as requested. 1803176771Sraj */ 1804176771Srajstatic void 1805176771Srajmmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1806176771Sraj vm_prot_t prot) 1807176771Sraj{ 1808176771Sraj vm_offset_t va; 1809176771Sraj vm_page_t m; 1810176771Sraj pte_t *pte; 1811176771Sraj 1812176771Sraj if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1813176771Sraj mmu_booke_remove(mmu, pmap, sva, eva); 1814176771Sraj return; 1815176771Sraj } 1816176771Sraj 1817176771Sraj if (prot & VM_PROT_WRITE) 1818176771Sraj return; 1819176771Sraj 1820176771Sraj vm_page_lock_queues(); 1821176771Sraj PMAP_LOCK(pmap); 1822176771Sraj for (va = sva; va < eva; va += PAGE_SIZE) { 1823176771Sraj if ((pte = pte_find(mmu, pmap, va)) != NULL) { 1824176771Sraj if (PTE_ISVALID(pte)) { 1825176771Sraj m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1826176771Sraj 1827176771Sraj /* Handle modified pages. */ 1828178626Smarcel if (PTE_ISMODIFIED(pte)) 1829178626Smarcel vm_page_dirty(m); 1830176771Sraj 1831176771Sraj /* Referenced pages. */ 1832176771Sraj if (PTE_ISREFERENCED(pte)) 1833176771Sraj vm_page_flag_set(m, PG_REFERENCED); 1834176771Sraj 1835176771Sraj /* Flush mapping from TLB0. */ 1836176771Sraj pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED | 1837176771Sraj PTE_REFERENCED); 1838176771Sraj tlb0_flush_entry(pmap, va); 1839176771Sraj } 1840176771Sraj } 1841176771Sraj } 1842176771Sraj PMAP_UNLOCK(pmap); 1843176771Sraj vm_page_unlock_queues(); 1844176771Sraj} 1845176771Sraj 1846176771Sraj/* 1847176771Sraj * Clear the write and modified bits in each of the given page's mappings. 1848176771Sraj */ 1849176771Srajstatic void 1850176771Srajmmu_booke_remove_write(mmu_t mmu, vm_page_t m) 1851176771Sraj{ 1852176771Sraj pv_entry_t pv; 1853176771Sraj pte_t *pte; 1854176771Sraj 1855176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1856176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1857176771Sraj (m->flags & PG_WRITEABLE) == 0) 1858176771Sraj return; 1859176771Sraj 1860176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1861176771Sraj PMAP_LOCK(pv->pv_pmap); 1862176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 1863176771Sraj if (PTE_ISVALID(pte)) { 1864176771Sraj m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1865176771Sraj 1866176771Sraj /* Handle modified pages. */ 1867178626Smarcel if (PTE_ISMODIFIED(pte)) 1868178626Smarcel vm_page_dirty(m); 1869176771Sraj 1870176771Sraj /* Referenced pages. */ 1871176771Sraj if (PTE_ISREFERENCED(pte)) 1872176771Sraj vm_page_flag_set(m, PG_REFERENCED); 1873176771Sraj 1874176771Sraj /* Flush mapping from TLB0. */ 1875176771Sraj pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED | 1876176771Sraj PTE_REFERENCED); 1877176771Sraj tlb0_flush_entry(pv->pv_pmap, pv->pv_va); 1878176771Sraj } 1879176771Sraj } 1880176771Sraj PMAP_UNLOCK(pv->pv_pmap); 1881176771Sraj } 1882176771Sraj vm_page_flag_clear(m, PG_WRITEABLE); 1883176771Sraj} 1884176771Sraj 1885176771Srajstatic boolean_t 1886176771Srajmmu_booke_page_executable(mmu_t mmu, vm_page_t m) 1887176771Sraj{ 1888176771Sraj pv_entry_t pv; 1889176771Sraj pte_t *pte; 1890176771Sraj boolean_t executable; 1891176771Sraj 1892176771Sraj executable = FALSE; 1893176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1894176771Sraj PMAP_LOCK(pv->pv_pmap); 1895176771Sraj pte = pte_find(mmu, pv->pv_pmap, pv->pv_va); 1896176771Sraj if (pte != NULL && PTE_ISVALID(pte) && (pte->flags & PTE_UX)) 1897176771Sraj executable = TRUE; 1898176771Sraj PMAP_UNLOCK(pv->pv_pmap); 1899176771Sraj if (executable) 1900176771Sraj break; 1901176771Sraj } 1902176771Sraj 1903176771Sraj return (executable); 1904176771Sraj} 1905176771Sraj 1906176771Sraj/* 1907176771Sraj * Atomically extract and hold the physical page with the given 1908176771Sraj * pmap and virtual address pair if that mapping permits the given 1909176771Sraj * protection. 1910176771Sraj */ 1911176771Srajstatic vm_page_t 1912176771Srajmmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 1913176771Sraj vm_prot_t prot) 1914176771Sraj{ 1915176771Sraj pte_t *pte; 1916176771Sraj vm_page_t m; 1917176771Sraj u_int32_t pte_wbit; 1918176771Sraj 1919176771Sraj m = NULL; 1920176771Sraj vm_page_lock_queues(); 1921176771Sraj PMAP_LOCK(pmap); 1922176771Sraj pte = pte_find(mmu, pmap, va); 1923176771Sraj 1924176771Sraj if ((pte != NULL) && PTE_ISVALID(pte)) { 1925176771Sraj if (pmap == kernel_pmap) 1926176771Sraj pte_wbit = PTE_SW; 1927176771Sraj else 1928176771Sraj pte_wbit = PTE_UW; 1929176771Sraj 1930176771Sraj if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 1931176771Sraj m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1932176771Sraj vm_page_hold(m); 1933176771Sraj } 1934176771Sraj } 1935176771Sraj 1936176771Sraj vm_page_unlock_queues(); 1937176771Sraj PMAP_UNLOCK(pmap); 1938176771Sraj return (m); 1939176771Sraj} 1940176771Sraj 1941176771Sraj/* 1942176771Sraj * Initialize a vm_page's machine-dependent fields. 1943176771Sraj */ 1944176771Srajstatic void 1945176771Srajmmu_booke_page_init(mmu_t mmu, vm_page_t m) 1946176771Sraj{ 1947176771Sraj 1948176771Sraj TAILQ_INIT(&m->md.pv_list); 1949176771Sraj} 1950176771Sraj 1951176771Sraj/* 1952176771Sraj * mmu_booke_zero_page_area zeros the specified hardware page by 1953176771Sraj * mapping it into virtual memory and using bzero to clear 1954176771Sraj * its contents. 1955176771Sraj * 1956176771Sraj * off and size must reside within a single page. 1957176771Sraj */ 1958176771Srajstatic void 1959176771Srajmmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 1960176771Sraj{ 1961176771Sraj vm_offset_t va; 1962176771Sraj 1963176771Sraj //debugf("mmu_booke_zero_page_area: s\n"); 1964176771Sraj 1965176771Sraj mtx_lock(&zero_page_mutex); 1966176771Sraj va = zero_page_va; 1967176771Sraj 1968176771Sraj mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 1969176771Sraj bzero((caddr_t)va + off, size); 1970176771Sraj mmu_booke_kremove(mmu, va); 1971176771Sraj 1972176771Sraj mtx_unlock(&zero_page_mutex); 1973176771Sraj 1974176771Sraj //debugf("mmu_booke_zero_page_area: e\n"); 1975176771Sraj} 1976176771Sraj 1977176771Sraj/* 1978176771Sraj * mmu_booke_zero_page zeros the specified hardware page. 1979176771Sraj */ 1980176771Srajstatic void 1981176771Srajmmu_booke_zero_page(mmu_t mmu, vm_page_t m) 1982176771Sraj{ 1983176771Sraj 1984176771Sraj //debugf("mmu_booke_zero_page: s\n"); 1985176771Sraj mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 1986176771Sraj //debugf("mmu_booke_zero_page: e\n"); 1987176771Sraj} 1988176771Sraj 1989176771Sraj/* 1990176771Sraj * mmu_booke_copy_page copies the specified (machine independent) page by 1991176771Sraj * mapping the page into virtual memory and using memcopy to copy the page, 1992176771Sraj * one machine dependent page at a time. 1993176771Sraj */ 1994176771Srajstatic void 1995176771Srajmmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 1996176771Sraj{ 1997176771Sraj vm_offset_t sva, dva; 1998176771Sraj 1999176771Sraj //debugf("mmu_booke_copy_page: s\n"); 2000176771Sraj 2001176771Sraj mtx_lock(©_page_mutex); 2002176771Sraj sva = copy_page_src_va; 2003176771Sraj dva = copy_page_dst_va; 2004176771Sraj 2005176771Sraj mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2006176771Sraj mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2007176771Sraj memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2008176771Sraj mmu_booke_kremove(mmu, dva); 2009176771Sraj mmu_booke_kremove(mmu, sva); 2010176771Sraj 2011176771Sraj mtx_unlock(©_page_mutex); 2012176771Sraj 2013176771Sraj //debugf("mmu_booke_copy_page: e\n"); 2014176771Sraj} 2015176771Sraj 2016176771Sraj#if 0 2017176771Sraj/* 2018176771Sraj * Remove all pages from specified address space, this aids process exit 2019176771Sraj * speeds. This is much faster than mmu_booke_remove in the case of running 2020176771Sraj * down an entire address space. Only works for the current pmap. 2021176771Sraj */ 2022176771Srajvoid 2023176771Srajmmu_booke_remove_pages(pmap_t pmap) 2024176771Sraj{ 2025176771Sraj} 2026176771Sraj#endif 2027176771Sraj 2028176771Sraj/* 2029176771Sraj * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2030176771Sraj * into virtual memory and using bzero to clear its contents. This is intended 2031176771Sraj * to be called from the vm_pagezero process only and outside of Giant. No 2032176771Sraj * lock is required. 2033176771Sraj */ 2034176771Srajstatic void 2035176771Srajmmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2036176771Sraj{ 2037176771Sraj vm_offset_t va; 2038176771Sraj 2039176771Sraj //debugf("mmu_booke_zero_page_idle: s\n"); 2040176771Sraj 2041176771Sraj va = zero_page_idle_va; 2042176771Sraj mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2043176771Sraj bzero((caddr_t)va, PAGE_SIZE); 2044176771Sraj mmu_booke_kremove(mmu, va); 2045176771Sraj 2046176771Sraj //debugf("mmu_booke_zero_page_idle: e\n"); 2047176771Sraj} 2048176771Sraj 2049176771Sraj/* 2050176771Sraj * Return whether or not the specified physical page was modified 2051176771Sraj * in any of physical maps. 2052176771Sraj */ 2053176771Srajstatic boolean_t 2054176771Srajmmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2055176771Sraj{ 2056176771Sraj pte_t *pte; 2057176771Sraj pv_entry_t pv; 2058176771Sraj 2059176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2060176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2061176771Sraj return (FALSE); 2062176771Sraj 2063176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2064176771Sraj PMAP_LOCK(pv->pv_pmap); 2065176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2066176771Sraj if (!PTE_ISVALID(pte)) 2067176771Sraj goto make_sure_to_unlock; 2068176771Sraj 2069176771Sraj if (PTE_ISMODIFIED(pte)) { 2070176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2071176771Sraj return (TRUE); 2072176771Sraj } 2073176771Sraj } 2074176771Srajmake_sure_to_unlock: 2075176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2076176771Sraj } 2077176771Sraj return (FALSE); 2078176771Sraj} 2079176771Sraj 2080176771Sraj/* 2081176771Sraj * Return whether or not the specified virtual address is elgible 2082176771Sraj * for prefault. 2083176771Sraj */ 2084176771Srajstatic boolean_t 2085176771Srajmmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2086176771Sraj{ 2087176771Sraj 2088176771Sraj return (FALSE); 2089176771Sraj} 2090176771Sraj 2091176771Sraj/* 2092176771Sraj * Clear the modify bits on the specified physical page. 2093176771Sraj */ 2094176771Srajstatic void 2095176771Srajmmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2096176771Sraj{ 2097176771Sraj pte_t *pte; 2098176771Sraj pv_entry_t pv; 2099176771Sraj 2100176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2101176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2102176771Sraj return; 2103176771Sraj 2104176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2105176771Sraj PMAP_LOCK(pv->pv_pmap); 2106176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2107176771Sraj if (!PTE_ISVALID(pte)) 2108176771Sraj goto make_sure_to_unlock; 2109176771Sraj 2110176771Sraj if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2111176771Sraj pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2112176771Sraj PTE_REFERENCED); 2113176771Sraj tlb0_flush_entry(pv->pv_pmap, pv->pv_va); 2114176771Sraj } 2115176771Sraj } 2116176771Srajmake_sure_to_unlock: 2117176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2118176771Sraj } 2119176771Sraj} 2120176771Sraj 2121176771Sraj/* 2122176771Sraj * Return a count of reference bits for a page, clearing those bits. 2123176771Sraj * It is not necessary for every reference bit to be cleared, but it 2124176771Sraj * is necessary that 0 only be returned when there are truly no 2125176771Sraj * reference bits set. 2126176771Sraj * 2127176771Sraj * XXX: The exact number of bits to check and clear is a matter that 2128176771Sraj * should be tested and standardized at some point in the future for 2129176771Sraj * optimal aging of shared pages. 2130176771Sraj */ 2131176771Srajstatic int 2132176771Srajmmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2133176771Sraj{ 2134176771Sraj pte_t *pte; 2135176771Sraj pv_entry_t pv; 2136176771Sraj int count; 2137176771Sraj 2138176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2139176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2140176771Sraj return (0); 2141176771Sraj 2142176771Sraj count = 0; 2143176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2144176771Sraj PMAP_LOCK(pv->pv_pmap); 2145176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2146176771Sraj if (!PTE_ISVALID(pte)) 2147176771Sraj goto make_sure_to_unlock; 2148176771Sraj 2149176771Sraj if (PTE_ISREFERENCED(pte)) { 2150176771Sraj pte->flags &= ~PTE_REFERENCED; 2151176771Sraj tlb0_flush_entry(pv->pv_pmap, pv->pv_va); 2152176771Sraj 2153176771Sraj if (++count > 4) { 2154176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2155176771Sraj break; 2156176771Sraj } 2157176771Sraj } 2158176771Sraj } 2159176771Srajmake_sure_to_unlock: 2160176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2161176771Sraj } 2162176771Sraj return (count); 2163176771Sraj} 2164176771Sraj 2165176771Sraj/* 2166176771Sraj * Clear the reference bit on the specified physical page. 2167176771Sraj */ 2168176771Srajstatic void 2169176771Srajmmu_booke_clear_reference(mmu_t mmu, vm_page_t m) 2170176771Sraj{ 2171176771Sraj pte_t *pte; 2172176771Sraj pv_entry_t pv; 2173176771Sraj 2174176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2175176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2176176771Sraj return; 2177176771Sraj 2178176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2179176771Sraj PMAP_LOCK(pv->pv_pmap); 2180176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 2181176771Sraj if (!PTE_ISVALID(pte)) 2182176771Sraj goto make_sure_to_unlock; 2183176771Sraj 2184176771Sraj if (PTE_ISREFERENCED(pte)) { 2185176771Sraj pte->flags &= ~PTE_REFERENCED; 2186176771Sraj tlb0_flush_entry(pv->pv_pmap, pv->pv_va); 2187176771Sraj } 2188176771Sraj } 2189176771Srajmake_sure_to_unlock: 2190176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2191176771Sraj } 2192176771Sraj} 2193176771Sraj 2194176771Sraj/* 2195176771Sraj * Change wiring attribute for a map/virtual-address pair. 2196176771Sraj */ 2197176771Srajstatic void 2198176771Srajmmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired) 2199176771Sraj{ 2200176771Sraj pte_t *pte;; 2201176771Sraj 2202176771Sraj PMAP_LOCK(pmap); 2203176771Sraj if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2204176771Sraj if (wired) { 2205176771Sraj if (!PTE_ISWIRED(pte)) { 2206176771Sraj pte->flags |= PTE_WIRED; 2207176771Sraj pmap->pm_stats.wired_count++; 2208176771Sraj } 2209176771Sraj } else { 2210176771Sraj if (PTE_ISWIRED(pte)) { 2211176771Sraj pte->flags &= ~PTE_WIRED; 2212176771Sraj pmap->pm_stats.wired_count--; 2213176771Sraj } 2214176771Sraj } 2215176771Sraj } 2216176771Sraj PMAP_UNLOCK(pmap); 2217176771Sraj} 2218176771Sraj 2219176771Sraj/* 2220176771Sraj * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2221176771Sraj * page. This count may be changed upwards or downwards in the future; it is 2222176771Sraj * only necessary that true be returned for a small subset of pmaps for proper 2223176771Sraj * page aging. 2224176771Sraj */ 2225176771Srajstatic boolean_t 2226176771Srajmmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2227176771Sraj{ 2228176771Sraj pv_entry_t pv; 2229176771Sraj int loops; 2230176771Sraj 2231176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2232176771Sraj if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 2233176771Sraj return (FALSE); 2234176771Sraj 2235176771Sraj loops = 0; 2236176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2237176771Sraj 2238176771Sraj if (pv->pv_pmap == pmap) 2239176771Sraj return (TRUE); 2240176771Sraj 2241176771Sraj if (++loops >= 16) 2242176771Sraj break; 2243176771Sraj } 2244176771Sraj return (FALSE); 2245176771Sraj} 2246176771Sraj 2247176771Sraj/* 2248176771Sraj * Return the number of managed mappings to the given physical page that are 2249176771Sraj * wired. 2250176771Sraj */ 2251176771Srajstatic int 2252176771Srajmmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2253176771Sraj{ 2254176771Sraj pv_entry_t pv; 2255176771Sraj pte_t *pte; 2256176771Sraj int count = 0; 2257176771Sraj 2258176771Sraj if ((m->flags & PG_FICTITIOUS) != 0) 2259176771Sraj return (count); 2260176771Sraj mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2261176771Sraj 2262176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2263176771Sraj PMAP_LOCK(pv->pv_pmap); 2264176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2265176771Sraj if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2266176771Sraj count++; 2267176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2268176771Sraj } 2269176771Sraj 2270176771Sraj return (count); 2271176771Sraj} 2272176771Sraj 2273176771Srajstatic int 2274176771Srajmmu_booke_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2275176771Sraj{ 2276176771Sraj int i; 2277176771Sraj vm_offset_t va; 2278176771Sraj 2279176771Sraj /* 2280176771Sraj * This currently does not work for entries that 2281176771Sraj * overlap TLB1 entries. 2282176771Sraj */ 2283176771Sraj for (i = 0; i < tlb1_idx; i ++) { 2284176771Sraj if (tlb1_iomapped(i, pa, size, &va) == 0) 2285176771Sraj return (0); 2286176771Sraj } 2287176771Sraj 2288176771Sraj return (EFAULT); 2289176771Sraj} 2290176771Sraj 2291176771Sraj/* 2292176771Sraj * Map a set of physical memory pages into the kernel virtual address space. 2293176771Sraj * Return a pointer to where it is mapped. This routine is intended to be used 2294176771Sraj * for mapping device memory, NOT real memory. 2295176771Sraj */ 2296176771Srajstatic void * 2297176771Srajmmu_booke_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2298176771Sraj{ 2299184244Smarcel void *res; 2300176771Sraj uintptr_t va; 2301184244Smarcel vm_size_t sz; 2302176771Sraj 2303176771Sraj va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa); 2304184244Smarcel res = (void *)va; 2305184244Smarcel 2306184244Smarcel do { 2307184244Smarcel sz = 1 << (ilog2(size) & ~1); 2308184244Smarcel if (bootverbose) 2309184244Smarcel printf("Wiring VA=%x to PA=%x (size=%x), " 2310184244Smarcel "using TLB1[%d]\n", va, pa, sz, tlb1_idx); 2311184244Smarcel tlb1_set_entry(va, pa, sz, _TLB_ENTRY_IO); 2312184244Smarcel size -= sz; 2313184244Smarcel pa += sz; 2314184244Smarcel va += sz; 2315184244Smarcel } while (size > 0); 2316184244Smarcel 2317184244Smarcel return (res); 2318176771Sraj} 2319176771Sraj 2320176771Sraj/* 2321176771Sraj * 'Unmap' a range mapped by mmu_booke_mapdev(). 2322176771Sraj */ 2323176771Srajstatic void 2324176771Srajmmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2325176771Sraj{ 2326176771Sraj vm_offset_t base, offset; 2327176771Sraj 2328176771Sraj //debugf("mmu_booke_unmapdev: s (va = 0x%08x)\n", va); 2329176771Sraj 2330176771Sraj /* 2331176771Sraj * Unmap only if this is inside kernel virtual space. 2332176771Sraj */ 2333176771Sraj if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2334176771Sraj base = trunc_page(va); 2335176771Sraj offset = va & PAGE_MASK; 2336176771Sraj size = roundup(offset + size, PAGE_SIZE); 2337176771Sraj kmem_free(kernel_map, base, size); 2338176771Sraj } 2339176771Sraj 2340176771Sraj //debugf("mmu_booke_unmapdev: e\n"); 2341176771Sraj} 2342176771Sraj 2343176771Sraj/* 2344176771Sraj * mmu_booke_object_init_pt preloads the ptes for a given object 2345176771Sraj * into the specified pmap. This eliminates the blast of soft 2346176771Sraj * faults on process startup and immediately after an mmap. 2347176771Sraj */ 2348176771Srajstatic void 2349176771Srajmmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2350176771Sraj vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2351176771Sraj{ 2352176771Sraj VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2353176771Sraj KASSERT(object->type == OBJT_DEVICE, 2354176771Sraj ("mmu_booke_object_init_pt: non-device object")); 2355176771Sraj} 2356176771Sraj 2357176771Sraj/* 2358176771Sraj * Perform the pmap work for mincore. 2359176771Sraj */ 2360176771Srajstatic int 2361176771Srajmmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2362176771Sraj{ 2363176771Sraj 2364176771Sraj TODO; 2365176771Sraj return (0); 2366176771Sraj} 2367176771Sraj 2368176771Sraj/**************************************************************************/ 2369176771Sraj/* TID handling */ 2370176771Sraj/**************************************************************************/ 2371176771Sraj/* 2372176771Sraj * Flush all entries from TLB0 matching given tid. 2373176771Sraj */ 2374176771Srajstatic void 2375176771Srajtid_flush(tlbtid_t tid) 2376176771Sraj{ 2377176771Sraj int i, entryidx, way; 2378176771Sraj 2379176771Sraj //debugf("tid_flush: s (tid = %d)\n", tid); 2380176771Sraj 2381176771Sraj mtx_lock_spin(&tlb0_mutex); 2382176771Sraj 2383176771Sraj for (i = 0; i < TLB0_SIZE; i++) { 2384176771Sraj if (MAS1_GETTID(tlb0[i].mas1) == tid) { 2385176771Sraj way = i / TLB0_ENTRIES_PER_WAY; 2386176771Sraj entryidx = i - (way * TLB0_ENTRIES_PER_WAY); 2387176771Sraj 2388176771Sraj //debugf("tid_flush: inval tlb0 entry %d\n", i); 2389176771Sraj tlb0_inval_entry(entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT, way); 2390176771Sraj } 2391176771Sraj } 2392176771Sraj 2393176771Sraj mtx_unlock_spin(&tlb0_mutex); 2394176771Sraj 2395176771Sraj //debugf("tid_flush: e\n"); 2396176771Sraj} 2397176771Sraj 2398176771Sraj/* 2399176771Sraj * Allocate a TID. If necessary, steal one from someone else. 2400176771Sraj * The new TID is flushed from the TLB before returning. 2401176771Sraj */ 2402176771Srajstatic tlbtid_t 2403176771Srajtid_alloc(pmap_t pmap) 2404176771Sraj{ 2405176771Sraj tlbtid_t tid; 2406176771Sraj static tlbtid_t next_tid = TID_MIN; 2407176771Sraj 2408176771Sraj //struct thread *td; 2409176771Sraj //struct proc *p; 2410176771Sraj 2411176771Sraj //td = PCPU_GET(curthread); 2412176771Sraj //p = td->td_proc; 2413176771Sraj //debugf("tid_alloc: s (pmap = 0x%08x)\n", (u_int32_t)pmap); 2414176771Sraj //printf("tid_alloc: proc %d '%s'\n", p->p_pid, p->p_comm); 2415176771Sraj 2416176771Sraj KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2417176771Sraj 2418176771Sraj /* 2419176771Sraj * Find a likely TID, allocate unused if possible, 2420176771Sraj * skip reserved entries. 2421176771Sraj */ 2422176771Sraj tid = next_tid; 2423176771Sraj while (tidbusy[tid] != NULL) { 2424176771Sraj if (tid == next_tid) 2425176771Sraj break; 2426176771Sraj 2427176771Sraj if (tid == TID_MAX) 2428176771Sraj tid = TID_MIN; 2429176771Sraj else 2430176771Sraj tid++; 2431176771Sraj 2432176771Sraj } 2433176771Sraj 2434176771Sraj /* Now clean it out */ 2435176771Sraj tid_flush(tid); 2436176771Sraj 2437176771Sraj /* If we are stealing pmap then clear its tid */ 2438176771Sraj if (tidbusy[tid]) { 2439176771Sraj //debugf("warning: stealing tid %d\n", tid); 2440176771Sraj tidbusy[tid]->pm_tid = 0; 2441176771Sraj } 2442176771Sraj 2443176771Sraj /* Calculate next tid */ 2444176771Sraj if (tid == TID_MAX) 2445176771Sraj next_tid = TID_MIN; 2446176771Sraj else 2447176771Sraj next_tid = tid + 1; 2448176771Sraj 2449176771Sraj tidbusy[tid] = pmap; 2450176771Sraj pmap->pm_tid = tid; 2451176771Sraj 2452176771Sraj //debugf("tid_alloc: e (%02d next = %02d)\n", tid, next_tid); 2453176771Sraj return (tid); 2454176771Sraj} 2455176771Sraj 2456176771Sraj#if 0 2457176771Sraj/* 2458176771Sraj * Free this pmap's TID. 2459176771Sraj */ 2460176771Srajstatic void 2461176771Srajtid_free(pmap_t pmap) 2462176771Sraj{ 2463176771Sraj tlbtid_t oldtid; 2464176771Sraj 2465176771Sraj oldtid = pmap->pm_tid; 2466176771Sraj 2467176771Sraj if (oldtid == 0) { 2468176771Sraj panic("tid_free: freeing kernel tid"); 2469176771Sraj } 2470176771Sraj 2471176771Sraj#ifdef DEBUG 2472176771Sraj if (tidbusy[oldtid] == 0) 2473176771Sraj debugf("tid_free: freeing free tid %d\n", oldtid); 2474176771Sraj if (tidbusy[oldtid] != pmap) { 2475176771Sraj debugf("tid_free: freeing someone esle's tid\n " 2476176771Sraj "tidbusy[%d] = 0x%08x pmap = 0x%08x\n", 2477176771Sraj oldtid, (u_int32_t)tidbusy[oldtid], (u_int32_t)pmap); 2478176771Sraj } 2479176771Sraj#endif 2480176771Sraj 2481176771Sraj tidbusy[oldtid] = NULL; 2482176771Sraj tid_flush(oldtid); 2483176771Sraj} 2484176771Sraj#endif 2485176771Sraj 2486176771Sraj#if 0 2487176771Sraj#if DEBUG 2488176771Srajstatic void 2489176771Srajtid_print_busy(void) 2490176771Sraj{ 2491176771Sraj int i; 2492176771Sraj 2493176771Sraj for (i = 0; i < TID_MAX; i++) { 2494176771Sraj debugf("tid %d = pmap 0x%08x", i, (u_int32_t)tidbusy[i]); 2495176771Sraj if (tidbusy[i]) 2496176771Sraj debugf(" pmap->tid = %d", tidbusy[i]->pm_tid); 2497176771Sraj debugf("\n"); 2498176771Sraj } 2499176771Sraj 2500176771Sraj} 2501176771Sraj#endif /* DEBUG */ 2502176771Sraj#endif 2503176771Sraj 2504176771Sraj/**************************************************************************/ 2505176771Sraj/* TLB0 handling */ 2506176771Sraj/**************************************************************************/ 2507176771Sraj 2508176771Srajstatic void 2509176771Srajtlb_print_entry(int i, u_int32_t mas1, u_int32_t mas2, u_int32_t mas3, u_int32_t mas7) 2510176771Sraj{ 2511176771Sraj int as; 2512176771Sraj char desc[3]; 2513176771Sraj tlbtid_t tid; 2514176771Sraj vm_size_t size; 2515176771Sraj unsigned int tsize; 2516176771Sraj 2517176771Sraj desc[2] = '\0'; 2518176771Sraj if (mas1 & MAS1_VALID) 2519176771Sraj desc[0] = 'V'; 2520176771Sraj else 2521176771Sraj desc[0] = ' '; 2522176771Sraj 2523176771Sraj if (mas1 & MAS1_IPROT) 2524176771Sraj desc[1] = 'P'; 2525176771Sraj else 2526176771Sraj desc[1] = ' '; 2527176771Sraj 2528176771Sraj as = (mas1 & MAS1_TS) ? 1 : 0; 2529176771Sraj tid = MAS1_GETTID(mas1); 2530176771Sraj 2531176771Sraj tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2532176771Sraj size = 0; 2533176771Sraj if (tsize) 2534176771Sraj size = tsize2size(tsize); 2535176771Sraj 2536176771Sraj debugf("%3d: (%s) [AS=%d] " 2537176771Sraj "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2538176771Sraj "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2539176771Sraj i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2540176771Sraj} 2541176771Sraj 2542176771Sraj/* Convert TLB0 va and way number to tlb0[] table index. */ 2543176771Srajstatic inline unsigned int 2544176771Srajtlb0_tableidx(vm_offset_t va, unsigned int way) 2545176771Sraj{ 2546176771Sraj unsigned int idx; 2547176771Sraj 2548176771Sraj idx = (way * TLB0_ENTRIES_PER_WAY); 2549176771Sraj idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2550176771Sraj return (idx); 2551176771Sraj} 2552176771Sraj 2553176771Sraj/* 2554176771Sraj * Write given entry to TLB0 hardware. 2555176771Sraj * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2556176771Sraj */ 2557176771Srajstatic void 2558176771Srajtlb0_write_entry(unsigned int idx, unsigned int way) 2559176771Sraj{ 2560176771Sraj u_int32_t mas0, mas7, nv; 2561176771Sraj 2562176771Sraj /* Clear high order RPN bits. */ 2563176771Sraj mas7 = 0; 2564176771Sraj 2565176771Sraj /* Preserve NV. */ 2566176771Sraj mas0 = mfspr(SPR_MAS0); 2567176771Sraj nv = mas0 & (TLB0_NWAYS - 1); 2568176771Sraj 2569176771Sraj /* Select entry. */ 2570176771Sraj mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way) | nv; 2571176771Sraj 2572176771Sraj //debugf("tlb0_write_entry: s (idx=%d way=%d mas0=0x%08x " 2573176771Sraj // "mas1=0x%08x mas2=0x%08x mas3=0x%08x)\n", 2574176771Sraj // idx, way, mas0, tlb0[idx].mas1, 2575176771Sraj // tlb0[idx].mas2, tlb0[idx].mas3); 2576176771Sraj 2577176771Sraj mtspr(SPR_MAS0, mas0); 2578176771Sraj __asm volatile("isync"); 2579176771Sraj mtspr(SPR_MAS1, tlb0[idx].mas1); 2580176771Sraj __asm volatile("isync"); 2581176771Sraj mtspr(SPR_MAS2, tlb0[idx].mas2); 2582176771Sraj __asm volatile("isync"); 2583176771Sraj mtspr(SPR_MAS3, tlb0[idx].mas3); 2584176771Sraj __asm volatile("isync"); 2585176771Sraj mtspr(SPR_MAS7, mas7); 2586176771Sraj __asm volatile("isync; tlbwe; isync; msync"); 2587176771Sraj 2588176771Sraj //debugf("tlb0_write_entry: e\n"); 2589176771Sraj} 2590176771Sraj 2591176771Sraj/* 2592176771Sraj * Invalidate TLB0 entry, clear correspondig tlb0 table element. 2593176771Sraj */ 2594176771Srajstatic void 2595176771Srajtlb0_inval_entry(vm_offset_t va, unsigned int way) 2596176771Sraj{ 2597176771Sraj int idx = tlb0_tableidx(va, way); 2598176771Sraj 2599176771Sraj //debugf("tlb0_inval_entry: s (va=0x%08x way=%d idx=%d)\n", 2600176771Sraj // va, way, idx); 2601176771Sraj 2602176771Sraj tlb0[idx].mas1 = 1 << MAS1_TSIZE_SHIFT; /* !MAS1_VALID */ 2603176771Sraj tlb0[idx].mas2 = va & MAS2_EPN; 2604176771Sraj tlb0[idx].mas3 = 0; 2605176771Sraj 2606176771Sraj tlb0_write_entry(idx, way); 2607176771Sraj 2608176771Sraj //debugf("tlb0_inval_entry: e\n"); 2609176771Sraj} 2610176771Sraj 2611176771Sraj/* 2612176771Sraj * Invalidate TLB0 entry that corresponds to pmap/va. 2613176771Sraj */ 2614176771Srajstatic void 2615176771Srajtlb0_flush_entry(pmap_t pmap, vm_offset_t va) 2616176771Sraj{ 2617176771Sraj int idx, way; 2618176771Sraj 2619176771Sraj //debugf("tlb0_flush_entry: s (pmap=0x%08x va=0x%08x)\n", 2620176771Sraj // (u_int32_t)pmap, va); 2621176771Sraj 2622176771Sraj mtx_lock_spin(&tlb0_mutex); 2623176771Sraj 2624176771Sraj /* Check all TLB0 ways. */ 2625176771Sraj for (way = 0; way < TLB0_NWAYS; way ++) { 2626176771Sraj idx = tlb0_tableidx(va, way); 2627176771Sraj 2628176771Sraj /* Invalidate only if entry matches va and pmap tid. */ 2629176771Sraj if (((MAS1_GETTID(tlb0[idx].mas1) == pmap->pm_tid) && 2630176771Sraj ((tlb0[idx].mas2 & MAS2_EPN) == va))) { 2631176771Sraj tlb0_inval_entry(va, way); 2632176771Sraj } 2633176771Sraj } 2634176771Sraj 2635176771Sraj mtx_unlock_spin(&tlb0_mutex); 2636176771Sraj 2637176771Sraj //debugf("tlb0_flush_entry: e\n"); 2638176771Sraj} 2639176771Sraj 2640176771Sraj/* Clean TLB0 hardware and tlb0[] table. */ 2641176771Srajstatic void 2642176771Srajtlb0_init(void) 2643176771Sraj{ 2644176771Sraj int entryidx, way; 2645176771Sraj 2646176771Sraj debugf("tlb0_init: TLB0_SIZE = %d TLB0_NWAYS = %d\n", 2647176771Sraj TLB0_SIZE, TLB0_NWAYS); 2648176771Sraj 2649176771Sraj mtx_lock_spin(&tlb0_mutex); 2650176771Sraj 2651176771Sraj for (way = 0; way < TLB0_NWAYS; way ++) { 2652176771Sraj for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2653176771Sraj tlb0_inval_entry(entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT, way); 2654176771Sraj } 2655176771Sraj } 2656176771Sraj 2657176771Sraj mtx_unlock_spin(&tlb0_mutex); 2658176771Sraj} 2659176771Sraj 2660176771Sraj#if 0 2661176771Sraj#if DEBUG 2662176771Sraj/* Print out tlb0 entries for given va. */ 2663176771Srajstatic void 2664176771Srajtlb0_print_tlbentries_va(vm_offset_t va) 2665176771Sraj{ 2666176771Sraj u_int32_t mas0, mas1, mas2, mas3, mas7; 2667176771Sraj int way, idx; 2668176771Sraj 2669176771Sraj debugf("TLB0 entries for va = 0x%08x:\n", va); 2670176771Sraj for (way = 0; way < TLB0_NWAYS; way ++) { 2671176771Sraj mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2672176771Sraj mtspr(SPR_MAS0, mas0); 2673176771Sraj __asm volatile("isync"); 2674176771Sraj 2675176771Sraj mas2 = va & MAS2_EPN; 2676176771Sraj mtspr(SPR_MAS2, mas2); 2677176771Sraj __asm volatile("isync; tlbre"); 2678176771Sraj 2679176771Sraj mas1 = mfspr(SPR_MAS1); 2680176771Sraj mas2 = mfspr(SPR_MAS2); 2681176771Sraj mas3 = mfspr(SPR_MAS3); 2682176771Sraj mas7 = mfspr(SPR_MAS7); 2683176771Sraj 2684176771Sraj idx = tlb0_tableidx(va, way); 2685176771Sraj tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2686176771Sraj } 2687176771Sraj} 2688176771Sraj 2689176771Sraj/* Print out contents of the MAS registers for each TLB0 entry */ 2690176771Srajstatic void 2691176771Srajtlb0_print_tlbentries(void) 2692176771Sraj{ 2693176771Sraj u_int32_t mas0, mas1, mas2, mas3, mas7; 2694176771Sraj int entryidx, way, idx; 2695176771Sraj 2696176771Sraj debugf("TLB0 entries:\n"); 2697176771Sraj for (way = 0; way < TLB0_NWAYS; way ++) { 2698176771Sraj for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2699176771Sraj 2700176771Sraj mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2701176771Sraj mtspr(SPR_MAS0, mas0); 2702176771Sraj __asm volatile("isync"); 2703176771Sraj 2704176771Sraj mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2705176771Sraj mtspr(SPR_MAS2, mas2); 2706176771Sraj 2707176771Sraj __asm volatile("isync; tlbre"); 2708176771Sraj 2709176771Sraj mas1 = mfspr(SPR_MAS1); 2710176771Sraj mas2 = mfspr(SPR_MAS2); 2711176771Sraj mas3 = mfspr(SPR_MAS3); 2712176771Sraj mas7 = mfspr(SPR_MAS7); 2713176771Sraj 2714176771Sraj idx = tlb0_tableidx(mas2, way); 2715176771Sraj tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2716176771Sraj } 2717176771Sraj } 2718176771Sraj} 2719176771Sraj 2720176771Sraj/* Print out kernel tlb0[] table. */ 2721176771Srajstatic void 2722176771Srajtlb0_print_entries(void) 2723176771Sraj{ 2724176771Sraj int i; 2725176771Sraj 2726176771Sraj debugf("tlb0[] table entries:\n"); 2727176771Sraj for (i = 0; i < TLB0_SIZE; i++) { 2728176771Sraj tlb_print_entry(i, tlb0[i].mas1, 2729176771Sraj tlb0[i].mas2, tlb0[i].mas3, 0); 2730176771Sraj } 2731176771Sraj} 2732176771Sraj#endif /* DEBUG */ 2733176771Sraj#endif 2734176771Sraj 2735176771Sraj/**************************************************************************/ 2736176771Sraj/* TLB1 handling */ 2737176771Sraj/**************************************************************************/ 2738176771Sraj/* 2739176771Sraj * Write given entry to TLB1 hardware. 2740176771Sraj * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2741176771Sraj */ 2742176771Srajstatic void 2743176771Srajtlb1_write_entry(unsigned int idx) 2744176771Sraj{ 2745176771Sraj u_int32_t mas0, mas7; 2746176771Sraj 2747176771Sraj //debugf("tlb1_write_entry: s\n"); 2748176771Sraj 2749176771Sraj /* Clear high order RPN bits */ 2750176771Sraj mas7 = 0; 2751176771Sraj 2752176771Sraj /* Select entry */ 2753176771Sraj mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2754176771Sraj //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2755176771Sraj 2756176771Sraj mtspr(SPR_MAS0, mas0); 2757176771Sraj __asm volatile("isync"); 2758176771Sraj mtspr(SPR_MAS1, tlb1[idx].mas1); 2759176771Sraj __asm volatile("isync"); 2760176771Sraj mtspr(SPR_MAS2, tlb1[idx].mas2); 2761176771Sraj __asm volatile("isync"); 2762176771Sraj mtspr(SPR_MAS3, tlb1[idx].mas3); 2763176771Sraj __asm volatile("isync"); 2764176771Sraj mtspr(SPR_MAS7, mas7); 2765176771Sraj __asm volatile("isync; tlbwe; isync; msync"); 2766176771Sraj 2767176771Sraj //debugf("tlb1_write_entry: e\n");; 2768176771Sraj} 2769176771Sraj 2770176771Sraj/* 2771176771Sraj * Return the largest uint value log such that 2^log <= num. 2772176771Sraj */ 2773176771Srajstatic unsigned int 2774176771Srajilog2(unsigned int num) 2775176771Sraj{ 2776176771Sraj int lz; 2777176771Sraj 2778176771Sraj __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2779176771Sraj return (31 - lz); 2780176771Sraj} 2781176771Sraj 2782176771Sraj/* 2783176771Sraj * Convert TLB TSIZE value to mapped region size. 2784176771Sraj */ 2785176771Srajstatic vm_size_t 2786176771Srajtsize2size(unsigned int tsize) 2787176771Sraj{ 2788176771Sraj 2789176771Sraj /* 2790176771Sraj * size = 4^tsize KB 2791176771Sraj * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2792176771Sraj */ 2793176771Sraj 2794176771Sraj return ((1 << (2 * tsize)) * 1024); 2795176771Sraj} 2796176771Sraj 2797176771Sraj/* 2798176771Sraj * Convert region size (must be power of 4) to TLB TSIZE value. 2799176771Sraj */ 2800176771Srajstatic unsigned int 2801176771Srajsize2tsize(vm_size_t size) 2802176771Sraj{ 2803176771Sraj 2804176771Sraj /* 2805176771Sraj * tsize = log2(size) / 2 - 5 2806176771Sraj */ 2807176771Sraj 2808176771Sraj return (ilog2(size) / 2 - 5); 2809176771Sraj} 2810176771Sraj 2811176771Sraj/* 2812176771Sraj * Setup entry in a sw tlb1 table, write entry to TLB1 hardware. 2813176771Sraj * This routine is used for low level operations on the TLB1, 2814176771Sraj * for creating temporaray as well as permanent mappings (tlb_set_entry). 2815176771Sraj * 2816176771Sraj * We assume kernel mappings only, thus all entries created have supervisor 2817176771Sraj * permission bits set nad user permission bits cleared. 2818176771Sraj * 2819176771Sraj * Provided mapping size must be a power of 4. 2820176771Sraj * Mapping flags must be a combination of MAS2_[WIMG]. 2821176771Sraj * Entry TID is set to _tid which must not exceed 8 bit value. 2822176771Sraj * Entry TS is set to either 0 or MAS1_TS based on provided _ts. 2823176771Sraj */ 2824176771Srajstatic void 2825176771Sraj__tlb1_set_entry(unsigned int idx, vm_offset_t va, vm_offset_t pa, 2826176771Sraj vm_size_t size, u_int32_t flags, unsigned int _tid, unsigned int _ts) 2827176771Sraj{ 2828176771Sraj int tsize; 2829176771Sraj u_int32_t ts, tid; 2830176771Sraj 2831176771Sraj //debugf("__tlb1_set_entry: s (idx = %d va = 0x%08x pa = 0x%08x " 2832176771Sraj // "size = 0x%08x flags = 0x%08x _tid = %d _ts = %d\n", 2833176771Sraj // idx, va, pa, size, flags, _tid, _ts); 2834176771Sraj 2835176771Sraj /* Convert size to TSIZE */ 2836176771Sraj tsize = size2tsize(size); 2837176771Sraj //debugf("__tlb1_set_entry: tsize = %d\n", tsize); 2838176771Sraj 2839176771Sraj tid = (_tid << MAS1_TID_SHIFT) & MAS1_TID_MASK; 2840176771Sraj ts = (_ts) ? MAS1_TS : 0; 2841176771Sraj tlb1[idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 2842176771Sraj tlb1[idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 2843176771Sraj 2844176771Sraj tlb1[idx].mas2 = (va & MAS2_EPN) | flags; 2845176771Sraj 2846176771Sraj /* Set supervisor rwx permission bits */ 2847176771Sraj tlb1[idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 2848176771Sraj 2849176771Sraj //debugf("__tlb1_set_entry: mas1 = %08x mas2 = %08x mas3 = 0x%08x\n", 2850176771Sraj // tlb1[idx].mas1, tlb1[idx].mas2, tlb1[idx].mas3); 2851176771Sraj 2852176771Sraj tlb1_write_entry(idx); 2853176771Sraj //debugf("__tlb1_set_entry: e\n"); 2854176771Sraj} 2855176771Sraj 2856176771Sraj/* 2857176771Sraj * Register permanent kernel mapping in TLB1. 2858176771Sraj * 2859176771Sraj * Entries are created starting from index 0 (current free entry is 2860176771Sraj * kept in tlb1_idx) and are not supposed to be invalidated. 2861176771Sraj */ 2862176771Srajstatic int 2863176771Srajtlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, u_int32_t flags) 2864176771Sraj{ 2865176771Sraj //debugf("tlb1_set_entry: s (tlb1_idx = %d va = 0x%08x pa = 0x%08x " 2866176771Sraj // "size = 0x%08x flags = 0x%08x\n", 2867176771Sraj // tlb1_idx, va, pa, size, flags); 2868176771Sraj 2869176771Sraj if (tlb1_idx >= TLB1_SIZE) { 2870176771Sraj //debugf("tlb1_set_entry: e (tlb1 full!)\n"); 2871176771Sraj return (-1); 2872176771Sraj } 2873176771Sraj 2874176771Sraj /* TS = 0, TID = 0 */ 2875176771Sraj __tlb1_set_entry(tlb1_idx++, va, pa, size, flags, KERNEL_TID, 0); 2876176771Sraj //debugf("tlb1_set_entry: e\n"); 2877176771Sraj return (0); 2878176771Sraj} 2879176771Sraj 2880176771Sraj/* 2881176771Sraj * Invalidate TLB1 entry, clear correspondig tlb1 table element. 2882176771Sraj * This routine is used to clear temporary entries created 2883176771Sraj * early in a locore.S or through the use of __tlb1_set_entry(). 2884176771Sraj */ 2885176771Srajvoid 2886176771Srajtlb1_inval_entry(unsigned int idx) 2887176771Sraj{ 2888176771Sraj vm_offset_t va; 2889176771Sraj 2890176771Sraj va = tlb1[idx].mas2 & MAS2_EPN; 2891176771Sraj 2892176771Sraj tlb1[idx].mas1 = 0; /* !MAS1_VALID */ 2893176771Sraj tlb1[idx].mas2 = 0; 2894176771Sraj tlb1[idx].mas3 = 0; 2895176771Sraj 2896176771Sraj tlb1_write_entry(idx); 2897176771Sraj} 2898176771Sraj 2899176771Srajstatic int 2900176771Srajtlb1_entry_size_cmp(const void *a, const void *b) 2901176771Sraj{ 2902176771Sraj const vm_size_t *sza; 2903176771Sraj const vm_size_t *szb; 2904176771Sraj 2905176771Sraj sza = a; 2906176771Sraj szb = b; 2907176771Sraj if (*sza > *szb) 2908176771Sraj return (-1); 2909176771Sraj else if (*sza < *szb) 2910176771Sraj return (1); 2911176771Sraj else 2912176771Sraj return (0); 2913176771Sraj} 2914176771Sraj 2915176771Sraj/* 2916176771Sraj * Mapin contiguous RAM region into the TLB1 using maximum of 2917176771Sraj * KERNEL_REGION_MAX_TLB_ENTRIES entries. 2918176771Sraj * 2919176771Sraj * If necessarry round up last entry size and return total size 2920176771Sraj * used by all allocated entries. 2921176771Sraj */ 2922176771Srajvm_size_t 2923176771Srajtlb1_mapin_region(vm_offset_t va, vm_offset_t pa, vm_size_t size) 2924176771Sraj{ 2925176771Sraj vm_size_t entry_size[KERNEL_REGION_MAX_TLB_ENTRIES]; 2926176771Sraj vm_size_t mapped_size, sz, esz; 2927176771Sraj unsigned int log; 2928176771Sraj int i; 2929176771Sraj 2930176771Sraj debugf("tlb1_mapin_region:\n"); 2931176771Sraj debugf(" region size = 0x%08x va = 0x%08x pa = 0x%08x\n", size, va, pa); 2932176771Sraj 2933176771Sraj mapped_size = 0; 2934176771Sraj sz = size; 2935176771Sraj memset(entry_size, 0, sizeof(entry_size)); 2936176771Sraj 2937176771Sraj /* Calculate entry sizes. */ 2938176771Sraj for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES && sz > 0; i++) { 2939176771Sraj 2940176771Sraj /* Largest region that is power of 4 and fits within size */ 2941176771Sraj log = ilog2(sz)/2; 2942176771Sraj esz = 1 << (2 * log); 2943176771Sraj 2944176771Sraj /* Minimum region size is 4KB */ 2945176771Sraj if (esz < (1 << 12)) 2946176771Sraj esz = 1 << 12; 2947176771Sraj 2948176771Sraj /* If this is last entry cover remaining size. */ 2949176771Sraj if (i == KERNEL_REGION_MAX_TLB_ENTRIES - 1) { 2950176771Sraj while (esz < sz) 2951176771Sraj esz = esz << 2; 2952176771Sraj } 2953176771Sraj 2954176771Sraj entry_size[i] = esz; 2955176771Sraj mapped_size += esz; 2956176771Sraj if (esz < sz) 2957176771Sraj sz -= esz; 2958176771Sraj else 2959176771Sraj sz = 0; 2960176771Sraj } 2961176771Sraj 2962176771Sraj /* Sort entry sizes, required to get proper entry address alignment. */ 2963176771Sraj qsort(entry_size, KERNEL_REGION_MAX_TLB_ENTRIES, 2964176771Sraj sizeof(vm_size_t), tlb1_entry_size_cmp); 2965176771Sraj 2966176771Sraj /* Load TLB1 entries. */ 2967176771Sraj for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES; i++) { 2968176771Sraj esz = entry_size[i]; 2969176771Sraj if (!esz) 2970176771Sraj break; 2971176771Sraj debugf(" entry %d: sz = 0x%08x (va = 0x%08x pa = 0x%08x)\n", 2972176771Sraj tlb1_idx, esz, va, pa); 2973176771Sraj tlb1_set_entry(va, pa, esz, _TLB_ENTRY_MEM); 2974176771Sraj 2975176771Sraj va += esz; 2976176771Sraj pa += esz; 2977176771Sraj } 2978176771Sraj 2979176771Sraj debugf(" mapped size 0x%08x (wasted space 0x%08x)\n", 2980176771Sraj mapped_size, mapped_size - size); 2981176771Sraj 2982176771Sraj return (mapped_size); 2983176771Sraj} 2984176771Sraj 2985176771Sraj/* 2986176771Sraj * TLB1 initialization routine, to be called after the very first 2987176771Sraj * assembler level setup done in locore.S. 2988176771Sraj */ 2989176771Srajvoid 2990176771Srajtlb1_init(vm_offset_t ccsrbar) 2991176771Sraj{ 2992176771Sraj uint32_t mas0; 2993176771Sraj 2994176771Sraj /* TBL1[1] is used to map the kernel. Save that entry. */ 2995176771Sraj mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(1); 2996176771Sraj mtspr(SPR_MAS0, mas0); 2997176771Sraj __asm __volatile("isync; tlbre"); 2998176771Sraj 2999176771Sraj tlb1[1].mas1 = mfspr(SPR_MAS1); 3000176771Sraj tlb1[1].mas2 = mfspr(SPR_MAS2); 3001176771Sraj tlb1[1].mas3 = mfspr(SPR_MAS3); 3002176771Sraj 3003176771Sraj /* Mapin CCSRBAR in TLB1[0] */ 3004176771Sraj __tlb1_set_entry(0, CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, 3005176771Sraj _TLB_ENTRY_IO, KERNEL_TID, 0); 3006176771Sraj 3007176771Sraj /* Setup TLB miss defaults */ 3008176771Sraj set_mas4_defaults(); 3009176771Sraj 3010176771Sraj /* Reset next available TLB1 entry index. */ 3011176771Sraj tlb1_idx = 2; 3012176771Sraj} 3013176771Sraj 3014176771Sraj/* 3015176771Sraj * Setup MAS4 defaults. 3016176771Sraj * These values are loaded to MAS0-2 on a TLB miss. 3017176771Sraj */ 3018176771Srajstatic void 3019176771Srajset_mas4_defaults(void) 3020176771Sraj{ 3021176771Sraj u_int32_t mas4; 3022176771Sraj 3023176771Sraj /* Defaults: TLB0, PID0, TSIZED=4K */ 3024176771Sraj mas4 = MAS4_TLBSELD0; 3025176771Sraj mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3026176771Sraj 3027176771Sraj mtspr(SPR_MAS4, mas4); 3028176771Sraj __asm volatile("isync"); 3029176771Sraj} 3030176771Sraj 3031176771Sraj/* 3032176771Sraj * Print out contents of the MAS registers for each TLB1 entry 3033176771Sraj */ 3034176771Srajvoid 3035176771Srajtlb1_print_tlbentries(void) 3036176771Sraj{ 3037176771Sraj u_int32_t mas0, mas1, mas2, mas3, mas7; 3038176771Sraj int i; 3039176771Sraj 3040176771Sraj debugf("TLB1 entries:\n"); 3041176771Sraj for (i = 0; i < TLB1_SIZE; i++) { 3042176771Sraj 3043176771Sraj mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3044176771Sraj mtspr(SPR_MAS0, mas0); 3045176771Sraj 3046176771Sraj __asm volatile("isync; tlbre"); 3047176771Sraj 3048176771Sraj mas1 = mfspr(SPR_MAS1); 3049176771Sraj mas2 = mfspr(SPR_MAS2); 3050176771Sraj mas3 = mfspr(SPR_MAS3); 3051176771Sraj mas7 = mfspr(SPR_MAS7); 3052176771Sraj 3053176771Sraj tlb_print_entry(i, mas1, mas2, mas3, mas7); 3054176771Sraj } 3055176771Sraj} 3056176771Sraj 3057176771Sraj/* 3058176771Sraj * Print out contents of the in-ram tlb1 table. 3059176771Sraj */ 3060176771Srajvoid 3061176771Srajtlb1_print_entries(void) 3062176771Sraj{ 3063176771Sraj int i; 3064176771Sraj 3065176771Sraj debugf("tlb1[] table entries:\n"); 3066176771Sraj for (i = 0; i < TLB1_SIZE; i++) 3067176771Sraj tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3068176771Sraj} 3069176771Sraj 3070176771Sraj/* 3071176771Sraj * Return 0 if the physical IO range is encompassed by one of the 3072176771Sraj * the TLB1 entries, otherwise return related error code. 3073176771Sraj */ 3074176771Srajstatic int 3075176771Srajtlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3076176771Sraj{ 3077176771Sraj u_int32_t prot; 3078176771Sraj vm_paddr_t pa_start; 3079176771Sraj vm_paddr_t pa_end; 3080176771Sraj unsigned int entry_tsize; 3081176771Sraj vm_size_t entry_size; 3082176771Sraj 3083176771Sraj *va = (vm_offset_t)NULL; 3084176771Sraj 3085176771Sraj /* Skip invalid entries */ 3086176771Sraj if (!(tlb1[i].mas1 & MAS1_VALID)) 3087176771Sraj return (EINVAL); 3088176771Sraj 3089176771Sraj /* 3090176771Sraj * The entry must be cache-inhibited, guarded, and r/w 3091176771Sraj * so it can function as an i/o page 3092176771Sraj */ 3093176771Sraj prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3094176771Sraj if (prot != (MAS2_I | MAS2_G)) 3095176771Sraj return (EPERM); 3096176771Sraj 3097176771Sraj prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3098176771Sraj if (prot != (MAS3_SR | MAS3_SW)) 3099176771Sraj return (EPERM); 3100176771Sraj 3101176771Sraj /* The address should be within the entry range. */ 3102176771Sraj entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3103176771Sraj KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3104176771Sraj 3105176771Sraj entry_size = tsize2size(entry_tsize); 3106176771Sraj pa_start = tlb1[i].mas3 & MAS3_RPN; 3107176771Sraj pa_end = pa_start + entry_size - 1; 3108176771Sraj 3109176771Sraj if ((pa < pa_start) || ((pa + size) > pa_end)) 3110176771Sraj return (ERANGE); 3111176771Sraj 3112176771Sraj /* Return virtual address of this mapping. */ 3113176771Sraj *va = (tlb1[i].mas2 & MAS2_EPN) + (pa - pa_start); 3114176771Sraj return (0); 3115176771Sraj} 3116