pcrtc.c revision 98736
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $FreeBSD: head/sys/pc98/cbus/pcrtc.c 98736 2002-06-24 08:04:47Z kato $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51/* 52 * modified for PC98 by Kakefuda 53 */ 54 55#include "opt_clock.h" 56#include "opt_isa.h" 57#include "opt_mca.h" 58 59#include <sys/param.h> 60#include <sys/systm.h> 61#include <sys/bus.h> 62#include <sys/lock.h> 63#include <sys/mutex.h> 64#include <sys/proc.h> 65#include <sys/time.h> 66#include <sys/timetc.h> 67#include <sys/kernel.h> 68#include <sys/sysctl.h> 69#include <sys/cons.h> 70#include <sys/power.h> 71 72#include <machine/clock.h> 73#ifdef CLK_CALIBRATION_LOOP 74#endif 75#include <machine/cputypes.h> 76#include <machine/frame.h> 77#include <machine/limits.h> 78#include <machine/md_var.h> 79#include <machine/psl.h> 80#ifdef APIC_IO 81#include <machine/segments.h> 82#endif 83#if defined(SMP) || defined(APIC_IO) 84#include <machine/smp.h> 85#endif /* SMP || APIC_IO */ 86#include <machine/specialreg.h> 87 88#include <i386/isa/icu.h> 89#ifdef PC98 90#include <pc98/pc98/pc98.h> 91#include <pc98/pc98/pc98_machdep.h> 92#include <i386/isa/isa_device.h> 93#else 94#include <i386/isa/isa.h> 95#include <isa/rtc.h> 96#endif 97#ifdef DEV_ISA 98#include <isa/isavar.h> 99#endif 100#include <i386/isa/timerreg.h> 101 102#include <i386/isa/intr_machdep.h> 103 104#ifdef DEV_MCA 105#include <i386/isa/mca_machdep.h> 106#endif 107 108#ifdef APIC_IO 109#include <i386/isa/intr_machdep.h> 110/* The interrupt triggered by the 8254 (timer) chip */ 111int apic_8254_intr; 112static u_long read_intr_count(int vec); 113static void setup_8254_mixed_mode(void); 114#endif 115 116/* 117 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 118 * can use a simple formula for leap years. 119 */ 120#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 121#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 122 123#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 124 125/* 126 * Time in timer cycles that it takes for microtime() to disable interrupts 127 * and latch the count. microtime() currently uses "cli; outb ..." so it 128 * normally takes less than 2 timer cycles. Add a few for cache misses. 129 * Add a few more to allow for latency in bogus calls to microtime() with 130 * interrupts already disabled. 131 */ 132#define TIMER0_LATCH_COUNT 20 133 134/* 135 * Maximum frequency that we are willing to allow for timer0. Must be 136 * low enough to guarantee that the timer interrupt handler returns 137 * before the next timer interrupt. 138 */ 139#define TIMER0_MAX_FREQ 20000 140 141int adjkerntz; /* local offset from GMT in seconds */ 142int clkintr_pending; 143int disable_rtc_set; /* disable resettodr() if != 0 */ 144int statclock_disable; 145#ifndef TIMER_FREQ 146#ifdef PC98 147#define TIMER_FREQ 2457600 148#else /* IBM-PC */ 149#define TIMER_FREQ 1193182 150#endif /* PC98 */ 151#endif 152u_int timer_freq = TIMER_FREQ; 153int timer0_max_count; 154u_int tsc_freq; 155int tsc_is_broken; 156u_int tsc_present; 157int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 158struct mtx clock_lock; 159 160static int beeping = 0; 161static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 162static u_int hardclock_max_count; 163static u_int32_t i8254_lastcount; 164static u_int32_t i8254_offset; 165static int i8254_ticked; 166/* 167 * XXX new_function and timer_func should not handle clockframes, but 168 * timer_func currently needs to hold hardclock to handle the 169 * timer0_state == 0 case. We should use inthand_add()/inthand_remove() 170 * to switch between clkintr() and a slightly different timerintr(). 171 */ 172static void (*new_function)(struct clockframe *frame); 173static u_int new_rate; 174#ifndef PC98 175static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 176static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 177#endif 178static u_int timer0_prescaler_count; 179 180/* Values for timerX_state: */ 181#define RELEASED 0 182#define RELEASE_PENDING 1 183#define ACQUIRED 2 184#define ACQUIRE_PENDING 3 185 186static u_char timer0_state; 187#ifdef PC98 188static u_char timer1_state; 189#endif 190static u_char timer2_state; 191static void (*timer_func)(struct clockframe *frame) = hardclock; 192#ifdef PC98 193static void rtc_serialcombit(int); 194static void rtc_serialcom(int); 195static int rtc_inb(void); 196static void rtc_outb(int); 197#endif 198 199static unsigned i8254_get_timecount(struct timecounter *tc); 200static unsigned tsc_get_timecount(struct timecounter *tc); 201static void set_timer_freq(u_int freq, int intr_freq); 202 203static struct timecounter tsc_timecounter = { 204 tsc_get_timecount, /* get_timecount */ 205 0, /* no poll_pps */ 206 ~0u, /* counter_mask */ 207 0, /* frequency */ 208 "TSC" /* name */ 209}; 210 211static struct timecounter i8254_timecounter = { 212 i8254_get_timecount, /* get_timecount */ 213 0, /* no poll_pps */ 214 ~0u, /* counter_mask */ 215 0, /* frequency */ 216 "i8254" /* name */ 217}; 218 219static void 220clkintr(struct clockframe frame) 221{ 222 223 if (timecounter->tc_get_timecount == i8254_get_timecount) { 224 mtx_lock_spin(&clock_lock); 225 if (i8254_ticked) 226 i8254_ticked = 0; 227 else { 228 i8254_offset += timer0_max_count; 229 i8254_lastcount = 0; 230 } 231 clkintr_pending = 0; 232 mtx_unlock_spin(&clock_lock); 233 } 234 timer_func(&frame); 235#ifdef SMP 236 if (timer_func == hardclock) 237 forward_hardclock(); 238#endif 239 switch (timer0_state) { 240 241 case RELEASED: 242 break; 243 244 case ACQUIRED: 245 if ((timer0_prescaler_count += timer0_max_count) 246 >= hardclock_max_count) { 247 timer0_prescaler_count -= hardclock_max_count; 248 hardclock(&frame); 249#ifdef SMP 250 forward_hardclock(); 251#endif 252 } 253 break; 254 255 case ACQUIRE_PENDING: 256 mtx_lock_spin(&clock_lock); 257 i8254_offset = i8254_get_timecount(NULL); 258 i8254_lastcount = 0; 259 timer0_max_count = TIMER_DIV(new_rate); 260 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 261 outb(TIMER_CNTR0, timer0_max_count & 0xff); 262 outb(TIMER_CNTR0, timer0_max_count >> 8); 263 mtx_unlock_spin(&clock_lock); 264 timer_func = new_function; 265 timer0_state = ACQUIRED; 266 break; 267 268 case RELEASE_PENDING: 269 if ((timer0_prescaler_count += timer0_max_count) 270 >= hardclock_max_count) { 271 mtx_lock_spin(&clock_lock); 272 i8254_offset = i8254_get_timecount(NULL); 273 i8254_lastcount = 0; 274 timer0_max_count = hardclock_max_count; 275 outb(TIMER_MODE, 276 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 277 outb(TIMER_CNTR0, timer0_max_count & 0xff); 278 outb(TIMER_CNTR0, timer0_max_count >> 8); 279 mtx_unlock_spin(&clock_lock); 280 timer0_prescaler_count = 0; 281 timer_func = hardclock; 282 timer0_state = RELEASED; 283 hardclock(&frame); 284#ifdef SMP 285 forward_hardclock(); 286#endif 287 } 288 break; 289 } 290#ifdef DEV_MCA 291 /* Reset clock interrupt by asserting bit 7 of port 0x61 */ 292 if (MCA_system) 293 outb(0x61, inb(0x61) | 0x80); 294#endif 295} 296 297/* 298 * The acquire and release functions must be called at ipl >= splclock(). 299 */ 300int 301acquire_timer0(int rate, void (*function)(struct clockframe *frame)) 302{ 303 static int old_rate; 304 305 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 306 return (-1); 307 switch (timer0_state) { 308 309 case RELEASED: 310 timer0_state = ACQUIRE_PENDING; 311 break; 312 313 case RELEASE_PENDING: 314 if (rate != old_rate) 315 return (-1); 316 /* 317 * The timer has been released recently, but is being 318 * re-acquired before the release completed. In this 319 * case, we simply reclaim it as if it had not been 320 * released at all. 321 */ 322 timer0_state = ACQUIRED; 323 break; 324 325 default: 326 return (-1); /* busy */ 327 } 328 new_function = function; 329 old_rate = new_rate = rate; 330 return (0); 331} 332 333#ifdef PC98 334int 335acquire_timer1(int mode) 336{ 337 338 if (timer1_state != RELEASED) 339 return (-1); 340 timer1_state = ACQUIRED; 341 342 /* 343 * This access to the timer registers is as atomic as possible 344 * because it is a single instruction. We could do better if we 345 * knew the rate. Use of splclock() limits glitches to 10-100us, 346 * and this is probably good enough for timer2, so we aren't as 347 * careful with it as with timer0. 348 */ 349 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 350 351 return (0); 352} 353#endif 354 355int 356acquire_timer2(int mode) 357{ 358 359 if (timer2_state != RELEASED) 360 return (-1); 361 timer2_state = ACQUIRED; 362 363 /* 364 * This access to the timer registers is as atomic as possible 365 * because it is a single instruction. We could do better if we 366 * knew the rate. Use of splclock() limits glitches to 10-100us, 367 * and this is probably good enough for timer2, so we aren't as 368 * careful with it as with timer0. 369 */ 370 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 371 372 return (0); 373} 374 375int 376release_timer0() 377{ 378 switch (timer0_state) { 379 380 case ACQUIRED: 381 timer0_state = RELEASE_PENDING; 382 break; 383 384 case ACQUIRE_PENDING: 385 /* Nothing happened yet, release quickly. */ 386 timer0_state = RELEASED; 387 break; 388 389 default: 390 return (-1); 391 } 392 return (0); 393} 394 395#ifdef PC98 396int 397release_timer1() 398{ 399 400 if (timer1_state != ACQUIRED) 401 return (-1); 402 timer1_state = RELEASED; 403 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 404 return (0); 405} 406#endif 407 408int 409release_timer2() 410{ 411 412 if (timer2_state != ACQUIRED) 413 return (-1); 414 timer2_state = RELEASED; 415 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 416 return (0); 417} 418 419#ifndef PC98 420/* 421 * This routine receives statistical clock interrupts from the RTC. 422 * As explained above, these occur at 128 interrupts per second. 423 * When profiling, we receive interrupts at a rate of 1024 Hz. 424 * 425 * This does not actually add as much overhead as it sounds, because 426 * when the statistical clock is active, the hardclock driver no longer 427 * needs to keep (inaccurate) statistics on its own. This decouples 428 * statistics gathering from scheduling interrupts. 429 * 430 * The RTC chip requires that we read status register C (RTC_INTR) 431 * to acknowledge an interrupt, before it will generate the next one. 432 * Under high interrupt load, rtcintr() can be indefinitely delayed and 433 * the clock can tick immediately after the read from RTC_INTR. In this 434 * case, the mc146818A interrupt signal will not drop for long enough 435 * to register with the 8259 PIC. If an interrupt is missed, the stat 436 * clock will halt, considerably degrading system performance. This is 437 * why we use 'while' rather than a more straightforward 'if' below. 438 * Stat clock ticks can still be lost, causing minor loss of accuracy 439 * in the statistics, but the stat clock will no longer stop. 440 */ 441static void 442rtcintr(struct clockframe frame) 443{ 444 while (rtcin(RTC_INTR) & RTCIR_PERIOD) { 445 statclock(&frame); 446#ifdef SMP 447 forward_statclock(); 448#endif 449 } 450} 451 452#include "opt_ddb.h" 453#ifdef DDB 454#include <ddb/ddb.h> 455 456DB_SHOW_COMMAND(rtc, rtc) 457{ 458 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 459 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 460 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 461 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 462} 463#endif /* DDB */ 464#endif /* for PC98 */ 465 466static int 467getit(void) 468{ 469 int high, low; 470 471 mtx_lock_spin(&clock_lock); 472 473 /* Select timer0 and latch counter value. */ 474 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 475 476 low = inb(TIMER_CNTR0); 477 high = inb(TIMER_CNTR0); 478 479 mtx_unlock_spin(&clock_lock); 480 return ((high << 8) | low); 481} 482 483/* 484 * Wait "n" microseconds. 485 * Relies on timer 1 counting down from (timer_freq / hz) 486 * Note: timer had better have been programmed before this is first used! 487 */ 488void 489DELAY(int n) 490{ 491 int delta, prev_tick, tick, ticks_left; 492 493#ifdef DELAYDEBUG 494 int getit_calls = 1; 495 int n1; 496 static int state = 0; 497 498 if (state == 0) { 499 state = 1; 500 for (n1 = 1; n1 <= 10000000; n1 *= 10) 501 DELAY(n1); 502 state = 2; 503 } 504 if (state == 1) 505 printf("DELAY(%d)...", n); 506#endif 507 /* 508 * Guard against the timer being uninitialized if we are called 509 * early for console i/o. 510 */ 511 if (timer0_max_count == 0) 512 set_timer_freq(timer_freq, hz); 513 514 /* 515 * Read the counter first, so that the rest of the setup overhead is 516 * counted. Guess the initial overhead is 20 usec (on most systems it 517 * takes about 1.5 usec for each of the i/o's in getit(). The loop 518 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 519 * multiplications and divisions to scale the count take a while). 520 */ 521 prev_tick = getit(); 522 n -= 0; /* XXX actually guess no initial overhead */ 523 /* 524 * Calculate (n * (timer_freq / 1e6)) without using floating point 525 * and without any avoidable overflows. 526 */ 527 if (n <= 0) 528 ticks_left = 0; 529 else if (n < 256) 530 /* 531 * Use fixed point to avoid a slow division by 1000000. 532 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 533 * 2^15 is the first power of 2 that gives exact results 534 * for n between 0 and 256. 535 */ 536 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 537 else 538 /* 539 * Don't bother using fixed point, although gcc-2.7.2 540 * generates particularly poor code for the long long 541 * division, since even the slow way will complete long 542 * before the delay is up (unless we're interrupted). 543 */ 544 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 545 / 1000000; 546 547 while (ticks_left > 0) { 548 tick = getit(); 549#ifdef DELAYDEBUG 550 ++getit_calls; 551#endif 552 delta = prev_tick - tick; 553 prev_tick = tick; 554 if (delta < 0) { 555 delta += timer0_max_count; 556 /* 557 * Guard against timer0_max_count being wrong. 558 * This shouldn't happen in normal operation, 559 * but it may happen if set_timer_freq() is 560 * traced. 561 */ 562 if (delta < 0) 563 delta = 0; 564 } 565 ticks_left -= delta; 566 } 567#ifdef DELAYDEBUG 568 if (state == 1) 569 printf(" %d calls to getit() at %d usec each\n", 570 getit_calls, (n + 5) / getit_calls); 571#endif 572} 573 574static void 575sysbeepstop(void *chan) 576{ 577#ifdef PC98 /* PC98 */ 578 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 579 release_timer1(); 580#else 581 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 582 release_timer2(); 583#endif 584 beeping = 0; 585} 586 587int 588sysbeep(int pitch, int period) 589{ 590 int x = splclock(); 591 592#ifdef PC98 593 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 594 if (!beeping) { 595 /* Something else owns it. */ 596 splx(x); 597 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 598 } 599 disable_intr(); 600 outb(0x3fdb, pitch); 601 outb(0x3fdb, (pitch>>8)); 602 enable_intr(); 603 if (!beeping) { 604 /* enable counter1 output to speaker */ 605 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 606 beeping = period; 607 timeout(sysbeepstop, (void *)NULL, period); 608 } 609#else 610 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 611 if (!beeping) { 612 /* Something else owns it. */ 613 splx(x); 614 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 615 } 616 mtx_lock_spin(&clock_lock); 617 outb(TIMER_CNTR2, pitch); 618 outb(TIMER_CNTR2, (pitch>>8)); 619 mtx_unlock_spin(&clock_lock); 620 if (!beeping) { 621 /* enable counter2 output to speaker */ 622 outb(IO_PPI, inb(IO_PPI) | 3); 623 beeping = period; 624 timeout(sysbeepstop, (void *)NULL, period); 625 } 626#endif 627 splx(x); 628 return (0); 629} 630 631#ifndef PC98 632/* 633 * RTC support routines 634 */ 635 636int 637rtcin(reg) 638 int reg; 639{ 640 int s; 641 u_char val; 642 643 s = splhigh(); 644 outb(IO_RTC, reg); 645 inb(0x84); 646 val = inb(IO_RTC + 1); 647 inb(0x84); 648 splx(s); 649 return (val); 650} 651 652static __inline void 653writertc(u_char reg, u_char val) 654{ 655 int s; 656 657 s = splhigh(); 658 inb(0x84); 659 outb(IO_RTC, reg); 660 inb(0x84); 661 outb(IO_RTC + 1, val); 662 inb(0x84); /* XXX work around wrong order in rtcin() */ 663 splx(s); 664} 665 666static __inline int 667readrtc(int port) 668{ 669 return(bcd2bin(rtcin(port))); 670} 671#endif 672 673#ifdef PC98 674unsigned int delaycount; 675#define FIRST_GUESS 0x2000 676static void findcpuspeed(void) 677{ 678 int i; 679 int remainder; 680 681 /* Put counter in count down mode */ 682 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 683 outb(TIMER_CNTR0, 0xff); 684 outb(TIMER_CNTR0, 0xff); 685 for (i = FIRST_GUESS; i; i--) 686 ; 687 remainder = getit(); 688 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 689} 690#endif 691 692#ifdef PC98 693static u_int 694calibrate_clocks(void) 695{ 696 int timeout; 697 u_int count, prev_count, tot_count; 698 u_short sec, start_sec; 699 700 if (bootverbose) 701 printf("Calibrating clock(s) ... "); 702 /* Check ARTIC. */ 703 if (!(PC98_SYSTEM_PARAMETER(0x458) & 0x80) && 704 !(PC98_SYSTEM_PARAMETER(0x45b) & 0x04)) 705 goto fail; 706 timeout = 100000000; 707 708 /* Read the ARTIC. */ 709 sec = inw(0x5e); 710 711 /* Wait for the ARTIC to changes. */ 712 start_sec = sec; 713 for (;;) { 714 sec = inw(0x5e); 715 if (sec != start_sec) 716 break; 717 if (--timeout == 0) 718 goto fail; 719 } 720 prev_count = getit(); 721 if (prev_count == 0 || prev_count > timer0_max_count) 722 goto fail; 723 tot_count = 0; 724 725 if (tsc_present) 726 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 727 start_sec = sec; 728 for (;;) { 729 sec = inw(0x5e); 730 count = getit(); 731 if (count == 0 || count > timer0_max_count) 732 goto fail; 733 if (count > prev_count) 734 tot_count += prev_count - (count - timer0_max_count); 735 else 736 tot_count += prev_count - count; 737 prev_count = count; 738 if ((sec == start_sec + 1200) || 739 (sec < start_sec && 740 (u_int)sec + 0x10000 == (u_int)start_sec + 1200)) 741 break; 742 if (--timeout == 0) 743 goto fail; 744 } 745 /* 746 * Read the cpu cycle counter. The timing considerations are 747 * similar to those for the i8254 clock. 748 */ 749 if (tsc_present) 750 tsc_freq = rdtsc(); 751 752 if (bootverbose) { 753 if (tsc_present) 754 printf("TSC clock: %u Hz, ", tsc_freq); 755 printf("i8254 clock: %u Hz\n", tot_count); 756 } 757 return (tot_count); 758 759fail: 760 if (bootverbose) 761 printf("failed, using default i8254 clock of %u Hz\n", 762 timer_freq); 763 return (timer_freq); 764} 765#else 766static u_int 767calibrate_clocks(void) 768{ 769 u_int64_t old_tsc; 770 u_int count, prev_count, tot_count; 771 int sec, start_sec, timeout; 772 773 if (bootverbose) 774 printf("Calibrating clock(s) ... "); 775 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 776 goto fail; 777 timeout = 100000000; 778 779 /* Read the mc146818A seconds counter. */ 780 for (;;) { 781 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 782 sec = rtcin(RTC_SEC); 783 break; 784 } 785 if (--timeout == 0) 786 goto fail; 787 } 788 789 /* Wait for the mC146818A seconds counter to change. */ 790 start_sec = sec; 791 for (;;) { 792 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 793 sec = rtcin(RTC_SEC); 794 if (sec != start_sec) 795 break; 796 } 797 if (--timeout == 0) 798 goto fail; 799 } 800 801 /* Start keeping track of the i8254 counter. */ 802 prev_count = getit(); 803 if (prev_count == 0 || prev_count > timer0_max_count) 804 goto fail; 805 tot_count = 0; 806 807 if (tsc_present) 808 old_tsc = rdtsc(); 809 else 810 old_tsc = 0; /* shut up gcc */ 811 812 /* 813 * Wait for the mc146818A seconds counter to change. Read the i8254 814 * counter for each iteration since this is convenient and only 815 * costs a few usec of inaccuracy. The timing of the final reads 816 * of the counters almost matches the timing of the initial reads, 817 * so the main cause of inaccuracy is the varying latency from 818 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 819 * rtcin(RTC_SEC) that returns a changed seconds count. The 820 * maximum inaccuracy from this cause is < 10 usec on 486's. 821 */ 822 start_sec = sec; 823 for (;;) { 824 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 825 sec = rtcin(RTC_SEC); 826 count = getit(); 827 if (count == 0 || count > timer0_max_count) 828 goto fail; 829 if (count > prev_count) 830 tot_count += prev_count - (count - timer0_max_count); 831 else 832 tot_count += prev_count - count; 833 prev_count = count; 834 if (sec != start_sec) 835 break; 836 if (--timeout == 0) 837 goto fail; 838 } 839 840 /* 841 * Read the cpu cycle counter. The timing considerations are 842 * similar to those for the i8254 clock. 843 */ 844 if (tsc_present) 845 tsc_freq = rdtsc() - old_tsc; 846 847 if (bootverbose) { 848 if (tsc_present) 849 printf("TSC clock: %u Hz, ", tsc_freq); 850 printf("i8254 clock: %u Hz\n", tot_count); 851 } 852 return (tot_count); 853 854fail: 855 if (bootverbose) 856 printf("failed, using default i8254 clock of %u Hz\n", 857 timer_freq); 858 return (timer_freq); 859} 860#endif /* !PC98 */ 861 862static void 863set_timer_freq(u_int freq, int intr_freq) 864{ 865 int new_timer0_max_count; 866 867 mtx_lock_spin(&clock_lock); 868 timer_freq = freq; 869 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 870 if (new_timer0_max_count != timer0_max_count) { 871 timer0_max_count = new_timer0_max_count; 872 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 873 outb(TIMER_CNTR0, timer0_max_count & 0xff); 874 outb(TIMER_CNTR0, timer0_max_count >> 8); 875 } 876 mtx_unlock_spin(&clock_lock); 877} 878 879/* 880 * i8254_restore is called from apm_default_resume() to reload 881 * the countdown register. 882 * this should not be necessary but there are broken laptops that 883 * do not restore the countdown register on resume. 884 * when it happnes, it messes up the hardclock interval and system clock, 885 * which leads to the infamous "calcru: negative time" problem. 886 */ 887static void 888i8254_restore(void) 889{ 890 891 mtx_lock_spin(&clock_lock); 892 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 893 outb(TIMER_CNTR0, timer0_max_count & 0xff); 894 outb(TIMER_CNTR0, timer0_max_count >> 8); 895 mtx_unlock_spin(&clock_lock); 896} 897 898#ifndef PC98 899static void 900rtc_restore(void) 901{ 902 903 /* Reenable RTC updates and interrupts. */ 904 /* XXX locking is needed for RTC access? */ 905 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 906 writertc(RTC_STATUSB, rtc_statusb); 907} 908#endif 909 910/* 911 * Restore all the timers atomically. 912 */ 913void 914timer_restore(void) 915{ 916 917 i8254_restore(); /* restore timer_freq and hz */ 918#ifndef PC98 919 rtc_restore(); /* reenable RTC interrupts */ 920#endif 921} 922 923/* 924 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 925 * XXX initialization of other timers is unintentionally left blank. 926 */ 927void 928startrtclock() 929{ 930 u_int delta, freq; 931 932#ifdef PC98 933 findcpuspeed(); 934 if (pc98_machine_type & M_8M) 935 timer_freq = 1996800L; /* 1.9968 MHz */ 936 else 937 timer_freq = 2457600L; /* 2.4576 MHz */ 938#endif /* PC98 */ 939 940 if (cpu_feature & CPUID_TSC) 941 tsc_present = 1; 942 else 943 tsc_present = 0; 944 945#ifndef PC98 946 writertc(RTC_STATUSA, rtc_statusa); 947 writertc(RTC_STATUSB, RTCSB_24HR); 948#endif 949 950 set_timer_freq(timer_freq, hz); 951 freq = calibrate_clocks(); 952#ifdef CLK_CALIBRATION_LOOP 953 if (bootverbose) { 954 printf( 955 "Press a key on the console to abort clock calibration\n"); 956 while (cncheckc() == -1) 957 calibrate_clocks(); 958 } 959#endif 960 961 /* 962 * Use the calibrated i8254 frequency if it seems reasonable. 963 * Otherwise use the default, and don't use the calibrated i586 964 * frequency. 965 */ 966 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 967 if (delta < timer_freq / 100) { 968#ifndef CLK_USE_I8254_CALIBRATION 969 if (bootverbose) 970 printf( 971"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 972 freq = timer_freq; 973#endif 974 timer_freq = freq; 975 } else { 976 if (bootverbose) 977 printf( 978 "%d Hz differs from default of %d Hz by more than 1%%\n", 979 freq, timer_freq); 980 tsc_freq = 0; 981 } 982 983 set_timer_freq(timer_freq, hz); 984 i8254_timecounter.tc_frequency = timer_freq; 985 tc_init(&i8254_timecounter); 986 987#ifndef CLK_USE_TSC_CALIBRATION 988 if (tsc_freq != 0) { 989 if (bootverbose) 990 printf( 991"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 992 tsc_freq = 0; 993 } 994#endif 995 if (tsc_present && tsc_freq == 0) { 996 /* 997 * Calibration of the i586 clock relative to the mc146818A 998 * clock failed. Do a less accurate calibration relative 999 * to the i8254 clock. 1000 */ 1001 u_int64_t old_tsc = rdtsc(); 1002 1003 DELAY(1000000); 1004 tsc_freq = rdtsc() - old_tsc; 1005#ifdef CLK_USE_TSC_CALIBRATION 1006 if (bootverbose) 1007 printf("TSC clock: %u Hz (Method B)\n", tsc_freq); 1008#endif 1009 } 1010 1011#if !defined(SMP) 1012 /* 1013 * We can not use the TSC in SMP mode, until we figure out a 1014 * cheap (impossible), reliable and precise (yeah right!) way 1015 * to synchronize the TSCs of all the CPUs. 1016 * Curse Intel for leaving the counter out of the I/O APIC. 1017 */ 1018 1019 /* 1020 * We can not use the TSC if we support APM. Precise timekeeping 1021 * on an APM'ed machine is at best a fools pursuit, since 1022 * any and all of the time spent in various SMM code can't 1023 * be reliably accounted for. Reading the RTC is your only 1024 * source of reliable time info. The i8254 looses too of course 1025 * but we need to have some kind of time... 1026 * We don't know at this point whether APM is going to be used 1027 * or not, nor when it might be activated. Play it safe. 1028 */ 1029 if (power_pm_get_type() == POWER_PM_TYPE_APM) { 1030 if (bootverbose) 1031 printf("TSC initialization skipped: APM enabled.\n"); 1032 return; 1033 } 1034 1035 if (tsc_present && tsc_freq != 0 && !tsc_is_broken) { 1036 tsc_timecounter.tc_frequency = tsc_freq; 1037 tc_init(&tsc_timecounter); 1038 } 1039 1040#endif /* !defined(SMP) */ 1041} 1042 1043#ifdef PC98 1044static void 1045rtc_serialcombit(int i) 1046{ 1047 outb(IO_RTC, ((i&0x01)<<5)|0x07); 1048 DELAY(1); 1049 outb(IO_RTC, ((i&0x01)<<5)|0x17); 1050 DELAY(1); 1051 outb(IO_RTC, ((i&0x01)<<5)|0x07); 1052 DELAY(1); 1053} 1054 1055static void 1056rtc_serialcom(int i) 1057{ 1058 rtc_serialcombit(i&0x01); 1059 rtc_serialcombit((i&0x02)>>1); 1060 rtc_serialcombit((i&0x04)>>2); 1061 rtc_serialcombit((i&0x08)>>3); 1062 outb(IO_RTC, 0x07); 1063 DELAY(1); 1064 outb(IO_RTC, 0x0f); 1065 DELAY(1); 1066 outb(IO_RTC, 0x07); 1067 DELAY(1); 1068} 1069 1070static void 1071rtc_outb(int val) 1072{ 1073 int s; 1074 int sa = 0; 1075 1076 for (s=0;s<8;s++) { 1077 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 1078 outb(IO_RTC, sa); /* set DI & CLK 0 */ 1079 DELAY(1); 1080 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 1081 DELAY(1); 1082 } 1083 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 1084} 1085 1086static int 1087rtc_inb(void) 1088{ 1089 int s; 1090 int sa = 0; 1091 1092 for (s=0;s<8;s++) { 1093 sa |= ((inb(0x33) & 0x01) << s); 1094 outb(IO_RTC, 0x17); /* CLK 1 */ 1095 DELAY(1); 1096 outb(IO_RTC, 0x07); /* CLK 0 */ 1097 DELAY(2); 1098 } 1099 return sa; 1100} 1101#endif /* PC-98 */ 1102 1103/* 1104 * Initialize the time of day register, based on the time base which is, e.g. 1105 * from a filesystem. 1106 */ 1107void 1108inittodr(time_t base) 1109{ 1110 unsigned long sec, days; 1111 int year, month; 1112 int y, m, s; 1113 struct timespec ts; 1114#ifdef PC98 1115 int second, min, hour; 1116#endif 1117 1118 if (base) { 1119 s = splclock(); 1120 ts.tv_sec = base; 1121 ts.tv_nsec = 0; 1122 tc_setclock(&ts); 1123 splx(s); 1124 } 1125 1126#ifdef PC98 1127 rtc_serialcom(0x03); /* Time Read */ 1128 rtc_serialcom(0x01); /* Register shift command. */ 1129 DELAY(20); 1130 1131 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 1132 min = bcd2bin(rtc_inb() & 0xff); /* min */ 1133 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 1134 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 1135 1136 month = (rtc_inb() >> 4) & 0x0f; /* month */ 1137 for (m = 1; m < month; m++) 1138 days += daysinmonth[m-1]; 1139 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 1140 /* 2000 year problem */ 1141 if (year < 1995) 1142 year += 100; 1143 if (year < 1970) 1144 goto wrong_time; 1145 for (y = 1970; y < year; y++) 1146 days += DAYSPERYEAR + LEAPYEAR(y); 1147 if ((month > 2) && LEAPYEAR(year)) 1148 days ++; 1149 sec = ((( days * 24 + 1150 hour) * 60 + 1151 min) * 60 + 1152 second); 1153 /* sec now contains the number of seconds, since Jan 1 1970, 1154 in the local time zone */ 1155 1156 s = splhigh(); 1157#else /* IBM-PC */ 1158 /* Look if we have a RTC present and the time is valid */ 1159 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 1160 goto wrong_time; 1161 1162 /* wait for time update to complete */ 1163 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 1164 s = splhigh(); 1165 while (rtcin(RTC_STATUSA) & RTCSA_TUP) { 1166 splx(s); 1167 s = splhigh(); 1168 } 1169 1170 days = 0; 1171#ifdef USE_RTC_CENTURY 1172 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 1173#else 1174 year = readrtc(RTC_YEAR) + 1900; 1175 if (year < 1970) 1176 year += 100; 1177#endif 1178 if (year < 1970) { 1179 splx(s); 1180 goto wrong_time; 1181 } 1182 month = readrtc(RTC_MONTH); 1183 for (m = 1; m < month; m++) 1184 days += daysinmonth[m-1]; 1185 if ((month > 2) && LEAPYEAR(year)) 1186 days ++; 1187 days += readrtc(RTC_DAY) - 1; 1188 for (y = 1970; y < year; y++) 1189 days += DAYSPERYEAR + LEAPYEAR(y); 1190 sec = ((( days * 24 + 1191 readrtc(RTC_HRS)) * 60 + 1192 readrtc(RTC_MIN)) * 60 + 1193 readrtc(RTC_SEC)); 1194 /* sec now contains the number of seconds, since Jan 1 1970, 1195 in the local time zone */ 1196#endif 1197 1198 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1199 1200 y = time_second - sec; 1201 if (y <= -2 || y >= 2) { 1202 /* badly off, adjust it */ 1203 ts.tv_sec = sec; 1204 ts.tv_nsec = 0; 1205 tc_setclock(&ts); 1206 } 1207 splx(s); 1208 return; 1209 1210wrong_time: 1211 printf("Invalid time in real time clock.\n"); 1212 printf("Check and reset the date immediately!\n"); 1213} 1214 1215/* 1216 * Write system time back to RTC 1217 */ 1218void 1219resettodr() 1220{ 1221 unsigned long tm; 1222 int y, m, s; 1223#ifdef PC98 1224 int wd; 1225#endif 1226 1227 if (disable_rtc_set) 1228 return; 1229 1230 s = splclock(); 1231 tm = time_second; 1232 splx(s); 1233 1234#ifdef PC98 1235 rtc_serialcom(0x01); /* Register shift command. */ 1236 1237 /* Calculate local time to put in RTC */ 1238 1239 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1240 1241 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1242 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1243 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1244 1245 /* We have now the days since 01-01-1970 in tm */ 1246 wd = (tm+4)%7; 1247 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1248 tm >= m; 1249 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1250 tm -= m; 1251 1252 /* Now we have the years in y and the day-of-the-year in tm */ 1253 for (m = 0; ; m++) { 1254 int ml; 1255 1256 ml = daysinmonth[m]; 1257 if (m == 1 && LEAPYEAR(y)) 1258 ml++; 1259 if (tm < ml) 1260 break; 1261 tm -= ml; 1262 } 1263 1264 m++; 1265 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1266 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1267 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1268 1269 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1270 rtc_serialcom(0x00); /* Register hold command. */ 1271#else 1272 /* Disable RTC updates and interrupts. */ 1273 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1274 1275 /* Calculate local time to put in RTC */ 1276 1277 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1278 1279 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1280 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1281 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1282 1283 /* We have now the days since 01-01-1970 in tm */ 1284 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1285 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1286 tm >= m; 1287 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1288 tm -= m; 1289 1290 /* Now we have the years in y and the day-of-the-year in tm */ 1291 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1292#ifdef USE_RTC_CENTURY 1293 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1294#endif 1295 for (m = 0; ; m++) { 1296 int ml; 1297 1298 ml = daysinmonth[m]; 1299 if (m == 1 && LEAPYEAR(y)) 1300 ml++; 1301 if (tm < ml) 1302 break; 1303 tm -= ml; 1304 } 1305 1306 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1307 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1308 1309 /* Reenable RTC updates and interrupts. */ 1310 writertc(RTC_STATUSB, rtc_statusb); 1311#endif /* PC98 */ 1312} 1313 1314 1315/* 1316 * Start both clocks running. 1317 */ 1318void 1319cpu_initclocks() 1320{ 1321#ifndef PC98 1322 int diag; 1323#endif 1324#ifdef APIC_IO 1325 int apic_8254_trial; 1326 void *clkdesc; 1327#endif /* APIC_IO */ 1328 register_t crit; 1329 1330#ifndef PC98 1331 if (statclock_disable) { 1332 /* 1333 * The stat interrupt mask is different without the 1334 * statistics clock. Also, don't set the interrupt 1335 * flag which would normally cause the RTC to generate 1336 * interrupts. 1337 */ 1338 rtc_statusb = RTCSB_24HR; 1339 } else { 1340 /* Setting stathz to nonzero early helps avoid races. */ 1341 stathz = RTC_NOPROFRATE; 1342 profhz = RTC_PROFRATE; 1343 } 1344#endif 1345 1346 /* Finish initializing 8253 timer 0. */ 1347#ifdef APIC_IO 1348 1349 apic_8254_intr = isa_apic_irq(0); 1350 apic_8254_trial = 0; 1351 if (apic_8254_intr >= 0 ) { 1352 if (apic_int_type(0, 0) == 3) 1353 apic_8254_trial = 1; 1354 } else { 1355 /* look for ExtInt on pin 0 */ 1356 if (apic_int_type(0, 0) == 3) { 1357 apic_8254_intr = apic_irq(0, 0); 1358 setup_8254_mixed_mode(); 1359 } else 1360 panic("APIC_IO: Cannot route 8254 interrupt to CPU"); 1361 } 1362 1363 inthand_add("clk", apic_8254_intr, (driver_intr_t *)clkintr, NULL, 1364 INTR_TYPE_CLK | INTR_FAST, &clkdesc); 1365 crit = intr_disable(); 1366 mtx_lock_spin(&icu_lock); 1367 INTREN(1 << apic_8254_intr); 1368 mtx_unlock_spin(&icu_lock); 1369 intr_restore(crit); 1370 1371#else /* APIC_IO */ 1372 1373 /* 1374 * XXX Check the priority of this interrupt handler. I 1375 * couldn't find anything suitable in the BSD/OS code (grog, 1376 * 19 July 2000). 1377 */ 1378 inthand_add("clk", 0, (driver_intr_t *)clkintr, NULL, 1379 INTR_TYPE_CLK | INTR_FAST, NULL); 1380 crit = intr_disable(); 1381 mtx_lock_spin(&icu_lock); 1382 INTREN(IRQ0); 1383 mtx_unlock_spin(&icu_lock); 1384 intr_restore(crit); 1385 1386#endif /* APIC_IO */ 1387 1388#ifndef PC98 1389 /* Initialize RTC. */ 1390 writertc(RTC_STATUSA, rtc_statusa); 1391 writertc(RTC_STATUSB, RTCSB_24HR); 1392 1393 /* Don't bother enabling the statistics clock. */ 1394 if (statclock_disable) 1395 return; 1396 diag = rtcin(RTC_DIAG); 1397 if (diag != 0) 1398 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1399#endif /* !PC98 */ 1400 1401#ifndef PC98 1402#ifdef APIC_IO 1403 if (isa_apic_irq(8) != 8) 1404 panic("APIC RTC != 8"); 1405#endif /* APIC_IO */ 1406 1407 inthand_add("rtc", 8, (driver_intr_t *)rtcintr, NULL, 1408 INTR_TYPE_CLK | INTR_FAST, NULL); 1409 1410 crit = intr_disable(); 1411 mtx_lock_spin(&icu_lock); 1412#ifdef APIC_IO 1413 INTREN(APIC_IRQ8); 1414#else 1415 INTREN(IRQ8); 1416#endif /* APIC_IO */ 1417 mtx_unlock_spin(&icu_lock); 1418 intr_restore(crit); 1419 1420 writertc(RTC_STATUSB, rtc_statusb); 1421#endif /* PC98 */ 1422 1423#ifdef APIC_IO 1424 if (apic_8254_trial) { 1425 1426 printf("APIC_IO: Testing 8254 interrupt delivery\n"); 1427 while (read_intr_count(8) < 6) 1428 ; /* nothing */ 1429 if (read_intr_count(apic_8254_intr) < 3) { 1430 /* 1431 * The MP table is broken. 1432 * The 8254 was not connected to the specified pin 1433 * on the IO APIC. 1434 * Workaround: Limited variant of mixed mode. 1435 */ 1436 crit = intr_disable(); 1437 mtx_lock_spin(&icu_lock); 1438 INTRDIS(1 << apic_8254_intr); 1439 mtx_unlock_spin(&icu_lock); 1440 intr_restore(crit); 1441 inthand_remove(clkdesc); 1442 printf("APIC_IO: Broken MP table detected: " 1443 "8254 is not connected to " 1444 "IOAPIC #%d intpin %d\n", 1445 int_to_apicintpin[apic_8254_intr].ioapic, 1446 int_to_apicintpin[apic_8254_intr].int_pin); 1447 /* 1448 * Revoke current ISA IRQ 0 assignment and 1449 * configure a fallback interrupt routing from 1450 * the 8254 Timer via the 8259 PIC to the 1451 * an ExtInt interrupt line on IOAPIC #0 intpin 0. 1452 * We reuse the low level interrupt handler number. 1453 */ 1454 if (apic_irq(0, 0) < 0) { 1455 revoke_apic_irq(apic_8254_intr); 1456 assign_apic_irq(0, 0, apic_8254_intr); 1457 } 1458 apic_8254_intr = apic_irq(0, 0); 1459 setup_8254_mixed_mode(); 1460 inthand_add("clk", apic_8254_intr, 1461 (driver_intr_t *)clkintr, NULL, 1462 INTR_TYPE_CLK | INTR_FAST, NULL); 1463 crit = intr_disable(); 1464 mtx_lock_spin(&icu_lock); 1465 INTREN(1 << apic_8254_intr); 1466 mtx_unlock_spin(&icu_lock); 1467 intr_restore(crit); 1468 } 1469 1470 } 1471 if (apic_int_type(0, 0) != 3 || 1472 int_to_apicintpin[apic_8254_intr].ioapic != 0 || 1473 int_to_apicintpin[apic_8254_intr].int_pin != 0) 1474 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n", 1475 int_to_apicintpin[apic_8254_intr].ioapic, 1476 int_to_apicintpin[apic_8254_intr].int_pin); 1477 else 1478 printf("APIC_IO: " 1479 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n"); 1480#endif 1481 1482} 1483 1484#ifdef APIC_IO 1485static u_long 1486read_intr_count(int vec) 1487{ 1488 u_long *up; 1489 up = intr_countp[vec]; 1490 if (up) 1491 return *up; 1492 return 0UL; 1493} 1494 1495static void 1496setup_8254_mixed_mode() 1497{ 1498 /* 1499 * Allow 8254 timer to INTerrupt 8259: 1500 * re-initialize master 8259: 1501 * reset; prog 4 bytes, single ICU, edge triggered 1502 */ 1503 outb(IO_ICU1, 0x13); 1504#ifdef PC98 1505 outb(IO_ICU1 + 2, NRSVIDT); /* start vector (unused) */ 1506 outb(IO_ICU1 + 2, 0x00); /* ignore slave */ 1507 outb(IO_ICU1 + 2, 0x03); /* auto EOI, 8086 */ 1508 outb(IO_ICU1 + 2, 0xfe); /* unmask INT0 */ 1509#else 1510 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */ 1511 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1512 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1513 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1514#endif 1515 1516 /* program IO APIC for type 3 INT on INT0 */ 1517 if (ext_int_setup(0, 0) < 0) 1518 panic("8254 redirect via APIC pin0 impossible!"); 1519} 1520#endif 1521 1522void 1523setstatclockrate(int newhz) 1524{ 1525#ifndef PC98 1526 if (newhz == RTC_PROFRATE) 1527 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1528 else 1529 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1530 writertc(RTC_STATUSA, rtc_statusa); 1531#endif 1532} 1533 1534static int 1535sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS) 1536{ 1537 int error; 1538 u_int freq; 1539 1540 /* 1541 * Use `i8254' instead of `timer' in external names because `timer' 1542 * is is too generic. Should use it everywhere. 1543 */ 1544 freq = timer_freq; 1545 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 1546 if (error == 0 && req->newptr != NULL) { 1547 if (timer0_state != RELEASED) 1548 return (EBUSY); /* too much trouble to handle */ 1549 set_timer_freq(freq, hz); 1550 i8254_timecounter.tc_frequency = freq; 1551 } 1552 return (error); 1553} 1554 1555SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1556 0, sizeof(u_int), sysctl_machdep_i8254_freq, "IU", ""); 1557 1558static int 1559sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS) 1560{ 1561 int error; 1562 u_int freq; 1563 1564 if (tsc_timecounter.tc_frequency == 0) 1565 return (EOPNOTSUPP); 1566 freq = tsc_freq; 1567 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 1568 if (error == 0 && req->newptr != NULL) { 1569 tsc_freq = freq; 1570 tsc_timecounter.tc_frequency = tsc_freq; 1571 } 1572 return (error); 1573} 1574 1575SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW, 1576 0, sizeof(u_int), sysctl_machdep_tsc_freq, "IU", ""); 1577 1578static unsigned 1579i8254_get_timecount(struct timecounter *tc) 1580{ 1581 u_int count; 1582 u_int high, low; 1583 u_int eflags; 1584 1585 eflags = read_eflags(); 1586 mtx_lock_spin(&clock_lock); 1587 1588 /* Select timer0 and latch counter value. */ 1589 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 1590 1591 low = inb(TIMER_CNTR0); 1592 high = inb(TIMER_CNTR0); 1593 count = timer0_max_count - ((high << 8) | low); 1594 if (count < i8254_lastcount || 1595 (!i8254_ticked && (clkintr_pending || 1596 ((count < 20 || (!(eflags & PSL_I) && count < timer0_max_count / 2u)) && 1597#ifdef APIC_IO 1598#define lapic_irr1 ((volatile u_int *)&lapic)[0x210 / 4] /* XXX XXX */ 1599 /* XXX this assumes that apic_8254_intr is < 24. */ 1600 (lapic_irr1 & (1 << apic_8254_intr)))) 1601#else 1602 (inb(IO_ICU1) & 1))) 1603#endif 1604 )) { 1605 i8254_ticked = 1; 1606 i8254_offset += timer0_max_count; 1607 } 1608 i8254_lastcount = count; 1609 count += i8254_offset; 1610 mtx_unlock_spin(&clock_lock); 1611 return (count); 1612} 1613 1614static unsigned 1615tsc_get_timecount(struct timecounter *tc) 1616{ 1617 return (rdtsc()); 1618} 1619 1620#ifdef DEV_ISA 1621/* 1622 * Attach to the ISA PnP descriptors for the timer and realtime clock. 1623 */ 1624static struct isa_pnp_id attimer_ids[] = { 1625 { 0x0001d041 /* PNP0100 */, "AT timer" }, 1626 { 0x000bd041 /* PNP0B00 */, "AT realtime clock" }, 1627 { 0 } 1628}; 1629 1630static int 1631attimer_probe(device_t dev) 1632{ 1633 int result; 1634 1635 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids)) <= 0) 1636 device_quiet(dev); 1637 return(result); 1638} 1639 1640static int 1641attimer_attach(device_t dev) 1642{ 1643 return(0); 1644} 1645 1646static device_method_t attimer_methods[] = { 1647 /* Device interface */ 1648 DEVMETHOD(device_probe, attimer_probe), 1649 DEVMETHOD(device_attach, attimer_attach), 1650 DEVMETHOD(device_detach, bus_generic_detach), 1651 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1652 DEVMETHOD(device_suspend, bus_generic_suspend), /* XXX stop statclock? */ 1653 DEVMETHOD(device_resume, bus_generic_resume), /* XXX restart statclock? */ 1654 { 0, 0 } 1655}; 1656 1657static driver_t attimer_driver = { 1658 "attimer", 1659 attimer_methods, 1660 1, /* no softc */ 1661}; 1662 1663static devclass_t attimer_devclass; 1664 1665DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0); 1666#ifndef PC98 1667DRIVER_MODULE(attimer, acpi, attimer_driver, attimer_devclass, 0, 0); 1668#endif 1669#endif /* DEV_ISA */ 1670