pcrtc.c revision 92793
1275970Scy/*- 2275970Scy * Copyright (c) 1990 The Regents of the University of California. 3275970Scy * All rights reserved. 4275970Scy * 5275970Scy * This code is derived from software contributed to Berkeley by 6275970Scy * William Jolitz and Don Ahn. 7275970Scy * 8275970Scy * Redistribution and use in source and binary forms, with or without 9275970Scy * modification, are permitted provided that the following conditions 10275970Scy * are met: 11275970Scy * 1. Redistributions of source code must retain the above copyright 12275970Scy * notice, this list of conditions and the following disclaimer. 13275970Scy * 2. Redistributions in binary form must reproduce the above copyright 14275970Scy * notice, this list of conditions and the following disclaimer in the 15275970Scy * documentation and/or other materials provided with the distribution. 16275970Scy * 3. All advertising materials mentioning features or use of this software 17275970Scy * must display the following acknowledgement: 18275970Scy * This product includes software developed by the University of 19275970Scy * California, Berkeley and its contributors. 20275970Scy * 4. Neither the name of the University nor the names of its contributors 21275970Scy * may be used to endorse or promote products derived from this software 22275970Scy * without specific prior written permission. 23275970Scy * 24275970Scy * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25275970Scy * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26275970Scy * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27275970Scy * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28275970Scy * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29275970Scy * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30275970Scy * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31275970Scy * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32275970Scy * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33275970Scy * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34275970Scy * SUCH DAMAGE. 35275970Scy * 36275970Scy * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37275970Scy * $FreeBSD: head/sys/pc98/cbus/pcrtc.c 92793 2002-03-20 12:22:31Z kato $ 38275970Scy */ 39275970Scy 40275970Scy/* 41275970Scy * Routines to handle clock hardware. 42275970Scy */ 43275970Scy 44275970Scy/* 45275970Scy * inittodr, settodr and support routines written 46275970Scy * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47275970Scy * 48275970Scy * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49275970Scy */ 50275970Scy 51275970Scy/* 52275970Scy * modified for PC98 by Kakefuda 53275970Scy */ 54275970Scy 55275970Scy#include "opt_clock.h" 56275970Scy#include "opt_isa.h" 57275970Scy#include "opt_mca.h" 58275970Scy 59275970Scy#include <sys/param.h> 60275970Scy#include <sys/systm.h> 61275970Scy#include <sys/bus.h> 62275970Scy#include <sys/lock.h> 63275970Scy#include <sys/mutex.h> 64275970Scy#include <sys/proc.h> 65275970Scy#include <sys/time.h> 66275970Scy#include <sys/timetc.h> 67275970Scy#include <sys/kernel.h> 68275970Scy#include <sys/sysctl.h> 69275970Scy#include <sys/cons.h> 70275970Scy#include <sys/power.h> 71275970Scy 72275970Scy#include <machine/clock.h> 73275970Scy#ifdef CLK_CALIBRATION_LOOP 74275970Scy#endif 75275970Scy#include <machine/cputypes.h> 76275970Scy#include <machine/frame.h> 77275970Scy#include <machine/limits.h> 78275970Scy#include <machine/md_var.h> 79275970Scy#include <machine/psl.h> 80275970Scy#ifdef APIC_IO 81275970Scy#include <machine/segments.h> 82275970Scy#endif 83275970Scy#if defined(SMP) || defined(APIC_IO) 84275970Scy#include <machine/smp.h> 85275970Scy#endif /* SMP || APIC_IO */ 86275970Scy#include <machine/specialreg.h> 87275970Scy 88275970Scy#include <i386/isa/icu.h> 89275970Scy#ifdef PC98 90275970Scy#include <pc98/pc98/pc98.h> 91275970Scy#include <pc98/pc98/pc98_machdep.h> 92275970Scy#include <i386/isa/isa_device.h> 93275970Scy#else 94275970Scy#include <i386/isa/isa.h> 95275970Scy#include <isa/rtc.h> 96275970Scy#endif 97275970Scy#ifdef DEV_ISA 98275970Scy#include <isa/isavar.h> 99275970Scy#endif 100275970Scy#include <i386/isa/timerreg.h> 101275970Scy 102275970Scy#include <i386/isa/intr_machdep.h> 103275970Scy 104275970Scy#ifdef DEV_MCA 105275970Scy#include <i386/isa/mca_machdep.h> 106275970Scy#endif 107275970Scy 108275970Scy#ifdef APIC_IO 109275970Scy#include <i386/isa/intr_machdep.h> 110275970Scy/* The interrupt triggered by the 8254 (timer) chip */ 111275970Scyint apic_8254_intr; 112275970Scystatic u_long read_intr_count(int vec); 113275970Scystatic void setup_8254_mixed_mode(void); 114275970Scy#endif 115275970Scy 116275970Scy/* 117275970Scy * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 118275970Scy * can use a simple formula for leap years. 119275970Scy */ 120275970Scy#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 121275970Scy#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 122275970Scy 123275970Scy#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 124275970Scy 125275970Scy/* 126275970Scy * Time in timer cycles that it takes for microtime() to disable interrupts 127275970Scy * and latch the count. microtime() currently uses "cli; outb ..." so it 128275970Scy * normally takes less than 2 timer cycles. Add a few for cache misses. 129275970Scy * Add a few more to allow for latency in bogus calls to microtime() with 130275970Scy * interrupts already disabled. 131275970Scy */ 132275970Scy#define TIMER0_LATCH_COUNT 20 133275970Scy 134275970Scy/* 135275970Scy * Maximum frequency that we are willing to allow for timer0. Must be 136275970Scy * low enough to guarantee that the timer interrupt handler returns 137275970Scy * before the next timer interrupt. 138275970Scy */ 139275970Scy#define TIMER0_MAX_FREQ 20000 140275970Scy 141275970Scyint adjkerntz; /* local offset from GMT in seconds */ 142275970Scyint clkintr_pending; 143275970Scyint disable_rtc_set; /* disable resettodr() if != 0 */ 144275970Scyint statclock_disable; 145275970Scy#ifndef TIMER_FREQ 146275970Scy#ifdef PC98 147275970Scy#define TIMER_FREQ 2457600 148275970Scy#else /* IBM-PC */ 149275970Scy#define TIMER_FREQ 1193182 150275970Scy#endif /* PC98 */ 151275970Scy#endif 152275970Scyu_int timer_freq = TIMER_FREQ; 153275970Scyint timer0_max_count; 154275970Scyu_int tsc_freq; 155275970Scyint tsc_is_broken; 156275970Scyu_int tsc_present; 157275970Scyint wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 158275970Scystruct mtx clock_lock; 159275970Scy 160275970Scystatic int beeping = 0; 161275970Scystatic const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 162275970Scystatic u_int hardclock_max_count; 163275970Scystatic u_int32_t i8254_lastcount; 164275970Scystatic u_int32_t i8254_offset; 165275970Scystatic int i8254_ticked; 166275970Scy/* 167275970Scy * XXX new_function and timer_func should not handle clockframes, but 168275970Scy * timer_func currently needs to hold hardclock to handle the 169275970Scy * timer0_state == 0 case. We should use inthand_add()/inthand_remove() 170275970Scy * to switch between clkintr() and a slightly different timerintr(). 171275970Scy */ 172275970Scystatic void (*new_function)(struct clockframe *frame); 173275970Scystatic u_int new_rate; 174275970Scy#ifndef PC98 175275970Scystatic u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 176275970Scystatic u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 177275970Scy#endif 178275970Scystatic u_int timer0_prescaler_count; 179275970Scy 180275970Scy/* Values for timerX_state: */ 181275970Scy#define RELEASED 0 182275970Scy#define RELEASE_PENDING 1 183275970Scy#define ACQUIRED 2 184275970Scy#define ACQUIRE_PENDING 3 185275970Scy 186275970Scystatic u_char timer0_state; 187275970Scy#ifdef PC98 188275970Scystatic u_char timer1_state; 189275970Scy#endif 190275970Scystatic u_char timer2_state; 191275970Scystatic void (*timer_func)(struct clockframe *frame) = hardclock; 192275970Scy#ifdef PC98 193275970Scystatic void rtc_serialcombit(int); 194275970Scystatic void rtc_serialcom(int); 195275970Scystatic int rtc_inb(void); 196275970Scystatic void rtc_outb(int); 197275970Scy#endif 198275970Scy 199275970Scystatic unsigned i8254_get_timecount(struct timecounter *tc); 200275970Scystatic unsigned tsc_get_timecount(struct timecounter *tc); 201275970Scystatic void set_timer_freq(u_int freq, int intr_freq); 202275970Scy 203275970Scystatic struct timecounter tsc_timecounter = { 204275970Scy tsc_get_timecount, /* get_timecount */ 205275970Scy 0, /* no poll_pps */ 206275970Scy ~0u, /* counter_mask */ 207275970Scy 0, /* frequency */ 208275970Scy "TSC" /* name */ 209}; 210 211SYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD, 212 &tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", ""); 213 214static struct timecounter i8254_timecounter = { 215 i8254_get_timecount, /* get_timecount */ 216 0, /* no poll_pps */ 217 ~0u, /* counter_mask */ 218 0, /* frequency */ 219 "i8254" /* name */ 220}; 221 222SYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD, 223 &i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", ""); 224 225static void 226clkintr(struct clockframe frame) 227{ 228 229 if (timecounter->tc_get_timecount == i8254_get_timecount) { 230 mtx_lock_spin(&clock_lock); 231 if (i8254_ticked) 232 i8254_ticked = 0; 233 else { 234 i8254_offset += timer0_max_count; 235 i8254_lastcount = 0; 236 } 237 clkintr_pending = 0; 238 mtx_unlock_spin(&clock_lock); 239 } 240 timer_func(&frame); 241#ifdef SMP 242 if (timer_func == hardclock) 243 forward_hardclock(); 244#endif 245 switch (timer0_state) { 246 247 case RELEASED: 248 break; 249 250 case ACQUIRED: 251 if ((timer0_prescaler_count += timer0_max_count) 252 >= hardclock_max_count) { 253 timer0_prescaler_count -= hardclock_max_count; 254 hardclock(&frame); 255#ifdef SMP 256 forward_hardclock(); 257#endif 258 } 259 break; 260 261 case ACQUIRE_PENDING: 262 mtx_lock_spin(&clock_lock); 263 i8254_offset = i8254_get_timecount(NULL); 264 i8254_lastcount = 0; 265 timer0_max_count = TIMER_DIV(new_rate); 266 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 267 outb(TIMER_CNTR0, timer0_max_count & 0xff); 268 outb(TIMER_CNTR0, timer0_max_count >> 8); 269 mtx_unlock_spin(&clock_lock); 270 timer_func = new_function; 271 timer0_state = ACQUIRED; 272 break; 273 274 case RELEASE_PENDING: 275 if ((timer0_prescaler_count += timer0_max_count) 276 >= hardclock_max_count) { 277 mtx_lock_spin(&clock_lock); 278 i8254_offset = i8254_get_timecount(NULL); 279 i8254_lastcount = 0; 280 timer0_max_count = hardclock_max_count; 281 outb(TIMER_MODE, 282 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 283 outb(TIMER_CNTR0, timer0_max_count & 0xff); 284 outb(TIMER_CNTR0, timer0_max_count >> 8); 285 mtx_unlock_spin(&clock_lock); 286 timer0_prescaler_count = 0; 287 timer_func = hardclock; 288 timer0_state = RELEASED; 289 hardclock(&frame); 290#ifdef SMP 291 forward_hardclock(); 292#endif 293 } 294 break; 295 } 296#ifdef DEV_MCA 297 /* Reset clock interrupt by asserting bit 7 of port 0x61 */ 298 if (MCA_system) 299 outb(0x61, inb(0x61) | 0x80); 300#endif 301} 302 303/* 304 * The acquire and release functions must be called at ipl >= splclock(). 305 */ 306int 307acquire_timer0(int rate, void (*function)(struct clockframe *frame)) 308{ 309 static int old_rate; 310 311 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 312 return (-1); 313 switch (timer0_state) { 314 315 case RELEASED: 316 timer0_state = ACQUIRE_PENDING; 317 break; 318 319 case RELEASE_PENDING: 320 if (rate != old_rate) 321 return (-1); 322 /* 323 * The timer has been released recently, but is being 324 * re-acquired before the release completed. In this 325 * case, we simply reclaim it as if it had not been 326 * released at all. 327 */ 328 timer0_state = ACQUIRED; 329 break; 330 331 default: 332 return (-1); /* busy */ 333 } 334 new_function = function; 335 old_rate = new_rate = rate; 336 return (0); 337} 338 339#ifdef PC98 340int 341acquire_timer1(int mode) 342{ 343 344 if (timer1_state != RELEASED) 345 return (-1); 346 timer1_state = ACQUIRED; 347 348 /* 349 * This access to the timer registers is as atomic as possible 350 * because it is a single instruction. We could do better if we 351 * knew the rate. Use of splclock() limits glitches to 10-100us, 352 * and this is probably good enough for timer2, so we aren't as 353 * careful with it as with timer0. 354 */ 355 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 356 357 return (0); 358} 359#endif 360 361int 362acquire_timer2(int mode) 363{ 364 365 if (timer2_state != RELEASED) 366 return (-1); 367 timer2_state = ACQUIRED; 368 369 /* 370 * This access to the timer registers is as atomic as possible 371 * because it is a single instruction. We could do better if we 372 * knew the rate. Use of splclock() limits glitches to 10-100us, 373 * and this is probably good enough for timer2, so we aren't as 374 * careful with it as with timer0. 375 */ 376 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 377 378 return (0); 379} 380 381int 382release_timer0() 383{ 384 switch (timer0_state) { 385 386 case ACQUIRED: 387 timer0_state = RELEASE_PENDING; 388 break; 389 390 case ACQUIRE_PENDING: 391 /* Nothing happened yet, release quickly. */ 392 timer0_state = RELEASED; 393 break; 394 395 default: 396 return (-1); 397 } 398 return (0); 399} 400 401#ifdef PC98 402int 403release_timer1() 404{ 405 406 if (timer1_state != ACQUIRED) 407 return (-1); 408 timer1_state = RELEASED; 409 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 410 return (0); 411} 412#endif 413 414int 415release_timer2() 416{ 417 418 if (timer2_state != ACQUIRED) 419 return (-1); 420 timer2_state = RELEASED; 421 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 422 return (0); 423} 424 425#ifndef PC98 426/* 427 * This routine receives statistical clock interrupts from the RTC. 428 * As explained above, these occur at 128 interrupts per second. 429 * When profiling, we receive interrupts at a rate of 1024 Hz. 430 * 431 * This does not actually add as much overhead as it sounds, because 432 * when the statistical clock is active, the hardclock driver no longer 433 * needs to keep (inaccurate) statistics on its own. This decouples 434 * statistics gathering from scheduling interrupts. 435 * 436 * The RTC chip requires that we read status register C (RTC_INTR) 437 * to acknowledge an interrupt, before it will generate the next one. 438 * Under high interrupt load, rtcintr() can be indefinitely delayed and 439 * the clock can tick immediately after the read from RTC_INTR. In this 440 * case, the mc146818A interrupt signal will not drop for long enough 441 * to register with the 8259 PIC. If an interrupt is missed, the stat 442 * clock will halt, considerably degrading system performance. This is 443 * why we use 'while' rather than a more straightforward 'if' below. 444 * Stat clock ticks can still be lost, causing minor loss of accuracy 445 * in the statistics, but the stat clock will no longer stop. 446 */ 447static void 448rtcintr(struct clockframe frame) 449{ 450 while (rtcin(RTC_INTR) & RTCIR_PERIOD) { 451 statclock(&frame); 452#ifdef SMP 453 forward_statclock(); 454#endif 455 } 456} 457 458#include "opt_ddb.h" 459#ifdef DDB 460#include <ddb/ddb.h> 461 462DB_SHOW_COMMAND(rtc, rtc) 463{ 464 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 465 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 466 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 467 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 468} 469#endif /* DDB */ 470#endif /* for PC98 */ 471 472static int 473getit(void) 474{ 475 int high, low; 476 477 mtx_lock_spin(&clock_lock); 478 479 /* Select timer0 and latch counter value. */ 480 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 481 482 low = inb(TIMER_CNTR0); 483 high = inb(TIMER_CNTR0); 484 485 mtx_unlock_spin(&clock_lock); 486 return ((high << 8) | low); 487} 488 489/* 490 * Wait "n" microseconds. 491 * Relies on timer 1 counting down from (timer_freq / hz) 492 * Note: timer had better have been programmed before this is first used! 493 */ 494void 495DELAY(int n) 496{ 497 int delta, prev_tick, tick, ticks_left; 498 499#ifdef DELAYDEBUG 500 int getit_calls = 1; 501 int n1; 502 static int state = 0; 503 504 if (state == 0) { 505 state = 1; 506 for (n1 = 1; n1 <= 10000000; n1 *= 10) 507 DELAY(n1); 508 state = 2; 509 } 510 if (state == 1) 511 printf("DELAY(%d)...", n); 512#endif 513 /* 514 * Guard against the timer being uninitialized if we are called 515 * early for console i/o. 516 */ 517 if (timer0_max_count == 0) 518 set_timer_freq(timer_freq, hz); 519 520 /* 521 * Read the counter first, so that the rest of the setup overhead is 522 * counted. Guess the initial overhead is 20 usec (on most systems it 523 * takes about 1.5 usec for each of the i/o's in getit(). The loop 524 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 525 * multiplications and divisions to scale the count take a while). 526 */ 527 prev_tick = getit(); 528 n -= 0; /* XXX actually guess no initial overhead */ 529 /* 530 * Calculate (n * (timer_freq / 1e6)) without using floating point 531 * and without any avoidable overflows. 532 */ 533 if (n <= 0) 534 ticks_left = 0; 535 else if (n < 256) 536 /* 537 * Use fixed point to avoid a slow division by 1000000. 538 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 539 * 2^15 is the first power of 2 that gives exact results 540 * for n between 0 and 256. 541 */ 542 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 543 else 544 /* 545 * Don't bother using fixed point, although gcc-2.7.2 546 * generates particularly poor code for the long long 547 * division, since even the slow way will complete long 548 * before the delay is up (unless we're interrupted). 549 */ 550 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 551 / 1000000; 552 553 while (ticks_left > 0) { 554 tick = getit(); 555#ifdef DELAYDEBUG 556 ++getit_calls; 557#endif 558 delta = prev_tick - tick; 559 prev_tick = tick; 560 if (delta < 0) { 561 delta += timer0_max_count; 562 /* 563 * Guard against timer0_max_count being wrong. 564 * This shouldn't happen in normal operation, 565 * but it may happen if set_timer_freq() is 566 * traced. 567 */ 568 if (delta < 0) 569 delta = 0; 570 } 571 ticks_left -= delta; 572 } 573#ifdef DELAYDEBUG 574 if (state == 1) 575 printf(" %d calls to getit() at %d usec each\n", 576 getit_calls, (n + 5) / getit_calls); 577#endif 578} 579 580static void 581sysbeepstop(void *chan) 582{ 583#ifdef PC98 /* PC98 */ 584 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 585 release_timer1(); 586#else 587 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 588 release_timer2(); 589#endif 590 beeping = 0; 591} 592 593int 594sysbeep(int pitch, int period) 595{ 596 int x = splclock(); 597 598#ifdef PC98 599 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 600 if (!beeping) { 601 /* Something else owns it. */ 602 splx(x); 603 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 604 } 605 disable_intr(); 606 outb(0x3fdb, pitch); 607 outb(0x3fdb, (pitch>>8)); 608 enable_intr(); 609 if (!beeping) { 610 /* enable counter1 output to speaker */ 611 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 612 beeping = period; 613 timeout(sysbeepstop, (void *)NULL, period); 614 } 615#else 616 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 617 if (!beeping) { 618 /* Something else owns it. */ 619 splx(x); 620 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 621 } 622 mtx_lock_spin(&clock_lock); 623 outb(TIMER_CNTR2, pitch); 624 outb(TIMER_CNTR2, (pitch>>8)); 625 mtx_unlock_spin(&clock_lock); 626 if (!beeping) { 627 /* enable counter2 output to speaker */ 628 outb(IO_PPI, inb(IO_PPI) | 3); 629 beeping = period; 630 timeout(sysbeepstop, (void *)NULL, period); 631 } 632#endif 633 splx(x); 634 return (0); 635} 636 637#ifndef PC98 638/* 639 * RTC support routines 640 */ 641 642int 643rtcin(reg) 644 int reg; 645{ 646 int s; 647 u_char val; 648 649 s = splhigh(); 650 outb(IO_RTC, reg); 651 inb(0x84); 652 val = inb(IO_RTC + 1); 653 inb(0x84); 654 splx(s); 655 return (val); 656} 657 658static __inline void 659writertc(u_char reg, u_char val) 660{ 661 int s; 662 663 s = splhigh(); 664 inb(0x84); 665 outb(IO_RTC, reg); 666 inb(0x84); 667 outb(IO_RTC + 1, val); 668 inb(0x84); /* XXX work around wrong order in rtcin() */ 669 splx(s); 670} 671 672static __inline int 673readrtc(int port) 674{ 675 return(bcd2bin(rtcin(port))); 676} 677#endif 678 679#ifdef PC98 680unsigned int delaycount; 681#define FIRST_GUESS 0x2000 682static void findcpuspeed(void) 683{ 684 int i; 685 int remainder; 686 687 /* Put counter in count down mode */ 688 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 689 outb(TIMER_CNTR0, 0xff); 690 outb(TIMER_CNTR0, 0xff); 691 for (i = FIRST_GUESS; i; i--) 692 ; 693 remainder = getit(); 694 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 695} 696#endif 697 698#ifdef PC98 699static u_int 700calibrate_clocks(void) 701{ 702 int timeout; 703 u_int count, prev_count, tot_count; 704 u_short sec, start_sec; 705 706 if (bootverbose) 707 printf("Calibrating clock(s) ... "); 708 /* Check ARTIC. */ 709 if (!(PC98_SYSTEM_PARAMETER(0x458) & 0x80) && 710 !(PC98_SYSTEM_PARAMETER(0x45b) & 0x04)) 711 goto fail; 712 timeout = 100000000; 713 714 /* Read the ARTIC. */ 715 sec = inw(0x5e); 716 717 /* Wait for the ARTIC to changes. */ 718 start_sec = sec; 719 for (;;) { 720 sec = inw(0x5e); 721 if (sec != start_sec) 722 break; 723 if (--timeout == 0) 724 goto fail; 725 } 726 prev_count = getit(); 727 if (prev_count == 0 || prev_count > timer0_max_count) 728 goto fail; 729 tot_count = 0; 730 731 if (tsc_present) 732 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 733 start_sec = sec; 734 for (;;) { 735 sec = inw(0x5e); 736 count = getit(); 737 if (count == 0 || count > timer0_max_count) 738 goto fail; 739 if (count > prev_count) 740 tot_count += prev_count - (count - timer0_max_count); 741 else 742 tot_count += prev_count - count; 743 prev_count = count; 744 if ((sec == start_sec + 1200) || 745 (sec < start_sec && 746 (u_int)sec + 0x10000 == (u_int)start_sec + 1200)) 747 break; 748 if (--timeout == 0) 749 goto fail; 750 } 751 /* 752 * Read the cpu cycle counter. The timing considerations are 753 * similar to those for the i8254 clock. 754 */ 755 if (tsc_present) 756 tsc_freq = rdtsc(); 757 758 if (bootverbose) { 759 if (tsc_present) 760 printf("TSC clock: %u Hz, ", tsc_freq); 761 printf("i8254 clock: %u Hz\n", tot_count); 762 } 763 return (tot_count); 764 765fail: 766 if (bootverbose) 767 printf("failed, using default i8254 clock of %u Hz\n", 768 timer_freq); 769 return (timer_freq); 770} 771#else 772static u_int 773calibrate_clocks(void) 774{ 775 u_int64_t old_tsc; 776 u_int count, prev_count, tot_count; 777 int sec, start_sec, timeout; 778 779 if (bootverbose) 780 printf("Calibrating clock(s) ... "); 781 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 782 goto fail; 783 timeout = 100000000; 784 785 /* Read the mc146818A seconds counter. */ 786 for (;;) { 787 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 788 sec = rtcin(RTC_SEC); 789 break; 790 } 791 if (--timeout == 0) 792 goto fail; 793 } 794 795 /* Wait for the mC146818A seconds counter to change. */ 796 start_sec = sec; 797 for (;;) { 798 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 799 sec = rtcin(RTC_SEC); 800 if (sec != start_sec) 801 break; 802 } 803 if (--timeout == 0) 804 goto fail; 805 } 806 807 /* Start keeping track of the i8254 counter. */ 808 prev_count = getit(); 809 if (prev_count == 0 || prev_count > timer0_max_count) 810 goto fail; 811 tot_count = 0; 812 813 if (tsc_present) 814 old_tsc = rdtsc(); 815 else 816 old_tsc = 0; /* shut up gcc */ 817 818 /* 819 * Wait for the mc146818A seconds counter to change. Read the i8254 820 * counter for each iteration since this is convenient and only 821 * costs a few usec of inaccuracy. The timing of the final reads 822 * of the counters almost matches the timing of the initial reads, 823 * so the main cause of inaccuracy is the varying latency from 824 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 825 * rtcin(RTC_SEC) that returns a changed seconds count. The 826 * maximum inaccuracy from this cause is < 10 usec on 486's. 827 */ 828 start_sec = sec; 829 for (;;) { 830 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 831 sec = rtcin(RTC_SEC); 832 count = getit(); 833 if (count == 0 || count > timer0_max_count) 834 goto fail; 835 if (count > prev_count) 836 tot_count += prev_count - (count - timer0_max_count); 837 else 838 tot_count += prev_count - count; 839 prev_count = count; 840 if (sec != start_sec) 841 break; 842 if (--timeout == 0) 843 goto fail; 844 } 845 846 /* 847 * Read the cpu cycle counter. The timing considerations are 848 * similar to those for the i8254 clock. 849 */ 850 if (tsc_present) 851 tsc_freq = rdtsc() - old_tsc; 852 853 if (bootverbose) { 854 if (tsc_present) 855 printf("TSC clock: %u Hz, ", tsc_freq); 856 printf("i8254 clock: %u Hz\n", tot_count); 857 } 858 return (tot_count); 859 860fail: 861 if (bootverbose) 862 printf("failed, using default i8254 clock of %u Hz\n", 863 timer_freq); 864 return (timer_freq); 865} 866#endif /* !PC98 */ 867 868static void 869set_timer_freq(u_int freq, int intr_freq) 870{ 871 int new_timer0_max_count; 872 873 mtx_lock_spin(&clock_lock); 874 timer_freq = freq; 875 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 876 if (new_timer0_max_count != timer0_max_count) { 877 timer0_max_count = new_timer0_max_count; 878 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 879 outb(TIMER_CNTR0, timer0_max_count & 0xff); 880 outb(TIMER_CNTR0, timer0_max_count >> 8); 881 } 882 mtx_unlock_spin(&clock_lock); 883} 884 885/* 886 * i8254_restore is called from apm_default_resume() to reload 887 * the countdown register. 888 * this should not be necessary but there are broken laptops that 889 * do not restore the countdown register on resume. 890 * when it happnes, it messes up the hardclock interval and system clock, 891 * which leads to the infamous "calcru: negative time" problem. 892 */ 893static void 894i8254_restore(void) 895{ 896 897 mtx_lock_spin(&clock_lock); 898 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 899 outb(TIMER_CNTR0, timer0_max_count & 0xff); 900 outb(TIMER_CNTR0, timer0_max_count >> 8); 901 mtx_unlock_spin(&clock_lock); 902} 903 904#ifndef PC98 905static void 906rtc_restore(void) 907{ 908 909 /* Reenable RTC updates and interrupts. */ 910 /* XXX locking is needed for RTC access? */ 911 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 912 writertc(RTC_STATUSB, rtc_statusb); 913} 914#endif 915 916/* 917 * Restore all the timers atomically. 918 */ 919void 920timer_restore(void) 921{ 922 923 i8254_restore(); /* restore timer_freq and hz */ 924#ifndef PC98 925 rtc_restore(); /* reenable RTC interrupts */ 926#endif 927} 928 929/* 930 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 931 * XXX initialization of other timers is unintentionally left blank. 932 */ 933void 934startrtclock() 935{ 936 u_int delta, freq; 937 938#ifdef PC98 939 findcpuspeed(); 940 if (pc98_machine_type & M_8M) 941 timer_freq = 1996800L; /* 1.9968 MHz */ 942 else 943 timer_freq = 2457600L; /* 2.4576 MHz */ 944#endif /* PC98 */ 945 946 if (cpu_feature & CPUID_TSC) 947 tsc_present = 1; 948 else 949 tsc_present = 0; 950 951#ifndef PC98 952 writertc(RTC_STATUSA, rtc_statusa); 953 writertc(RTC_STATUSB, RTCSB_24HR); 954#endif 955 956 set_timer_freq(timer_freq, hz); 957 freq = calibrate_clocks(); 958#ifdef CLK_CALIBRATION_LOOP 959 if (bootverbose) { 960 printf( 961 "Press a key on the console to abort clock calibration\n"); 962 while (cncheckc() == -1) 963 calibrate_clocks(); 964 } 965#endif 966 967 /* 968 * Use the calibrated i8254 frequency if it seems reasonable. 969 * Otherwise use the default, and don't use the calibrated i586 970 * frequency. 971 */ 972 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 973 if (delta < timer_freq / 100) { 974#ifndef CLK_USE_I8254_CALIBRATION 975 if (bootverbose) 976 printf( 977"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 978 freq = timer_freq; 979#endif 980 timer_freq = freq; 981 } else { 982 if (bootverbose) 983 printf( 984 "%d Hz differs from default of %d Hz by more than 1%%\n", 985 freq, timer_freq); 986 tsc_freq = 0; 987 } 988 989 set_timer_freq(timer_freq, hz); 990 i8254_timecounter.tc_frequency = timer_freq; 991 tc_init(&i8254_timecounter); 992 993#ifndef CLK_USE_TSC_CALIBRATION 994 if (tsc_freq != 0) { 995 if (bootverbose) 996 printf( 997"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 998 tsc_freq = 0; 999 } 1000#endif 1001 if (tsc_present && tsc_freq == 0) { 1002 /* 1003 * Calibration of the i586 clock relative to the mc146818A 1004 * clock failed. Do a less accurate calibration relative 1005 * to the i8254 clock. 1006 */ 1007 u_int64_t old_tsc = rdtsc(); 1008 1009 DELAY(1000000); 1010 tsc_freq = rdtsc() - old_tsc; 1011#ifdef CLK_USE_TSC_CALIBRATION 1012 if (bootverbose) 1013 printf("TSC clock: %u Hz (Method B)\n", tsc_freq); 1014#endif 1015 } 1016 1017#if !defined(SMP) 1018 /* 1019 * We can not use the TSC in SMP mode, until we figure out a 1020 * cheap (impossible), reliable and precise (yeah right!) way 1021 * to synchronize the TSCs of all the CPUs. 1022 * Curse Intel for leaving the counter out of the I/O APIC. 1023 */ 1024 1025 /* 1026 * We can not use the TSC if we support APM. Precise timekeeping 1027 * on an APM'ed machine is at best a fools pursuit, since 1028 * any and all of the time spent in various SMM code can't 1029 * be reliably accounted for. Reading the RTC is your only 1030 * source of reliable time info. The i8254 looses too of course 1031 * but we need to have some kind of time... 1032 * We don't know at this point whether APM is going to be used 1033 * or not, nor when it might be activated. Play it safe. 1034 */ 1035 if (power_pm_get_type() == POWER_PM_TYPE_APM) { 1036 if (bootverbose) 1037 printf("TSC initialization skipped: APM enabled.\n"); 1038 return; 1039 } 1040 1041 if (tsc_present && tsc_freq != 0 && !tsc_is_broken) { 1042 tsc_timecounter.tc_frequency = tsc_freq; 1043 tc_init(&tsc_timecounter); 1044 } 1045 1046#endif /* !defined(SMP) */ 1047} 1048 1049#ifdef PC98 1050static void 1051rtc_serialcombit(int i) 1052{ 1053 outb(IO_RTC, ((i&0x01)<<5)|0x07); 1054 DELAY(1); 1055 outb(IO_RTC, ((i&0x01)<<5)|0x17); 1056 DELAY(1); 1057 outb(IO_RTC, ((i&0x01)<<5)|0x07); 1058 DELAY(1); 1059} 1060 1061static void 1062rtc_serialcom(int i) 1063{ 1064 rtc_serialcombit(i&0x01); 1065 rtc_serialcombit((i&0x02)>>1); 1066 rtc_serialcombit((i&0x04)>>2); 1067 rtc_serialcombit((i&0x08)>>3); 1068 outb(IO_RTC, 0x07); 1069 DELAY(1); 1070 outb(IO_RTC, 0x0f); 1071 DELAY(1); 1072 outb(IO_RTC, 0x07); 1073 DELAY(1); 1074} 1075 1076static void 1077rtc_outb(int val) 1078{ 1079 int s; 1080 int sa = 0; 1081 1082 for (s=0;s<8;s++) { 1083 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 1084 outb(IO_RTC, sa); /* set DI & CLK 0 */ 1085 DELAY(1); 1086 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 1087 DELAY(1); 1088 } 1089 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 1090} 1091 1092static int 1093rtc_inb(void) 1094{ 1095 int s; 1096 int sa = 0; 1097 1098 for (s=0;s<8;s++) { 1099 sa |= ((inb(0x33) & 0x01) << s); 1100 outb(IO_RTC, 0x17); /* CLK 1 */ 1101 DELAY(1); 1102 outb(IO_RTC, 0x07); /* CLK 0 */ 1103 DELAY(2); 1104 } 1105 return sa; 1106} 1107#endif /* PC-98 */ 1108 1109/* 1110 * Initialize the time of day register, based on the time base which is, e.g. 1111 * from a filesystem. 1112 */ 1113void 1114inittodr(time_t base) 1115{ 1116 unsigned long sec, days; 1117 int year, month; 1118 int y, m, s; 1119 struct timespec ts; 1120#ifdef PC98 1121 int second, min, hour; 1122#endif 1123 1124 if (base) { 1125 s = splclock(); 1126 ts.tv_sec = base; 1127 ts.tv_nsec = 0; 1128 tc_setclock(&ts); 1129 splx(s); 1130 } 1131 1132#ifdef PC98 1133 rtc_serialcom(0x03); /* Time Read */ 1134 rtc_serialcom(0x01); /* Register shift command. */ 1135 DELAY(20); 1136 1137 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 1138 min = bcd2bin(rtc_inb() & 0xff); /* min */ 1139 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 1140 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 1141 1142 month = (rtc_inb() >> 4) & 0x0f; /* month */ 1143 for (m = 1; m < month; m++) 1144 days += daysinmonth[m-1]; 1145 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 1146 /* 2000 year problem */ 1147 if (year < 1995) 1148 year += 100; 1149 if (year < 1970) 1150 goto wrong_time; 1151 for (y = 1970; y < year; y++) 1152 days += DAYSPERYEAR + LEAPYEAR(y); 1153 if ((month > 2) && LEAPYEAR(year)) 1154 days ++; 1155 sec = ((( days * 24 + 1156 hour) * 60 + 1157 min) * 60 + 1158 second); 1159 /* sec now contains the number of seconds, since Jan 1 1970, 1160 in the local time zone */ 1161 1162 s = splhigh(); 1163#else /* IBM-PC */ 1164 /* Look if we have a RTC present and the time is valid */ 1165 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 1166 goto wrong_time; 1167 1168 /* wait for time update to complete */ 1169 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 1170 s = splhigh(); 1171 while (rtcin(RTC_STATUSA) & RTCSA_TUP) { 1172 splx(s); 1173 s = splhigh(); 1174 } 1175 1176 days = 0; 1177#ifdef USE_RTC_CENTURY 1178 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 1179#else 1180 year = readrtc(RTC_YEAR) + 1900; 1181 if (year < 1970) 1182 year += 100; 1183#endif 1184 if (year < 1970) { 1185 splx(s); 1186 goto wrong_time; 1187 } 1188 month = readrtc(RTC_MONTH); 1189 for (m = 1; m < month; m++) 1190 days += daysinmonth[m-1]; 1191 if ((month > 2) && LEAPYEAR(year)) 1192 days ++; 1193 days += readrtc(RTC_DAY) - 1; 1194 for (y = 1970; y < year; y++) 1195 days += DAYSPERYEAR + LEAPYEAR(y); 1196 sec = ((( days * 24 + 1197 readrtc(RTC_HRS)) * 60 + 1198 readrtc(RTC_MIN)) * 60 + 1199 readrtc(RTC_SEC)); 1200 /* sec now contains the number of seconds, since Jan 1 1970, 1201 in the local time zone */ 1202#endif 1203 1204 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1205 1206 y = time_second - sec; 1207 if (y <= -2 || y >= 2) { 1208 /* badly off, adjust it */ 1209 ts.tv_sec = sec; 1210 ts.tv_nsec = 0; 1211 tc_setclock(&ts); 1212 } 1213 splx(s); 1214 return; 1215 1216wrong_time: 1217 printf("Invalid time in real time clock.\n"); 1218 printf("Check and reset the date immediately!\n"); 1219} 1220 1221/* 1222 * Write system time back to RTC 1223 */ 1224void 1225resettodr() 1226{ 1227 unsigned long tm; 1228 int y, m, s; 1229#ifdef PC98 1230 int wd; 1231#endif 1232 1233 if (disable_rtc_set) 1234 return; 1235 1236 s = splclock(); 1237 tm = time_second; 1238 splx(s); 1239 1240#ifdef PC98 1241 rtc_serialcom(0x01); /* Register shift command. */ 1242 1243 /* Calculate local time to put in RTC */ 1244 1245 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1246 1247 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1248 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1249 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1250 1251 /* We have now the days since 01-01-1970 in tm */ 1252 wd = (tm+4)%7; 1253 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1254 tm >= m; 1255 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1256 tm -= m; 1257 1258 /* Now we have the years in y and the day-of-the-year in tm */ 1259 for (m = 0; ; m++) { 1260 int ml; 1261 1262 ml = daysinmonth[m]; 1263 if (m == 1 && LEAPYEAR(y)) 1264 ml++; 1265 if (tm < ml) 1266 break; 1267 tm -= ml; 1268 } 1269 1270 m++; 1271 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1272 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1273 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1274 1275 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1276 rtc_serialcom(0x00); /* Register hold command. */ 1277#else 1278 /* Disable RTC updates and interrupts. */ 1279 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1280 1281 /* Calculate local time to put in RTC */ 1282 1283 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1284 1285 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1286 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1287 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1288 1289 /* We have now the days since 01-01-1970 in tm */ 1290 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1291 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1292 tm >= m; 1293 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1294 tm -= m; 1295 1296 /* Now we have the years in y and the day-of-the-year in tm */ 1297 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1298#ifdef USE_RTC_CENTURY 1299 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1300#endif 1301 for (m = 0; ; m++) { 1302 int ml; 1303 1304 ml = daysinmonth[m]; 1305 if (m == 1 && LEAPYEAR(y)) 1306 ml++; 1307 if (tm < ml) 1308 break; 1309 tm -= ml; 1310 } 1311 1312 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1313 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1314 1315 /* Reenable RTC updates and interrupts. */ 1316 writertc(RTC_STATUSB, rtc_statusb); 1317#endif /* PC98 */ 1318} 1319 1320 1321/* 1322 * Start both clocks running. 1323 */ 1324void 1325cpu_initclocks() 1326{ 1327#ifndef PC98 1328 int diag; 1329#endif 1330#ifdef APIC_IO 1331 int apic_8254_trial; 1332 void *clkdesc; 1333#endif /* APIC_IO */ 1334 1335#ifndef PC98 1336 if (statclock_disable) { 1337 /* 1338 * The stat interrupt mask is different without the 1339 * statistics clock. Also, don't set the interrupt 1340 * flag which would normally cause the RTC to generate 1341 * interrupts. 1342 */ 1343 rtc_statusb = RTCSB_24HR; 1344 } else { 1345 /* Setting stathz to nonzero early helps avoid races. */ 1346 stathz = RTC_NOPROFRATE; 1347 profhz = RTC_PROFRATE; 1348 } 1349#endif 1350 1351 /* Finish initializing 8253 timer 0. */ 1352#ifdef APIC_IO 1353 1354 apic_8254_intr = isa_apic_irq(0); 1355 apic_8254_trial = 0; 1356 if (apic_8254_intr >= 0 ) { 1357 if (apic_int_type(0, 0) == 3) 1358 apic_8254_trial = 1; 1359 } else { 1360 /* look for ExtInt on pin 0 */ 1361 if (apic_int_type(0, 0) == 3) { 1362 apic_8254_intr = apic_irq(0, 0); 1363 setup_8254_mixed_mode(); 1364 } else 1365 panic("APIC_IO: Cannot route 8254 interrupt to CPU"); 1366 } 1367 1368 inthand_add("clk", apic_8254_intr, (driver_intr_t *)clkintr, NULL, 1369 INTR_TYPE_CLK | INTR_FAST, &clkdesc); 1370 mtx_lock_spin(&icu_lock); 1371 INTREN(1 << apic_8254_intr); 1372 mtx_unlock_spin(&icu_lock); 1373 1374#else /* APIC_IO */ 1375 1376 /* 1377 * XXX Check the priority of this interrupt handler. I 1378 * couldn't find anything suitable in the BSD/OS code (grog, 1379 * 19 July 2000). 1380 */ 1381 inthand_add("clk", 0, (driver_intr_t *)clkintr, NULL, 1382 INTR_TYPE_CLK | INTR_FAST, NULL); 1383 mtx_lock_spin(&icu_lock); 1384 INTREN(IRQ0); 1385 mtx_unlock_spin(&icu_lock); 1386 1387#endif /* APIC_IO */ 1388 1389#ifndef PC98 1390 /* Initialize RTC. */ 1391 writertc(RTC_STATUSA, rtc_statusa); 1392 writertc(RTC_STATUSB, RTCSB_24HR); 1393 1394 /* Don't bother enabling the statistics clock. */ 1395 if (statclock_disable) 1396 return; 1397 diag = rtcin(RTC_DIAG); 1398 if (diag != 0) 1399 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1400#endif /* !PC98 */ 1401 1402#ifndef PC98 1403#ifdef APIC_IO 1404 if (isa_apic_irq(8) != 8) 1405 panic("APIC RTC != 8"); 1406#endif /* APIC_IO */ 1407 1408 inthand_add("rtc", 8, (driver_intr_t *)rtcintr, NULL, 1409 INTR_TYPE_CLK | INTR_FAST, NULL); 1410 1411 mtx_lock_spin(&icu_lock); 1412#ifdef APIC_IO 1413 INTREN(APIC_IRQ8); 1414#else 1415 INTREN(IRQ8); 1416#endif /* APIC_IO */ 1417 mtx_unlock_spin(&icu_lock); 1418 1419 writertc(RTC_STATUSB, rtc_statusb); 1420#endif /* PC98 */ 1421 1422#ifdef APIC_IO 1423 if (apic_8254_trial) { 1424 1425 printf("APIC_IO: Testing 8254 interrupt delivery\n"); 1426 while (read_intr_count(8) < 6) 1427 ; /* nothing */ 1428 if (read_intr_count(apic_8254_intr) < 3) { 1429 /* 1430 * The MP table is broken. 1431 * The 8254 was not connected to the specified pin 1432 * on the IO APIC. 1433 * Workaround: Limited variant of mixed mode. 1434 */ 1435 mtx_lock_spin(&icu_lock); 1436 INTRDIS(1 << apic_8254_intr); 1437 mtx_unlock_spin(&icu_lock); 1438 inthand_remove(clkdesc); 1439 printf("APIC_IO: Broken MP table detected: " 1440 "8254 is not connected to " 1441 "IOAPIC #%d intpin %d\n", 1442 int_to_apicintpin[apic_8254_intr].ioapic, 1443 int_to_apicintpin[apic_8254_intr].int_pin); 1444 /* 1445 * Revoke current ISA IRQ 0 assignment and 1446 * configure a fallback interrupt routing from 1447 * the 8254 Timer via the 8259 PIC to the 1448 * an ExtInt interrupt line on IOAPIC #0 intpin 0. 1449 * We reuse the low level interrupt handler number. 1450 */ 1451 if (apic_irq(0, 0) < 0) { 1452 revoke_apic_irq(apic_8254_intr); 1453 assign_apic_irq(0, 0, apic_8254_intr); 1454 } 1455 apic_8254_intr = apic_irq(0, 0); 1456 setup_8254_mixed_mode(); 1457 inthand_add("clk", apic_8254_intr, 1458 (driver_intr_t *)clkintr, NULL, 1459 INTR_TYPE_CLK | INTR_FAST, NULL); 1460 mtx_lock_spin(&icu_lock); 1461 INTREN(1 << apic_8254_intr); 1462 mtx_unlock_spin(&icu_lock); 1463 } 1464 1465 } 1466 if (apic_int_type(0, 0) != 3 || 1467 int_to_apicintpin[apic_8254_intr].ioapic != 0 || 1468 int_to_apicintpin[apic_8254_intr].int_pin != 0) 1469 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n", 1470 int_to_apicintpin[apic_8254_intr].ioapic, 1471 int_to_apicintpin[apic_8254_intr].int_pin); 1472 else 1473 printf("APIC_IO: " 1474 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n"); 1475#endif 1476 1477} 1478 1479#ifdef APIC_IO 1480static u_long 1481read_intr_count(int vec) 1482{ 1483 u_long *up; 1484 up = intr_countp[vec]; 1485 if (up) 1486 return *up; 1487 return 0UL; 1488} 1489 1490static void 1491setup_8254_mixed_mode() 1492{ 1493 /* 1494 * Allow 8254 timer to INTerrupt 8259: 1495 * re-initialize master 8259: 1496 * reset; prog 4 bytes, single ICU, edge triggered 1497 */ 1498 outb(IO_ICU1, 0x13); 1499#ifdef PC98 1500 outb(IO_ICU1 + 2, NRSVIDT); /* start vector (unused) */ 1501 outb(IO_ICU1 + 2, 0x00); /* ignore slave */ 1502 outb(IO_ICU1 + 2, 0x03); /* auto EOI, 8086 */ 1503 outb(IO_ICU1 + 2, 0xfe); /* unmask INT0 */ 1504#else 1505 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */ 1506 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1507 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1508 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1509#endif 1510 1511 /* program IO APIC for type 3 INT on INT0 */ 1512 if (ext_int_setup(0, 0) < 0) 1513 panic("8254 redirect via APIC pin0 impossible!"); 1514} 1515#endif 1516 1517void 1518setstatclockrate(int newhz) 1519{ 1520#ifndef PC98 1521 if (newhz == RTC_PROFRATE) 1522 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1523 else 1524 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1525 writertc(RTC_STATUSA, rtc_statusa); 1526#endif 1527} 1528 1529static int 1530sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS) 1531{ 1532 int error; 1533 u_int freq; 1534 1535 /* 1536 * Use `i8254' instead of `timer' in external names because `timer' 1537 * is is too generic. Should use it everywhere. 1538 */ 1539 freq = timer_freq; 1540 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 1541 if (error == 0 && req->newptr != NULL) { 1542 if (timer0_state != RELEASED) 1543 return (EBUSY); /* too much trouble to handle */ 1544 set_timer_freq(freq, hz); 1545 i8254_timecounter.tc_frequency = freq; 1546 tc_update(&i8254_timecounter); 1547 } 1548 return (error); 1549} 1550 1551SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1552 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1553 1554static int 1555sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS) 1556{ 1557 int error; 1558 u_int freq; 1559 1560 if (tsc_timecounter.tc_frequency == 0) 1561 return (EOPNOTSUPP); 1562 freq = tsc_freq; 1563 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 1564 if (error == 0 && req->newptr != NULL) { 1565 tsc_freq = freq; 1566 tsc_timecounter.tc_frequency = tsc_freq; 1567 tc_update(&tsc_timecounter); 1568 } 1569 return (error); 1570} 1571 1572SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW, 1573 0, sizeof(u_int), sysctl_machdep_tsc_freq, "I", ""); 1574 1575static unsigned 1576i8254_get_timecount(struct timecounter *tc) 1577{ 1578 u_int count; 1579 u_int high, low; 1580 u_int eflags; 1581 1582 eflags = read_eflags(); 1583 mtx_lock_spin(&clock_lock); 1584 1585 /* Select timer0 and latch counter value. */ 1586 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 1587 1588 low = inb(TIMER_CNTR0); 1589 high = inb(TIMER_CNTR0); 1590 count = timer0_max_count - ((high << 8) | low); 1591 if (count < i8254_lastcount || 1592 (!i8254_ticked && (clkintr_pending || 1593 ((count < 20 || (!(eflags & PSL_I) && count < timer0_max_count / 2u)) && 1594#ifdef APIC_IO 1595#define lapic_irr1 ((volatile u_int *)&lapic)[0x210 / 4] /* XXX XXX */ 1596 /* XXX this assumes that apic_8254_intr is < 24. */ 1597 (lapic_irr1 & (1 << apic_8254_intr)))) 1598#else 1599 (inb(IO_ICU1) & 1))) 1600#endif 1601 )) { 1602 i8254_ticked = 1; 1603 i8254_offset += timer0_max_count; 1604 } 1605 i8254_lastcount = count; 1606 count += i8254_offset; 1607 mtx_unlock_spin(&clock_lock); 1608 return (count); 1609} 1610 1611static unsigned 1612tsc_get_timecount(struct timecounter *tc) 1613{ 1614 return (rdtsc()); 1615} 1616 1617#ifdef DEV_ISA 1618/* 1619 * Attach to the ISA PnP descriptors for the timer and realtime clock. 1620 */ 1621static struct isa_pnp_id attimer_ids[] = { 1622 { 0x0001d041 /* PNP0100 */, "AT timer" }, 1623 { 0x000bd041 /* PNP0B00 */, "AT realtime clock" }, 1624 { 0 } 1625}; 1626 1627static int 1628attimer_probe(device_t dev) 1629{ 1630 int result; 1631 1632 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids)) <= 0) 1633 device_quiet(dev); 1634 return(result); 1635} 1636 1637static int 1638attimer_attach(device_t dev) 1639{ 1640 return(0); 1641} 1642 1643static device_method_t attimer_methods[] = { 1644 /* Device interface */ 1645 DEVMETHOD(device_probe, attimer_probe), 1646 DEVMETHOD(device_attach, attimer_attach), 1647 DEVMETHOD(device_detach, bus_generic_detach), 1648 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1649 DEVMETHOD(device_suspend, bus_generic_suspend), /* XXX stop statclock? */ 1650 DEVMETHOD(device_resume, bus_generic_resume), /* XXX restart statclock? */ 1651 { 0, 0 } 1652}; 1653 1654static driver_t attimer_driver = { 1655 "attimer", 1656 attimer_methods, 1657 1, /* no softc */ 1658}; 1659 1660static devclass_t attimer_devclass; 1661 1662DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0); 1663#ifndef PC98 1664DRIVER_MODULE(attimer, acpi, attimer_driver, attimer_devclass, 0, 0); 1665#endif 1666#endif /* DEV_ISA */ 1667