pcrtc.c revision 76650
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $FreeBSD: head/sys/pc98/cbus/pcrtc.c 76650 2001-05-15 23:22:29Z jhb $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51/* 52 * modified for PC98 by Kakefuda 53 */ 54 55#include "opt_clock.h" 56#include "opt_apm.h" 57#include "opt_mca.h" 58 59#include <sys/param.h> 60#include <sys/systm.h> 61#include <sys/bus.h> 62#include <sys/lock.h> 63#include <sys/mutex.h> 64#include <sys/proc.h> 65#include <sys/time.h> 66#include <sys/timetc.h> 67#include <sys/kernel.h> 68#include <sys/sysctl.h> 69#include <sys/cons.h> 70 71#include <machine/clock.h> 72#ifdef CLK_CALIBRATION_LOOP 73#endif 74#include <machine/cputypes.h> 75#include <machine/frame.h> 76#include <machine/limits.h> 77#include <machine/md_var.h> 78#include <machine/psl.h> 79#ifdef APIC_IO 80#include <machine/segments.h> 81#endif 82#if defined(SMP) || defined(APIC_IO) 83#include <machine/smp.h> 84#endif /* SMP || APIC_IO */ 85#include <machine/specialreg.h> 86 87#include <i386/isa/icu.h> 88#ifdef PC98 89#include <pc98/pc98/pc98.h> 90#include <pc98/pc98/pc98_machdep.h> 91#include <i386/isa/isa_device.h> 92#else 93#include <i386/isa/isa.h> 94#include <isa/rtc.h> 95#endif 96#include <isa/isavar.h> 97#include <i386/isa/timerreg.h> 98 99#include <i386/isa/intr_machdep.h> 100 101#ifdef DEV_MCA 102#include <i386/isa/mca_machdep.h> 103#endif 104 105#ifdef APIC_IO 106#include <i386/isa/intr_machdep.h> 107/* The interrupt triggered by the 8254 (timer) chip */ 108int apic_8254_intr; 109static u_long read_intr_count __P((int vec)); 110static void setup_8254_mixed_mode __P((void)); 111#endif 112 113/* 114 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 115 * can use a simple formula for leap years. 116 */ 117#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 118#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 119 120#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 121 122/* 123 * Time in timer cycles that it takes for microtime() to disable interrupts 124 * and latch the count. microtime() currently uses "cli; outb ..." so it 125 * normally takes less than 2 timer cycles. Add a few for cache misses. 126 * Add a few more to allow for latency in bogus calls to microtime() with 127 * interrupts already disabled. 128 */ 129#define TIMER0_LATCH_COUNT 20 130 131/* 132 * Maximum frequency that we are willing to allow for timer0. Must be 133 * low enough to guarantee that the timer interrupt handler returns 134 * before the next timer interrupt. 135 */ 136#define TIMER0_MAX_FREQ 20000 137 138int adjkerntz; /* local offset from GMT in seconds */ 139int clkintr_pending; 140int disable_rtc_set; /* disable resettodr() if != 0 */ 141int statclock_disable; 142#ifndef TIMER_FREQ 143#ifdef PC98 144#define TIMER_FREQ 2457600; 145#else /* IBM-PC */ 146#define TIMER_FREQ 1193182; 147#endif /* PC98 */ 148#endif 149u_int timer_freq = TIMER_FREQ; 150int timer0_max_count; 151u_int tsc_freq; 152int tsc_is_broken; 153u_int tsc_present; 154int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 155struct mtx clock_lock; 156 157static int beeping = 0; 158static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 159static u_int hardclock_max_count; 160static u_int32_t i8254_lastcount; 161static u_int32_t i8254_offset; 162static int i8254_ticked; 163/* 164 * XXX new_function and timer_func should not handle clockframes, but 165 * timer_func currently needs to hold hardclock to handle the 166 * timer0_state == 0 case. We should use inthand_add()/inthand_remove() 167 * to switch between clkintr() and a slightly different timerintr(). 168 */ 169static void (*new_function) __P((struct clockframe *frame)); 170static u_int new_rate; 171#ifndef PC98 172static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 173static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 174#endif 175static u_int timer0_prescaler_count; 176 177/* Values for timerX_state: */ 178#define RELEASED 0 179#define RELEASE_PENDING 1 180#define ACQUIRED 2 181#define ACQUIRE_PENDING 3 182 183static u_char timer0_state; 184#ifdef PC98 185static u_char timer1_state; 186#endif 187static u_char timer2_state; 188static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 189#ifdef PC98 190static void rtc_serialcombit __P((int)); 191static void rtc_serialcom __P((int)); 192static int rtc_inb __P((void)); 193static void rtc_outb __P((int)); 194#endif 195 196static unsigned i8254_get_timecount __P((struct timecounter *tc)); 197static unsigned tsc_get_timecount __P((struct timecounter *tc)); 198static void set_timer_freq(u_int freq, int intr_freq); 199 200static struct timecounter tsc_timecounter = { 201 tsc_get_timecount, /* get_timecount */ 202 0, /* no poll_pps */ 203 ~0u, /* counter_mask */ 204 0, /* frequency */ 205 "TSC" /* name */ 206}; 207 208SYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD, 209 &tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", ""); 210 211static struct timecounter i8254_timecounter = { 212 i8254_get_timecount, /* get_timecount */ 213 0, /* no poll_pps */ 214 ~0u, /* counter_mask */ 215 0, /* frequency */ 216 "i8254" /* name */ 217}; 218 219SYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD, 220 &i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", ""); 221 222static void 223clkintr(struct clockframe frame) 224{ 225 226 if (timecounter->tc_get_timecount == i8254_get_timecount) { 227 mtx_lock_spin(&clock_lock); 228 if (i8254_ticked) 229 i8254_ticked = 0; 230 else { 231 i8254_offset += timer0_max_count; 232 i8254_lastcount = 0; 233 } 234 clkintr_pending = 0; 235 mtx_unlock_spin(&clock_lock); 236 } 237 timer_func(&frame); 238#ifdef SMP 239 if (timer_func == hardclock) 240 forward_hardclock(); 241#endif 242 switch (timer0_state) { 243 244 case RELEASED: 245 break; 246 247 case ACQUIRED: 248 if ((timer0_prescaler_count += timer0_max_count) 249 >= hardclock_max_count) { 250 timer0_prescaler_count -= hardclock_max_count; 251 hardclock(&frame); 252#ifdef SMP 253 forward_hardclock(); 254#endif 255 } 256 break; 257 258 case ACQUIRE_PENDING: 259 mtx_lock_spin(&clock_lock); 260 i8254_offset = i8254_get_timecount(NULL); 261 i8254_lastcount = 0; 262 timer0_max_count = TIMER_DIV(new_rate); 263 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 264 outb(TIMER_CNTR0, timer0_max_count & 0xff); 265 outb(TIMER_CNTR0, timer0_max_count >> 8); 266 mtx_unlock_spin(&clock_lock); 267 timer_func = new_function; 268 timer0_state = ACQUIRED; 269 break; 270 271 case RELEASE_PENDING: 272 if ((timer0_prescaler_count += timer0_max_count) 273 >= hardclock_max_count) { 274 mtx_lock_spin(&clock_lock); 275 i8254_offset = i8254_get_timecount(NULL); 276 i8254_lastcount = 0; 277 timer0_max_count = hardclock_max_count; 278 outb(TIMER_MODE, 279 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 280 outb(TIMER_CNTR0, timer0_max_count & 0xff); 281 outb(TIMER_CNTR0, timer0_max_count >> 8); 282 mtx_unlock_spin(&clock_lock); 283 timer0_prescaler_count = 0; 284 timer_func = hardclock; 285 timer0_state = RELEASED; 286 hardclock(&frame); 287#ifdef SMP 288 forward_hardclock(); 289#endif 290 } 291 break; 292 } 293#ifdef DEV_MCA 294 /* Reset clock interrupt by asserting bit 7 of port 0x61 */ 295 if (MCA_system) 296 outb(0x61, inb(0x61) | 0x80); 297#endif 298} 299 300/* 301 * The acquire and release functions must be called at ipl >= splclock(). 302 */ 303int 304acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 305{ 306 static int old_rate; 307 308 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 309 return (-1); 310 switch (timer0_state) { 311 312 case RELEASED: 313 timer0_state = ACQUIRE_PENDING; 314 break; 315 316 case RELEASE_PENDING: 317 if (rate != old_rate) 318 return (-1); 319 /* 320 * The timer has been released recently, but is being 321 * re-acquired before the release completed. In this 322 * case, we simply reclaim it as if it had not been 323 * released at all. 324 */ 325 timer0_state = ACQUIRED; 326 break; 327 328 default: 329 return (-1); /* busy */ 330 } 331 new_function = function; 332 old_rate = new_rate = rate; 333 return (0); 334} 335 336#ifdef PC98 337int 338acquire_timer1(int mode) 339{ 340 341 if (timer1_state != RELEASED) 342 return (-1); 343 timer1_state = ACQUIRED; 344 345 /* 346 * This access to the timer registers is as atomic as possible 347 * because it is a single instruction. We could do better if we 348 * knew the rate. Use of splclock() limits glitches to 10-100us, 349 * and this is probably good enough for timer2, so we aren't as 350 * careful with it as with timer0. 351 */ 352 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 353 354 return (0); 355} 356#endif 357 358int 359acquire_timer2(int mode) 360{ 361 362 if (timer2_state != RELEASED) 363 return (-1); 364 timer2_state = ACQUIRED; 365 366 /* 367 * This access to the timer registers is as atomic as possible 368 * because it is a single instruction. We could do better if we 369 * knew the rate. Use of splclock() limits glitches to 10-100us, 370 * and this is probably good enough for timer2, so we aren't as 371 * careful with it as with timer0. 372 */ 373 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 374 375 return (0); 376} 377 378int 379release_timer0() 380{ 381 switch (timer0_state) { 382 383 case ACQUIRED: 384 timer0_state = RELEASE_PENDING; 385 break; 386 387 case ACQUIRE_PENDING: 388 /* Nothing happened yet, release quickly. */ 389 timer0_state = RELEASED; 390 break; 391 392 default: 393 return (-1); 394 } 395 return (0); 396} 397 398#ifdef PC98 399int 400release_timer1() 401{ 402 403 if (timer1_state != ACQUIRED) 404 return (-1); 405 timer1_state = RELEASED; 406 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 407 return (0); 408} 409#endif 410 411int 412release_timer2() 413{ 414 415 if (timer2_state != ACQUIRED) 416 return (-1); 417 timer2_state = RELEASED; 418 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 419 return (0); 420} 421 422#ifndef PC98 423/* 424 * This routine receives statistical clock interrupts from the RTC. 425 * As explained above, these occur at 128 interrupts per second. 426 * When profiling, we receive interrupts at a rate of 1024 Hz. 427 * 428 * This does not actually add as much overhead as it sounds, because 429 * when the statistical clock is active, the hardclock driver no longer 430 * needs to keep (inaccurate) statistics on its own. This decouples 431 * statistics gathering from scheduling interrupts. 432 * 433 * The RTC chip requires that we read status register C (RTC_INTR) 434 * to acknowledge an interrupt, before it will generate the next one. 435 * Under high interrupt load, rtcintr() can be indefinitely delayed and 436 * the clock can tick immediately after the read from RTC_INTR. In this 437 * case, the mc146818A interrupt signal will not drop for long enough 438 * to register with the 8259 PIC. If an interrupt is missed, the stat 439 * clock will halt, considerably degrading system performance. This is 440 * why we use 'while' rather than a more straightforward 'if' below. 441 * Stat clock ticks can still be lost, causing minor loss of accuracy 442 * in the statistics, but the stat clock will no longer stop. 443 */ 444static void 445rtcintr(struct clockframe frame) 446{ 447 while (rtcin(RTC_INTR) & RTCIR_PERIOD) { 448 statclock(&frame); 449#ifdef SMP 450 forward_statclock(); 451#endif 452 } 453} 454 455#include "opt_ddb.h" 456#ifdef DDB 457#include <ddb/ddb.h> 458 459DB_SHOW_COMMAND(rtc, rtc) 460{ 461 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 462 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 463 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 464 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 465} 466#endif /* DDB */ 467#endif /* for PC98 */ 468 469static int 470getit(void) 471{ 472 int high, low; 473 474 mtx_lock_spin(&clock_lock); 475 476 /* Select timer0 and latch counter value. */ 477 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 478 479 low = inb(TIMER_CNTR0); 480 high = inb(TIMER_CNTR0); 481 482 mtx_unlock_spin(&clock_lock); 483 return ((high << 8) | low); 484} 485 486/* 487 * Wait "n" microseconds. 488 * Relies on timer 1 counting down from (timer_freq / hz) 489 * Note: timer had better have been programmed before this is first used! 490 */ 491void 492DELAY(int n) 493{ 494 int delta, prev_tick, tick, ticks_left; 495 496#ifdef DELAYDEBUG 497 int getit_calls = 1; 498 int n1; 499 static int state = 0; 500 501 if (state == 0) { 502 state = 1; 503 for (n1 = 1; n1 <= 10000000; n1 *= 10) 504 DELAY(n1); 505 state = 2; 506 } 507 if (state == 1) 508 printf("DELAY(%d)...", n); 509#endif 510 /* 511 * Guard against the timer being uninitialized if we are called 512 * early for console i/o. 513 */ 514 if (timer0_max_count == 0) 515 set_timer_freq(timer_freq, hz); 516 517 /* 518 * Read the counter first, so that the rest of the setup overhead is 519 * counted. Guess the initial overhead is 20 usec (on most systems it 520 * takes about 1.5 usec for each of the i/o's in getit(). The loop 521 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 522 * multiplications and divisions to scale the count take a while). 523 */ 524 prev_tick = getit(); 525 n -= 0; /* XXX actually guess no initial overhead */ 526 /* 527 * Calculate (n * (timer_freq / 1e6)) without using floating point 528 * and without any avoidable overflows. 529 */ 530 if (n <= 0) 531 ticks_left = 0; 532 else if (n < 256) 533 /* 534 * Use fixed point to avoid a slow division by 1000000. 535 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 536 * 2^15 is the first power of 2 that gives exact results 537 * for n between 0 and 256. 538 */ 539 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 540 else 541 /* 542 * Don't bother using fixed point, although gcc-2.7.2 543 * generates particularly poor code for the long long 544 * division, since even the slow way will complete long 545 * before the delay is up (unless we're interrupted). 546 */ 547 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 548 / 1000000; 549 550 while (ticks_left > 0) { 551 tick = getit(); 552#ifdef DELAYDEBUG 553 ++getit_calls; 554#endif 555 delta = prev_tick - tick; 556 prev_tick = tick; 557 if (delta < 0) { 558 delta += timer0_max_count; 559 /* 560 * Guard against timer0_max_count being wrong. 561 * This shouldn't happen in normal operation, 562 * but it may happen if set_timer_freq() is 563 * traced. 564 */ 565 if (delta < 0) 566 delta = 0; 567 } 568 ticks_left -= delta; 569 } 570#ifdef DELAYDEBUG 571 if (state == 1) 572 printf(" %d calls to getit() at %d usec each\n", 573 getit_calls, (n + 5) / getit_calls); 574#endif 575} 576 577static void 578sysbeepstop(void *chan) 579{ 580#ifdef PC98 /* PC98 */ 581 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 582 release_timer1(); 583#else 584 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 585 release_timer2(); 586#endif 587 beeping = 0; 588} 589 590int 591sysbeep(int pitch, int period) 592{ 593 int x = splclock(); 594 595#ifdef PC98 596 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 597 if (!beeping) { 598 /* Something else owns it. */ 599 splx(x); 600 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 601 } 602 disable_intr(); 603 outb(0x3fdb, pitch); 604 outb(0x3fdb, (pitch>>8)); 605 enable_intr(); 606 if (!beeping) { 607 /* enable counter1 output to speaker */ 608 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 609 beeping = period; 610 timeout(sysbeepstop, (void *)NULL, period); 611 } 612#else 613 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 614 if (!beeping) { 615 /* Something else owns it. */ 616 splx(x); 617 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 618 } 619 mtx_lock_spin(&clock_lock); 620 outb(TIMER_CNTR2, pitch); 621 outb(TIMER_CNTR2, (pitch>>8)); 622 mtx_unlock_spin(&clock_lock); 623 if (!beeping) { 624 /* enable counter2 output to speaker */ 625 outb(IO_PPI, inb(IO_PPI) | 3); 626 beeping = period; 627 timeout(sysbeepstop, (void *)NULL, period); 628 } 629#endif 630 splx(x); 631 return (0); 632} 633 634#ifndef PC98 635/* 636 * RTC support routines 637 */ 638 639int 640rtcin(reg) 641 int reg; 642{ 643 int s; 644 u_char val; 645 646 s = splhigh(); 647 outb(IO_RTC, reg); 648 inb(0x84); 649 val = inb(IO_RTC + 1); 650 inb(0x84); 651 splx(s); 652 return (val); 653} 654 655static __inline void 656writertc(u_char reg, u_char val) 657{ 658 int s; 659 660 s = splhigh(); 661 inb(0x84); 662 outb(IO_RTC, reg); 663 inb(0x84); 664 outb(IO_RTC + 1, val); 665 inb(0x84); /* XXX work around wrong order in rtcin() */ 666 splx(s); 667} 668 669static __inline int 670readrtc(int port) 671{ 672 return(bcd2bin(rtcin(port))); 673} 674#endif 675 676#ifdef PC98 677unsigned int delaycount; 678#define FIRST_GUESS 0x2000 679static void findcpuspeed(void) 680{ 681 int i; 682 int remainder; 683 684 /* Put counter in count down mode */ 685 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 686 outb(TIMER_CNTR0, 0xff); 687 outb(TIMER_CNTR0, 0xff); 688 for (i = FIRST_GUESS; i; i--) 689 ; 690 remainder = getit(); 691 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 692} 693#endif 694 695#ifdef PC98 696static u_int 697calibrate_clocks(void) 698{ 699 int timeout; 700 u_int count, prev_count, tot_count; 701 u_short sec, start_sec; 702 703 if (bootverbose) 704 printf("Calibrating clock(s) ... "); 705 /* Check ARTIC. */ 706 if (!(PC98_SYSTEM_PARAMETER(0x458) & 0x80) && 707 !(PC98_SYSTEM_PARAMETER(0x45b) & 0x04)) 708 goto fail; 709 timeout = 100000000; 710 711 /* Read the ARTIC. */ 712 sec = inw(0x5e); 713 714 /* Wait for the ARTIC to changes. */ 715 start_sec = sec; 716 for (;;) { 717 sec = inw(0x5e); 718 if (sec != start_sec) 719 break; 720 if (--timeout == 0) 721 goto fail; 722 } 723 prev_count = getit(); 724 if (prev_count == 0 || prev_count > timer0_max_count) 725 goto fail; 726 tot_count = 0; 727 728 if (tsc_present) 729 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 730 start_sec = sec; 731 for (;;) { 732 sec = inw(0x5e); 733 count = getit(); 734 if (count == 0 || count > timer0_max_count) 735 goto fail; 736 if (count > prev_count) 737 tot_count += prev_count - (count - timer0_max_count); 738 else 739 tot_count += prev_count - count; 740 prev_count = count; 741 if ((sec == start_sec + 1200) || 742 (sec < start_sec && 743 (u_int)sec + 0x10000 == (u_int)start_sec + 1200)) 744 break; 745 if (--timeout == 0) 746 goto fail; 747 } 748 /* 749 * Read the cpu cycle counter. The timing considerations are 750 * similar to those for the i8254 clock. 751 */ 752 if (tsc_present) 753 tsc_freq = rdtsc(); 754 755 if (bootverbose) { 756 if (tsc_present) 757 printf("TSC clock: %u Hz, ", tsc_freq); 758 printf("i8254 clock: %u Hz\n", tot_count); 759 } 760 return (tot_count); 761 762fail: 763 if (bootverbose) 764 printf("failed, using default i8254 clock of %u Hz\n", 765 timer_freq); 766 return (timer_freq); 767} 768#else 769static u_int 770calibrate_clocks(void) 771{ 772 u_int64_t old_tsc; 773 u_int count, prev_count, tot_count; 774 int sec, start_sec, timeout; 775 776 if (bootverbose) 777 printf("Calibrating clock(s) ... "); 778 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 779 goto fail; 780 timeout = 100000000; 781 782 /* Read the mc146818A seconds counter. */ 783 for (;;) { 784 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 785 sec = rtcin(RTC_SEC); 786 break; 787 } 788 if (--timeout == 0) 789 goto fail; 790 } 791 792 /* Wait for the mC146818A seconds counter to change. */ 793 start_sec = sec; 794 for (;;) { 795 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 796 sec = rtcin(RTC_SEC); 797 if (sec != start_sec) 798 break; 799 } 800 if (--timeout == 0) 801 goto fail; 802 } 803 804 /* Start keeping track of the i8254 counter. */ 805 prev_count = getit(); 806 if (prev_count == 0 || prev_count > timer0_max_count) 807 goto fail; 808 tot_count = 0; 809 810 if (tsc_present) 811 old_tsc = rdtsc(); 812 else 813 old_tsc = 0; /* shut up gcc */ 814 815 /* 816 * Wait for the mc146818A seconds counter to change. Read the i8254 817 * counter for each iteration since this is convenient and only 818 * costs a few usec of inaccuracy. The timing of the final reads 819 * of the counters almost matches the timing of the initial reads, 820 * so the main cause of inaccuracy is the varying latency from 821 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 822 * rtcin(RTC_SEC) that returns a changed seconds count. The 823 * maximum inaccuracy from this cause is < 10 usec on 486's. 824 */ 825 start_sec = sec; 826 for (;;) { 827 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 828 sec = rtcin(RTC_SEC); 829 count = getit(); 830 if (count == 0 || count > timer0_max_count) 831 goto fail; 832 if (count > prev_count) 833 tot_count += prev_count - (count - timer0_max_count); 834 else 835 tot_count += prev_count - count; 836 prev_count = count; 837 if (sec != start_sec) 838 break; 839 if (--timeout == 0) 840 goto fail; 841 } 842 843 /* 844 * Read the cpu cycle counter. The timing considerations are 845 * similar to those for the i8254 clock. 846 */ 847 if (tsc_present) 848 tsc_freq = rdtsc() - old_tsc; 849 850 if (bootverbose) { 851 if (tsc_present) 852 printf("TSC clock: %u Hz, ", tsc_freq); 853 printf("i8254 clock: %u Hz\n", tot_count); 854 } 855 return (tot_count); 856 857fail: 858 if (bootverbose) 859 printf("failed, using default i8254 clock of %u Hz\n", 860 timer_freq); 861 return (timer_freq); 862} 863#endif /* !PC98 */ 864 865static void 866set_timer_freq(u_int freq, int intr_freq) 867{ 868 int new_timer0_max_count; 869 870 mtx_lock_spin(&clock_lock); 871 timer_freq = freq; 872 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 873 if (new_timer0_max_count != timer0_max_count) { 874 timer0_max_count = new_timer0_max_count; 875 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 876 outb(TIMER_CNTR0, timer0_max_count & 0xff); 877 outb(TIMER_CNTR0, timer0_max_count >> 8); 878 } 879 mtx_unlock_spin(&clock_lock); 880} 881 882/* 883 * i8254_restore is called from apm_default_resume() to reload 884 * the countdown register. 885 * this should not be necessary but there are broken laptops that 886 * do not restore the countdown register on resume. 887 * when it happnes, it messes up the hardclock interval and system clock, 888 * which leads to the infamous "calcru: negative time" problem. 889 */ 890void 891i8254_restore(void) 892{ 893 894 mtx_lock_spin(&clock_lock); 895 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 896 outb(TIMER_CNTR0, timer0_max_count & 0xff); 897 outb(TIMER_CNTR0, timer0_max_count >> 8); 898 mtx_unlock_spin(&clock_lock); 899} 900 901/* 902 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 903 * XXX initialization of other timers is unintentionally left blank. 904 */ 905void 906startrtclock() 907{ 908 u_int delta, freq; 909 910#ifdef PC98 911 findcpuspeed(); 912 if (pc98_machine_type & M_8M) 913 timer_freq = 1996800L; /* 1.9968 MHz */ 914 else 915 timer_freq = 2457600L; /* 2.4576 MHz */ 916#endif /* PC98 */ 917 918 if (cpu_feature & CPUID_TSC) 919 tsc_present = 1; 920 else 921 tsc_present = 0; 922 923#ifndef PC98 924 writertc(RTC_STATUSA, rtc_statusa); 925 writertc(RTC_STATUSB, RTCSB_24HR); 926#endif 927 928 set_timer_freq(timer_freq, hz); 929 freq = calibrate_clocks(); 930#ifdef CLK_CALIBRATION_LOOP 931 if (bootverbose) { 932 printf( 933 "Press a key on the console to abort clock calibration\n"); 934 while (cncheckc() == -1) 935 calibrate_clocks(); 936 } 937#endif 938 939 /* 940 * Use the calibrated i8254 frequency if it seems reasonable. 941 * Otherwise use the default, and don't use the calibrated i586 942 * frequency. 943 */ 944 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 945 if (delta < timer_freq / 100) { 946#ifndef CLK_USE_I8254_CALIBRATION 947 if (bootverbose) 948 printf( 949"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 950 freq = timer_freq; 951#endif 952 timer_freq = freq; 953 } else { 954 if (bootverbose) 955 printf( 956 "%d Hz differs from default of %d Hz by more than 1%%\n", 957 freq, timer_freq); 958 tsc_freq = 0; 959 } 960 961 set_timer_freq(timer_freq, hz); 962 i8254_timecounter.tc_frequency = timer_freq; 963 tc_init(&i8254_timecounter); 964 965#ifndef CLK_USE_TSC_CALIBRATION 966 if (tsc_freq != 0) { 967 if (bootverbose) 968 printf( 969"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 970 tsc_freq = 0; 971 } 972#endif 973 if (tsc_present && tsc_freq == 0) { 974 /* 975 * Calibration of the i586 clock relative to the mc146818A 976 * clock failed. Do a less accurate calibration relative 977 * to the i8254 clock. 978 */ 979 u_int64_t old_tsc = rdtsc(); 980 981 DELAY(1000000); 982 tsc_freq = rdtsc() - old_tsc; 983#ifdef CLK_USE_TSC_CALIBRATION 984 if (bootverbose) 985 printf("TSC clock: %u Hz (Method B)\n", tsc_freq); 986#endif 987 } 988 989#if !defined(SMP) 990 /* 991 * We can not use the TSC in SMP mode, until we figure out a 992 * cheap (impossible), reliable and precise (yeah right!) way 993 * to synchronize the TSCs of all the CPUs. 994 * Curse Intel for leaving the counter out of the I/O APIC. 995 */ 996 997#ifdef DEV_APM 998 /* 999 * We can not use the TSC if we support APM. Precise timekeeping 1000 * on an APM'ed machine is at best a fools pursuit, since 1001 * any and all of the time spent in various SMM code can't 1002 * be reliably accounted for. Reading the RTC is your only 1003 * source of reliable time info. The i8254 looses too of course 1004 * but we need to have some kind of time... 1005 * We don't know at this point whether APM is going to be used 1006 * or not, nor when it might be activated. Play it safe. 1007 */ 1008 { 1009 int disabled = 0; 1010 resource_int_value("apm", 0, "disabled", &disabled); 1011 if (disabled == 0) 1012 return; 1013 } 1014#endif /* DEV_APM */ 1015 1016 if (tsc_present && tsc_freq != 0 && !tsc_is_broken) { 1017 tsc_timecounter.tc_frequency = tsc_freq; 1018 tc_init(&tsc_timecounter); 1019 } 1020 1021#endif /* !defined(SMP) */ 1022} 1023 1024#ifdef PC98 1025static void 1026rtc_serialcombit(int i) 1027{ 1028 outb(IO_RTC, ((i&0x01)<<5)|0x07); 1029 DELAY(1); 1030 outb(IO_RTC, ((i&0x01)<<5)|0x17); 1031 DELAY(1); 1032 outb(IO_RTC, ((i&0x01)<<5)|0x07); 1033 DELAY(1); 1034} 1035 1036static void 1037rtc_serialcom(int i) 1038{ 1039 rtc_serialcombit(i&0x01); 1040 rtc_serialcombit((i&0x02)>>1); 1041 rtc_serialcombit((i&0x04)>>2); 1042 rtc_serialcombit((i&0x08)>>3); 1043 outb(IO_RTC, 0x07); 1044 DELAY(1); 1045 outb(IO_RTC, 0x0f); 1046 DELAY(1); 1047 outb(IO_RTC, 0x07); 1048 DELAY(1); 1049} 1050 1051static void 1052rtc_outb(int val) 1053{ 1054 int s; 1055 int sa = 0; 1056 1057 for (s=0;s<8;s++) { 1058 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 1059 outb(IO_RTC, sa); /* set DI & CLK 0 */ 1060 DELAY(1); 1061 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 1062 DELAY(1); 1063 } 1064 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 1065} 1066 1067static int 1068rtc_inb(void) 1069{ 1070 int s; 1071 int sa = 0; 1072 1073 for (s=0;s<8;s++) { 1074 sa |= ((inb(0x33) & 0x01) << s); 1075 outb(IO_RTC, 0x17); /* CLK 1 */ 1076 DELAY(1); 1077 outb(IO_RTC, 0x07); /* CLK 0 */ 1078 DELAY(2); 1079 } 1080 return sa; 1081} 1082#endif /* PC-98 */ 1083 1084/* 1085 * Initialize the time of day register, based on the time base which is, e.g. 1086 * from a filesystem. 1087 */ 1088void 1089inittodr(time_t base) 1090{ 1091 unsigned long sec, days; 1092#ifndef PC98 1093 int yd; 1094#endif 1095 int year, month; 1096 int y, m, s; 1097 struct timespec ts; 1098#ifdef PC98 1099 int second, min, hour; 1100#endif 1101 1102 if (base) { 1103 s = splclock(); 1104 ts.tv_sec = base; 1105 ts.tv_nsec = 0; 1106 tc_setclock(&ts); 1107 splx(s); 1108 } 1109 1110#ifdef PC98 1111 rtc_serialcom(0x03); /* Time Read */ 1112 rtc_serialcom(0x01); /* Register shift command. */ 1113 DELAY(20); 1114 1115 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 1116 min = bcd2bin(rtc_inb() & 0xff); /* min */ 1117 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 1118 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 1119 1120 month = (rtc_inb() >> 4) & 0x0f; /* month */ 1121 for (m = 1; m < month; m++) 1122 days += daysinmonth[m-1]; 1123 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 1124 /* 2000 year problem */ 1125 if (year < 1995) 1126 year += 100; 1127 if (year < 1970) 1128 goto wrong_time; 1129 for (y = 1970; y < year; y++) 1130 days += DAYSPERYEAR + LEAPYEAR(y); 1131 if ((month > 2) && LEAPYEAR(year)) 1132 days ++; 1133 sec = ((( days * 24 + 1134 hour) * 60 + 1135 min) * 60 + 1136 second); 1137 /* sec now contains the number of seconds, since Jan 1 1970, 1138 in the local time zone */ 1139 1140 s = splhigh(); 1141#else /* IBM-PC */ 1142 /* Look if we have a RTC present and the time is valid */ 1143 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 1144 goto wrong_time; 1145 1146 /* wait for time update to complete */ 1147 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 1148 s = splhigh(); 1149 while (rtcin(RTC_STATUSA) & RTCSA_TUP) { 1150 splx(s); 1151 s = splhigh(); 1152 } 1153 1154 days = 0; 1155#ifdef USE_RTC_CENTURY 1156 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 1157#else 1158 year = readrtc(RTC_YEAR) + 1900; 1159 if (year < 1970) 1160 year += 100; 1161#endif 1162 if (year < 1970) { 1163 splx(s); 1164 goto wrong_time; 1165 } 1166 month = readrtc(RTC_MONTH); 1167 for (m = 1; m < month; m++) 1168 days += daysinmonth[m-1]; 1169 if ((month > 2) && LEAPYEAR(year)) 1170 days ++; 1171 days += readrtc(RTC_DAY) - 1; 1172 yd = days; 1173 for (y = 1970; y < year; y++) 1174 days += DAYSPERYEAR + LEAPYEAR(y); 1175 sec = ((( days * 24 + 1176 readrtc(RTC_HRS)) * 60 + 1177 readrtc(RTC_MIN)) * 60 + 1178 readrtc(RTC_SEC)); 1179 /* sec now contains the number of seconds, since Jan 1 1970, 1180 in the local time zone */ 1181#endif 1182 1183 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1184 1185 y = time_second - sec; 1186 if (y <= -2 || y >= 2) { 1187 /* badly off, adjust it */ 1188 ts.tv_sec = sec; 1189 ts.tv_nsec = 0; 1190 tc_setclock(&ts); 1191 } 1192 splx(s); 1193 return; 1194 1195wrong_time: 1196 printf("Invalid time in real time clock.\n"); 1197 printf("Check and reset the date immediately!\n"); 1198} 1199 1200/* 1201 * Write system time back to RTC 1202 */ 1203void 1204resettodr() 1205{ 1206 unsigned long tm; 1207 int y, m, s; 1208#ifdef PC98 1209 int wd; 1210#endif 1211 1212 if (disable_rtc_set) 1213 return; 1214 1215 s = splclock(); 1216 tm = time_second; 1217 splx(s); 1218 1219#ifdef PC98 1220 rtc_serialcom(0x01); /* Register shift command. */ 1221 1222 /* Calculate local time to put in RTC */ 1223 1224 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1225 1226 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1227 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1228 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1229 1230 /* We have now the days since 01-01-1970 in tm */ 1231 wd = (tm+4)%7; 1232 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1233 tm >= m; 1234 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1235 tm -= m; 1236 1237 /* Now we have the years in y and the day-of-the-year in tm */ 1238 for (m = 0; ; m++) { 1239 int ml; 1240 1241 ml = daysinmonth[m]; 1242 if (m == 1 && LEAPYEAR(y)) 1243 ml++; 1244 if (tm < ml) 1245 break; 1246 tm -= ml; 1247 } 1248 1249 m++; 1250 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1251 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1252 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1253 1254 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1255 rtc_serialcom(0x00); /* Register hold command. */ 1256#else 1257 /* Disable RTC updates and interrupts. */ 1258 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1259 1260 /* Calculate local time to put in RTC */ 1261 1262 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1263 1264 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1265 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1266 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1267 1268 /* We have now the days since 01-01-1970 in tm */ 1269 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1270 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1271 tm >= m; 1272 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1273 tm -= m; 1274 1275 /* Now we have the years in y and the day-of-the-year in tm */ 1276 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1277#ifdef USE_RTC_CENTURY 1278 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1279#endif 1280 for (m = 0; ; m++) { 1281 int ml; 1282 1283 ml = daysinmonth[m]; 1284 if (m == 1 && LEAPYEAR(y)) 1285 ml++; 1286 if (tm < ml) 1287 break; 1288 tm -= ml; 1289 } 1290 1291 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1292 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1293 1294 /* Reenable RTC updates and interrupts. */ 1295 writertc(RTC_STATUSB, rtc_statusb); 1296#endif /* PC98 */ 1297} 1298 1299 1300/* 1301 * Start both clocks running. 1302 */ 1303void 1304cpu_initclocks() 1305{ 1306#ifdef APIC_IO 1307 int apic_8254_trial; 1308 void *clkdesc; 1309#endif /* APIC_IO */ 1310#ifndef PC98 1311 int diag; 1312 1313 if (statclock_disable) { 1314 /* 1315 * The stat interrupt mask is different without the 1316 * statistics clock. Also, don't set the interrupt 1317 * flag which would normally cause the RTC to generate 1318 * interrupts. 1319 */ 1320 rtc_statusb = RTCSB_24HR; 1321 } else { 1322 /* Setting stathz to nonzero early helps avoid races. */ 1323 stathz = RTC_NOPROFRATE; 1324 profhz = RTC_PROFRATE; 1325 } 1326#endif 1327 1328 /* Finish initializing 8253 timer 0. */ 1329#ifdef APIC_IO 1330 1331 apic_8254_intr = isa_apic_irq(0); 1332 apic_8254_trial = 0; 1333 if (apic_8254_intr >= 0 ) { 1334 if (apic_int_type(0, 0) == 3) 1335 apic_8254_trial = 1; 1336 } else { 1337 /* look for ExtInt on pin 0 */ 1338 if (apic_int_type(0, 0) == 3) { 1339 apic_8254_intr = apic_irq(0, 0); 1340 setup_8254_mixed_mode(); 1341 } else 1342 panic("APIC_IO: Cannot route 8254 interrupt to CPU"); 1343 } 1344 1345 inthand_add("clk", apic_8254_intr, (driver_intr_t *)clkintr, NULL, 1346 INTR_TYPE_CLK | INTR_FAST, &clkdesc); 1347 INTREN(1 << apic_8254_intr); 1348 1349#else /* APIC_IO */ 1350 1351 /* 1352 * XXX Check the priority of this interrupt handler. I 1353 * couldn't find anything suitable in the BSD/OS code (grog, 1354 * 19 July 2000). 1355 */ 1356 inthand_add("clk", 0, (driver_intr_t *)clkintr, NULL, 1357 INTR_TYPE_CLK | INTR_FAST, NULL); 1358 INTREN(IRQ0); 1359 1360#endif /* APIC_IO */ 1361 1362#ifndef PC98 1363 /* Initialize RTC. */ 1364 writertc(RTC_STATUSA, rtc_statusa); 1365 writertc(RTC_STATUSB, RTCSB_24HR); 1366 1367 /* Don't bother enabling the statistics clock. */ 1368 if (statclock_disable) 1369 return; 1370 diag = rtcin(RTC_DIAG); 1371 if (diag != 0) 1372 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1373#endif /* !PC98 */ 1374 1375#ifndef PC98 1376#ifdef APIC_IO 1377 if (isa_apic_irq(8) != 8) 1378 panic("APIC RTC != 8"); 1379#endif /* APIC_IO */ 1380 1381 inthand_add("rtc", 8, (driver_intr_t *)rtcintr, NULL, 1382 INTR_TYPE_CLK | INTR_FAST, NULL); 1383 1384#ifdef APIC_IO 1385 INTREN(APIC_IRQ8); 1386#else 1387 INTREN(IRQ8); 1388#endif /* APIC_IO */ 1389 1390 writertc(RTC_STATUSB, rtc_statusb); 1391#endif /* PC98 */ 1392 1393#ifdef APIC_IO 1394 if (apic_8254_trial) { 1395 1396 printf("APIC_IO: Testing 8254 interrupt delivery\n"); 1397 while (read_intr_count(8) < 6) 1398 ; /* nothing */ 1399 if (read_intr_count(apic_8254_intr) < 3) { 1400 /* 1401 * The MP table is broken. 1402 * The 8254 was not connected to the specified pin 1403 * on the IO APIC. 1404 * Workaround: Limited variant of mixed mode. 1405 */ 1406 INTRDIS(1 << apic_8254_intr); 1407 inthand_remove(clkdesc); 1408 printf("APIC_IO: Broken MP table detected: " 1409 "8254 is not connected to " 1410 "IOAPIC #%d intpin %d\n", 1411 int_to_apicintpin[apic_8254_intr].ioapic, 1412 int_to_apicintpin[apic_8254_intr].int_pin); 1413 /* 1414 * Revoke current ISA IRQ 0 assignment and 1415 * configure a fallback interrupt routing from 1416 * the 8254 Timer via the 8259 PIC to the 1417 * an ExtInt interrupt line on IOAPIC #0 intpin 0. 1418 * We reuse the low level interrupt handler number. 1419 */ 1420 if (apic_irq(0, 0) < 0) { 1421 revoke_apic_irq(apic_8254_intr); 1422 assign_apic_irq(0, 0, apic_8254_intr); 1423 } 1424 apic_8254_intr = apic_irq(0, 0); 1425 setup_8254_mixed_mode(); 1426 inthand_add("clk", apic_8254_intr, 1427 (driver_intr_t *)clkintr, NULL, 1428 INTR_TYPE_CLK | INTR_FAST, NULL); 1429 INTREN(1 << apic_8254_intr); 1430 } 1431 1432 } 1433 if (apic_int_type(0, 0) != 3 || 1434 int_to_apicintpin[apic_8254_intr].ioapic != 0 || 1435 int_to_apicintpin[apic_8254_intr].int_pin != 0) 1436 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n", 1437 int_to_apicintpin[apic_8254_intr].ioapic, 1438 int_to_apicintpin[apic_8254_intr].int_pin); 1439 else 1440 printf("APIC_IO: " 1441 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n"); 1442#endif 1443 1444} 1445 1446#ifdef APIC_IO 1447static u_long 1448read_intr_count(int vec) 1449{ 1450 u_long *up; 1451 up = intr_countp[vec]; 1452 if (up) 1453 return *up; 1454 return 0UL; 1455} 1456 1457static void 1458setup_8254_mixed_mode() 1459{ 1460 /* 1461 * Allow 8254 timer to INTerrupt 8259: 1462 * re-initialize master 8259: 1463 * reset; prog 4 bytes, single ICU, edge triggered 1464 */ 1465 outb(IO_ICU1, 0x13); 1466#ifdef PC98 1467 outb(IO_ICU1 + 2, NRSVIDT); /* start vector (unused) */ 1468 outb(IO_ICU1 + 2, 0x00); /* ignore slave */ 1469 outb(IO_ICU1 + 2, 0x03); /* auto EOI, 8086 */ 1470 outb(IO_ICU1 + 2, 0xfe); /* unmask INT0 */ 1471#else 1472 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */ 1473 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1474 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1475 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1476#endif 1477 /* program IO APIC for type 3 INT on INT0 */ 1478 if (ext_int_setup(0, 0) < 0) 1479 panic("8254 redirect via APIC pin0 impossible!"); 1480} 1481#endif 1482 1483void 1484setstatclockrate(int newhz) 1485{ 1486#ifndef PC98 1487 if (newhz == RTC_PROFRATE) 1488 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1489 else 1490 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1491 writertc(RTC_STATUSA, rtc_statusa); 1492#endif 1493} 1494 1495static int 1496sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS) 1497{ 1498 int error; 1499 u_int freq; 1500 1501 /* 1502 * Use `i8254' instead of `timer' in external names because `timer' 1503 * is is too generic. Should use it everywhere. 1504 */ 1505 freq = timer_freq; 1506 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 1507 if (error == 0 && req->newptr != NULL) { 1508 if (timer0_state != RELEASED) 1509 return (EBUSY); /* too much trouble to handle */ 1510 set_timer_freq(freq, hz); 1511 i8254_timecounter.tc_frequency = freq; 1512 tc_update(&i8254_timecounter); 1513 } 1514 return (error); 1515} 1516 1517SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1518 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1519 1520static int 1521sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS) 1522{ 1523 int error; 1524 u_int freq; 1525 1526 if (tsc_timecounter.tc_frequency == 0) 1527 return (EOPNOTSUPP); 1528 freq = tsc_freq; 1529 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 1530 if (error == 0 && req->newptr != NULL) { 1531 tsc_freq = freq; 1532 tsc_timecounter.tc_frequency = tsc_freq; 1533 tc_update(&tsc_timecounter); 1534 } 1535 return (error); 1536} 1537 1538SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW, 1539 0, sizeof(u_int), sysctl_machdep_tsc_freq, "I", ""); 1540 1541static unsigned 1542i8254_get_timecount(struct timecounter *tc) 1543{ 1544 u_int count; 1545 u_int high, low; 1546 u_int eflags; 1547 1548 eflags = read_eflags(); 1549 mtx_lock_spin(&clock_lock); 1550 1551 /* Select timer0 and latch counter value. */ 1552 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 1553 1554 low = inb(TIMER_CNTR0); 1555 high = inb(TIMER_CNTR0); 1556 count = timer0_max_count - ((high << 8) | low); 1557 if (count < i8254_lastcount || 1558 (!i8254_ticked && (clkintr_pending || 1559 ((count < 20 || (!(eflags & PSL_I) && count < timer0_max_count / 2u)) && 1560#ifdef APIC_IO 1561#define lapic_irr1 ((volatile u_int *)&lapic)[0x210 / 4] /* XXX XXX */ 1562 /* XXX this assumes that apic_8254_intr is < 24. */ 1563 (lapic_irr1 & (1 << apic_8254_intr)))) 1564#else 1565 (inb(IO_ICU1) & 1))) 1566#endif 1567 )) { 1568 i8254_ticked = 1; 1569 i8254_offset += timer0_max_count; 1570 } 1571 i8254_lastcount = count; 1572 count += i8254_offset; 1573 mtx_unlock_spin(&clock_lock); 1574 return (count); 1575} 1576 1577static unsigned 1578tsc_get_timecount(struct timecounter *tc) 1579{ 1580 return (rdtsc()); 1581} 1582 1583/* 1584 * Attach to the ISA PnP descriptors for the timer and realtime clock. 1585 */ 1586static struct isa_pnp_id attimer_ids[] = { 1587 { 0x0001d041 /* PNP0100 */, "AT timer" }, 1588 { 0x000bd041 /* PNP0B00 */, "AT realtime clock" }, 1589 { 0 } 1590}; 1591 1592static int 1593attimer_probe(device_t dev) 1594{ 1595 int result; 1596 1597 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids)) <= 0) 1598 device_quiet(dev); 1599 return(result); 1600} 1601 1602static int 1603attimer_attach(device_t dev) 1604{ 1605 return(0); 1606} 1607 1608static device_method_t attimer_methods[] = { 1609 /* Device interface */ 1610 DEVMETHOD(device_probe, attimer_probe), 1611 DEVMETHOD(device_attach, attimer_attach), 1612 DEVMETHOD(device_detach, bus_generic_detach), 1613 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1614 DEVMETHOD(device_suspend, bus_generic_suspend), /* XXX stop statclock? */ 1615 DEVMETHOD(device_resume, bus_generic_resume), /* XXX restart statclock? */ 1616 { 0, 0 } 1617}; 1618 1619static driver_t attimer_driver = { 1620 "attimer", 1621 attimer_methods, 1622 1, /* no softc */ 1623}; 1624 1625static devclass_t attimer_devclass; 1626 1627DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0); 1628