pcrtc.c revision 61329
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $FreeBSD: head/sys/pc98/cbus/pcrtc.c 61329 2000-06-06 08:20:22Z kato $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51/* 52 * modified for PC98 by Kakefuda 53 */ 54 55#include "opt_clock.h" 56#include "apm.h" 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/time.h> 61#include <sys/timetc.h> 62#include <sys/kernel.h> 63#ifndef SMP 64#include <sys/lock.h> 65#endif 66#include <sys/sysctl.h> 67#include <sys/cons.h> 68 69#include <machine/clock.h> 70#ifdef CLK_CALIBRATION_LOOP 71#endif 72#include <machine/cputypes.h> 73#include <machine/frame.h> 74#include <machine/ipl.h> 75#include <machine/limits.h> 76#include <machine/md_var.h> 77#include <machine/psl.h> 78#ifdef APIC_IO 79#include <machine/segments.h> 80#endif 81#if defined(SMP) || defined(APIC_IO) 82#include <machine/smp.h> 83#endif /* SMP || APIC_IO */ 84#include <machine/specialreg.h> 85 86#include <i386/isa/icu.h> 87#ifdef PC98 88#include <pc98/pc98/pc98.h> 89#include <pc98/pc98/pc98_machdep.h> 90#include <i386/isa/isa_device.h> 91#else 92#include <i386/isa/isa.h> 93#include <isa/rtc.h> 94#endif 95#include <i386/isa/timerreg.h> 96 97#include <i386/isa/intr_machdep.h> 98 99#include "mca.h" 100#if NMCA > 0 101#include <i386/isa/mca_machdep.h> 102#endif 103 104#ifdef SMP 105#define disable_intr() CLOCK_DISABLE_INTR() 106#define enable_intr() CLOCK_ENABLE_INTR() 107 108#ifdef APIC_IO 109#include <i386/isa/intr_machdep.h> 110/* The interrupt triggered by the 8254 (timer) chip */ 111int apic_8254_intr; 112static u_long read_intr_count __P((int vec)); 113static void setup_8254_mixed_mode __P((void)); 114#endif 115#endif /* SMP */ 116 117/* 118 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 119 * can use a simple formula for leap years. 120 */ 121#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 122#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 123 124#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 125 126/* 127 * Time in timer cycles that it takes for microtime() to disable interrupts 128 * and latch the count. microtime() currently uses "cli; outb ..." so it 129 * normally takes less than 2 timer cycles. Add a few for cache misses. 130 * Add a few more to allow for latency in bogus calls to microtime() with 131 * interrupts already disabled. 132 */ 133#define TIMER0_LATCH_COUNT 20 134 135/* 136 * Maximum frequency that we are willing to allow for timer0. Must be 137 * low enough to guarantee that the timer interrupt handler returns 138 * before the next timer interrupt. 139 */ 140#define TIMER0_MAX_FREQ 20000 141 142int adjkerntz; /* local offset from GMT in seconds */ 143int clkintr_pending; 144int disable_rtc_set; /* disable resettodr() if != 0 */ 145volatile u_int idelayed; 146int statclock_disable; 147u_int stat_imask = SWI_LOW_MASK; 148#ifndef TIMER_FREQ 149#ifdef PC98 150#define TIMER_FREQ 2457600; 151#else /* IBM-PC */ 152#define TIMER_FREQ 1193182; 153#endif /* PC98 */ 154#endif 155u_int timer_freq = TIMER_FREQ; 156int timer0_max_count; 157u_int tsc_freq; 158int tsc_is_broken; 159int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 160 161static int beeping = 0; 162static u_int clk_imask = HWI_MASK | SWI_MASK; 163static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 164static u_int hardclock_max_count; 165static u_int32_t i8254_lastcount; 166static u_int32_t i8254_offset; 167static int i8254_ticked; 168/* 169 * XXX new_function and timer_func should not handle clockframes, but 170 * timer_func currently needs to hold hardclock to handle the 171 * timer0_state == 0 case. We should use inthand_add()/inthand_remove() 172 * to switch between clkintr() and a slightly different timerintr(). 173 */ 174static void (*new_function) __P((struct clockframe *frame)); 175static u_int new_rate; 176#ifndef PC98 177static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 178static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 179#endif 180static u_int timer0_prescaler_count; 181 182/* Values for timerX_state: */ 183#define RELEASED 0 184#define RELEASE_PENDING 1 185#define ACQUIRED 2 186#define ACQUIRE_PENDING 3 187 188static u_char timer0_state; 189#ifdef PC98 190static u_char timer1_state; 191#endif 192static u_char timer2_state; 193static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 194#ifdef PC98 195static void rtc_serialcombit __P((int)); 196static void rtc_serialcom __P((int)); 197static int rtc_inb __P((void)); 198static void rtc_outb __P((int)); 199#endif 200static u_int tsc_present; 201 202static unsigned i8254_get_timecount __P((struct timecounter *tc)); 203static unsigned tsc_get_timecount __P((struct timecounter *tc)); 204static void set_timer_freq(u_int freq, int intr_freq); 205 206static struct timecounter tsc_timecounter = { 207 tsc_get_timecount, /* get_timecount */ 208 0, /* no poll_pps */ 209 ~0u, /* counter_mask */ 210 0, /* frequency */ 211 "TSC" /* name */ 212}; 213 214SYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD, 215 &tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", ""); 216 217static struct timecounter i8254_timecounter = { 218 i8254_get_timecount, /* get_timecount */ 219 0, /* no poll_pps */ 220 ~0u, /* counter_mask */ 221 0, /* frequency */ 222 "i8254" /* name */ 223}; 224 225SYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD, 226 &i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", ""); 227 228static void 229clkintr(struct clockframe frame) 230{ 231 if (timecounter->tc_get_timecount == i8254_get_timecount) { 232 disable_intr(); 233 if (i8254_ticked) 234 i8254_ticked = 0; 235 else { 236 i8254_offset += timer0_max_count; 237 i8254_lastcount = 0; 238 } 239 clkintr_pending = 0; 240 enable_intr(); 241 } 242 timer_func(&frame); 243 switch (timer0_state) { 244 245 case RELEASED: 246 setdelayed(); 247 break; 248 249 case ACQUIRED: 250 if ((timer0_prescaler_count += timer0_max_count) 251 >= hardclock_max_count) { 252 timer0_prescaler_count -= hardclock_max_count; 253 hardclock(&frame); 254 setdelayed(); 255 } 256 break; 257 258 case ACQUIRE_PENDING: 259 disable_intr(); 260 i8254_offset = i8254_get_timecount(NULL); 261 i8254_lastcount = 0; 262 timer0_max_count = TIMER_DIV(new_rate); 263 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 264 outb(TIMER_CNTR0, timer0_max_count & 0xff); 265 outb(TIMER_CNTR0, timer0_max_count >> 8); 266 enable_intr(); 267 timer_func = new_function; 268 timer0_state = ACQUIRED; 269 setdelayed(); 270 break; 271 272 case RELEASE_PENDING: 273 if ((timer0_prescaler_count += timer0_max_count) 274 >= hardclock_max_count) { 275 disable_intr(); 276 i8254_offset = i8254_get_timecount(NULL); 277 i8254_lastcount = 0; 278 timer0_max_count = hardclock_max_count; 279 outb(TIMER_MODE, 280 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 281 outb(TIMER_CNTR0, timer0_max_count & 0xff); 282 outb(TIMER_CNTR0, timer0_max_count >> 8); 283 enable_intr(); 284 timer0_prescaler_count = 0; 285 timer_func = hardclock; 286 timer0_state = RELEASED; 287 hardclock(&frame); 288 setdelayed(); 289 } 290 break; 291 } 292#if NMCA > 0 293 /* Reset clock interrupt by asserting bit 7 of port 0x61 */ 294 if (MCA_system) 295 outb(0x61, inb(0x61) | 0x80); 296#endif 297} 298 299/* 300 * The acquire and release functions must be called at ipl >= splclock(). 301 */ 302int 303acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 304{ 305 static int old_rate; 306 307 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 308 return (-1); 309 switch (timer0_state) { 310 311 case RELEASED: 312 timer0_state = ACQUIRE_PENDING; 313 break; 314 315 case RELEASE_PENDING: 316 if (rate != old_rate) 317 return (-1); 318 /* 319 * The timer has been released recently, but is being 320 * re-acquired before the release completed. In this 321 * case, we simply reclaim it as if it had not been 322 * released at all. 323 */ 324 timer0_state = ACQUIRED; 325 break; 326 327 default: 328 return (-1); /* busy */ 329 } 330 new_function = function; 331 old_rate = new_rate = rate; 332 return (0); 333} 334 335#ifdef PC98 336int 337acquire_timer1(int mode) 338{ 339 340 if (timer1_state != RELEASED) 341 return (-1); 342 timer1_state = ACQUIRED; 343 344 /* 345 * This access to the timer registers is as atomic as possible 346 * because it is a single instruction. We could do better if we 347 * knew the rate. Use of splclock() limits glitches to 10-100us, 348 * and this is probably good enough for timer2, so we aren't as 349 * careful with it as with timer0. 350 */ 351 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 352 353 return (0); 354} 355#endif 356 357int 358acquire_timer2(int mode) 359{ 360 361 if (timer2_state != RELEASED) 362 return (-1); 363 timer2_state = ACQUIRED; 364 365 /* 366 * This access to the timer registers is as atomic as possible 367 * because it is a single instruction. We could do better if we 368 * knew the rate. Use of splclock() limits glitches to 10-100us, 369 * and this is probably good enough for timer2, so we aren't as 370 * careful with it as with timer0. 371 */ 372 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 373 374 return (0); 375} 376 377int 378release_timer0() 379{ 380 switch (timer0_state) { 381 382 case ACQUIRED: 383 timer0_state = RELEASE_PENDING; 384 break; 385 386 case ACQUIRE_PENDING: 387 /* Nothing happened yet, release quickly. */ 388 timer0_state = RELEASED; 389 break; 390 391 default: 392 return (-1); 393 } 394 return (0); 395} 396 397#ifdef PC98 398int 399release_timer1() 400{ 401 402 if (timer1_state != ACQUIRED) 403 return (-1); 404 timer1_state = RELEASED; 405 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 406 return (0); 407} 408#endif 409 410int 411release_timer2() 412{ 413 414 if (timer2_state != ACQUIRED) 415 return (-1); 416 timer2_state = RELEASED; 417 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 418 return (0); 419} 420 421#ifndef PC98 422/* 423 * This routine receives statistical clock interrupts from the RTC. 424 * As explained above, these occur at 128 interrupts per second. 425 * When profiling, we receive interrupts at a rate of 1024 Hz. 426 * 427 * This does not actually add as much overhead as it sounds, because 428 * when the statistical clock is active, the hardclock driver no longer 429 * needs to keep (inaccurate) statistics on its own. This decouples 430 * statistics gathering from scheduling interrupts. 431 * 432 * The RTC chip requires that we read status register C (RTC_INTR) 433 * to acknowledge an interrupt, before it will generate the next one. 434 * Under high interrupt load, rtcintr() can be indefinitely delayed and 435 * the clock can tick immediately after the read from RTC_INTR. In this 436 * case, the mc146818A interrupt signal will not drop for long enough 437 * to register with the 8259 PIC. If an interrupt is missed, the stat 438 * clock will halt, considerably degrading system performance. This is 439 * why we use 'while' rather than a more straightforward 'if' below. 440 * Stat clock ticks can still be lost, causing minor loss of accuracy 441 * in the statistics, but the stat clock will no longer stop. 442 */ 443static void 444rtcintr(struct clockframe frame) 445{ 446 while (rtcin(RTC_INTR) & RTCIR_PERIOD) 447 statclock(&frame); 448} 449 450#include "opt_ddb.h" 451#ifdef DDB 452#include <ddb/ddb.h> 453 454DB_SHOW_COMMAND(rtc, rtc) 455{ 456 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 457 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 458 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 459 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 460} 461#endif /* DDB */ 462#endif /* for PC98 */ 463 464static int 465getit(void) 466{ 467 u_long ef; 468 int high, low; 469 470 ef = read_eflags(); 471 disable_intr(); 472 473 /* Select timer0 and latch counter value. */ 474 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 475 476 low = inb(TIMER_CNTR0); 477 high = inb(TIMER_CNTR0); 478 479 CLOCK_UNLOCK(); 480 write_eflags(ef); 481 return ((high << 8) | low); 482} 483 484/* 485 * Wait "n" microseconds. 486 * Relies on timer 1 counting down from (timer_freq / hz) 487 * Note: timer had better have been programmed before this is first used! 488 */ 489void 490DELAY(int n) 491{ 492 int delta, prev_tick, tick, ticks_left; 493 494#ifdef DELAYDEBUG 495 int getit_calls = 1; 496 int n1; 497 static int state = 0; 498 499 if (state == 0) { 500 state = 1; 501 for (n1 = 1; n1 <= 10000000; n1 *= 10) 502 DELAY(n1); 503 state = 2; 504 } 505 if (state == 1) 506 printf("DELAY(%d)...", n); 507#endif 508 /* 509 * Guard against the timer being uninitialized if we are called 510 * early for console i/o. 511 */ 512 if (timer0_max_count == 0) 513 set_timer_freq(timer_freq, hz); 514 515 /* 516 * Read the counter first, so that the rest of the setup overhead is 517 * counted. Guess the initial overhead is 20 usec (on most systems it 518 * takes about 1.5 usec for each of the i/o's in getit(). The loop 519 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 520 * multiplications and divisions to scale the count take a while). 521 */ 522 prev_tick = getit(); 523 n -= 0; /* XXX actually guess no initial overhead */ 524 /* 525 * Calculate (n * (timer_freq / 1e6)) without using floating point 526 * and without any avoidable overflows. 527 */ 528 if (n <= 0) 529 ticks_left = 0; 530 else if (n < 256) 531 /* 532 * Use fixed point to avoid a slow division by 1000000. 533 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 534 * 2^15 is the first power of 2 that gives exact results 535 * for n between 0 and 256. 536 */ 537 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 538 else 539 /* 540 * Don't bother using fixed point, although gcc-2.7.2 541 * generates particularly poor code for the long long 542 * division, since even the slow way will complete long 543 * before the delay is up (unless we're interrupted). 544 */ 545 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 546 / 1000000; 547 548 while (ticks_left > 0) { 549 tick = getit(); 550#ifdef DELAYDEBUG 551 ++getit_calls; 552#endif 553 delta = prev_tick - tick; 554 prev_tick = tick; 555 if (delta < 0) { 556 delta += timer0_max_count; 557 /* 558 * Guard against timer0_max_count being wrong. 559 * This shouldn't happen in normal operation, 560 * but it may happen if set_timer_freq() is 561 * traced. 562 */ 563 if (delta < 0) 564 delta = 0; 565 } 566 ticks_left -= delta; 567 } 568#ifdef DELAYDEBUG 569 if (state == 1) 570 printf(" %d calls to getit() at %d usec each\n", 571 getit_calls, (n + 5) / getit_calls); 572#endif 573} 574 575static void 576sysbeepstop(void *chan) 577{ 578#ifdef PC98 /* PC98 */ 579 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 580 release_timer1(); 581#else 582 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 583 release_timer2(); 584#endif 585 beeping = 0; 586} 587 588int 589sysbeep(int pitch, int period) 590{ 591 int x = splclock(); 592 593#ifdef PC98 594 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 595 if (!beeping) { 596 /* Something else owns it. */ 597 splx(x); 598 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 599 } 600 disable_intr(); 601 outb(0x3fdb, pitch); 602 outb(0x3fdb, (pitch>>8)); 603 enable_intr(); 604 if (!beeping) { 605 /* enable counter1 output to speaker */ 606 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 607 beeping = period; 608 timeout(sysbeepstop, (void *)NULL, period); 609 } 610#else 611 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 612 if (!beeping) { 613 /* Something else owns it. */ 614 splx(x); 615 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 616 } 617 disable_intr(); 618 outb(TIMER_CNTR2, pitch); 619 outb(TIMER_CNTR2, (pitch>>8)); 620 enable_intr(); 621 if (!beeping) { 622 /* enable counter2 output to speaker */ 623 outb(IO_PPI, inb(IO_PPI) | 3); 624 beeping = period; 625 timeout(sysbeepstop, (void *)NULL, period); 626 } 627#endif 628 splx(x); 629 return (0); 630} 631 632#ifndef PC98 633/* 634 * RTC support routines 635 */ 636 637int 638rtcin(reg) 639 int reg; 640{ 641 int s; 642 u_char val; 643 644 s = splhigh(); 645 outb(IO_RTC, reg); 646 inb(0x84); 647 val = inb(IO_RTC + 1); 648 inb(0x84); 649 splx(s); 650 return (val); 651} 652 653static __inline void 654writertc(u_char reg, u_char val) 655{ 656 int s; 657 658 s = splhigh(); 659 inb(0x84); 660 outb(IO_RTC, reg); 661 inb(0x84); 662 outb(IO_RTC + 1, val); 663 inb(0x84); /* XXX work around wrong order in rtcin() */ 664 splx(s); 665} 666 667static __inline int 668readrtc(int port) 669{ 670 return(bcd2bin(rtcin(port))); 671} 672#endif 673 674#ifdef PC98 675unsigned int delaycount; 676#define FIRST_GUESS 0x2000 677static void findcpuspeed(void) 678{ 679 int i; 680 int remainder; 681 682 /* Put counter in count down mode */ 683 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 684 outb(TIMER_CNTR0, 0xff); 685 outb(TIMER_CNTR0, 0xff); 686 for (i = FIRST_GUESS; i; i--) 687 ; 688 remainder = getit(); 689 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 690} 691#endif 692 693#ifdef PC98 694static u_int 695calibrate_clocks(void) 696{ 697 int timeout; 698 u_int count, prev_count, tot_count; 699 u_short sec, start_sec; 700 701 if (bootverbose) 702 printf("Calibrating clock(s) ... "); 703 /* Check ARTIC. */ 704 if (!(PC98_SYSTEM_PARAMETER(0x458) & 0x80) && 705 !(PC98_SYSTEM_PARAMETER(0x45b) & 0x04)) 706 goto fail; 707 timeout = 100000000; 708 709 /* Read the ARTIC. */ 710 sec = inw(0x5e); 711 712 /* Wait for the ARTIC to changes. */ 713 start_sec = sec; 714 for (;;) { 715 sec = inw(0x5e); 716 if (sec != start_sec) 717 break; 718 if (--timeout == 0) 719 goto fail; 720 } 721 prev_count = getit(); 722 if (prev_count == 0 || prev_count > timer0_max_count) 723 goto fail; 724 tot_count = 0; 725 726 if (tsc_present) 727 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 728 start_sec = sec; 729 for (;;) { 730 sec = inw(0x5e); 731 count = getit(); 732 if (count == 0 || count > timer0_max_count) 733 goto fail; 734 if (count > prev_count) 735 tot_count += prev_count - (count - timer0_max_count); 736 else 737 tot_count += prev_count - count; 738 prev_count = count; 739 if ((sec == start_sec + 1200) || 740 (sec < start_sec && 741 (u_int)sec + 0x10000 == (u_int)start_sec + 1200)) 742 break; 743 if (--timeout == 0) 744 goto fail; 745 } 746 /* 747 * Read the cpu cycle counter. The timing considerations are 748 * similar to those for the i8254 clock. 749 */ 750 if (tsc_present) 751 tsc_freq = rdtsc(); 752 753 if (bootverbose) { 754 if (tsc_present) 755 printf("TSC clock: %u Hz, ", tsc_freq); 756 printf("i8254 clock: %u Hz\n", tot_count); 757 } 758 return (tot_count); 759 760fail: 761 if (bootverbose) 762 printf("failed, using default i8254 clock of %u Hz\n", 763 timer_freq); 764 return (timer_freq); 765} 766#else 767static u_int 768calibrate_clocks(void) 769{ 770 u_int64_t old_tsc; 771 u_int count, prev_count, tot_count; 772 int sec, start_sec, timeout; 773 774 if (bootverbose) 775 printf("Calibrating clock(s) ... "); 776 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 777 goto fail; 778 timeout = 100000000; 779 780 /* Read the mc146818A seconds counter. */ 781 for (;;) { 782 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 783 sec = rtcin(RTC_SEC); 784 break; 785 } 786 if (--timeout == 0) 787 goto fail; 788 } 789 790 /* Wait for the mC146818A seconds counter to change. */ 791 start_sec = sec; 792 for (;;) { 793 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 794 sec = rtcin(RTC_SEC); 795 if (sec != start_sec) 796 break; 797 } 798 if (--timeout == 0) 799 goto fail; 800 } 801 802 /* Start keeping track of the i8254 counter. */ 803 prev_count = getit(); 804 if (prev_count == 0 || prev_count > timer0_max_count) 805 goto fail; 806 tot_count = 0; 807 808 if (tsc_present) 809 old_tsc = rdtsc(); 810 else 811 old_tsc = 0; /* shut up gcc */ 812 813 /* 814 * Wait for the mc146818A seconds counter to change. Read the i8254 815 * counter for each iteration since this is convenient and only 816 * costs a few usec of inaccuracy. The timing of the final reads 817 * of the counters almost matches the timing of the initial reads, 818 * so the main cause of inaccuracy is the varying latency from 819 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 820 * rtcin(RTC_SEC) that returns a changed seconds count. The 821 * maximum inaccuracy from this cause is < 10 usec on 486's. 822 */ 823 start_sec = sec; 824 for (;;) { 825 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 826 sec = rtcin(RTC_SEC); 827 count = getit(); 828 if (count == 0 || count > timer0_max_count) 829 goto fail; 830 if (count > prev_count) 831 tot_count += prev_count - (count - timer0_max_count); 832 else 833 tot_count += prev_count - count; 834 prev_count = count; 835 if (sec != start_sec) 836 break; 837 if (--timeout == 0) 838 goto fail; 839 } 840 841 /* 842 * Read the cpu cycle counter. The timing considerations are 843 * similar to those for the i8254 clock. 844 */ 845 if (tsc_present) 846 tsc_freq = rdtsc() - old_tsc; 847 848 if (bootverbose) { 849 if (tsc_present) 850 printf("TSC clock: %u Hz, ", tsc_freq); 851 printf("i8254 clock: %u Hz\n", tot_count); 852 } 853 return (tot_count); 854 855fail: 856 if (bootverbose) 857 printf("failed, using default i8254 clock of %u Hz\n", 858 timer_freq); 859 return (timer_freq); 860} 861#endif /* !PC98 */ 862 863static void 864set_timer_freq(u_int freq, int intr_freq) 865{ 866 u_long ef; 867 int new_timer0_max_count; 868 869 ef = read_eflags(); 870 disable_intr(); 871 timer_freq = freq; 872 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 873 if (new_timer0_max_count != timer0_max_count) { 874 timer0_max_count = new_timer0_max_count; 875 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 876 outb(TIMER_CNTR0, timer0_max_count & 0xff); 877 outb(TIMER_CNTR0, timer0_max_count >> 8); 878 } 879 CLOCK_UNLOCK(); 880 write_eflags(ef); 881} 882 883/* 884 * i8254_restore is called from apm_default_resume() to reload 885 * the countdown register. 886 * this should not be necessary but there are broken laptops that 887 * do not restore the countdown register on resume. 888 * when it happnes, it messes up the hardclock interval and system clock, 889 * which leads to the infamous "calcru: negative time" problem. 890 */ 891void 892i8254_restore(void) 893{ 894 u_long ef; 895 896 ef = read_eflags(); 897 disable_intr(); 898 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 899 outb(TIMER_CNTR0, timer0_max_count & 0xff); 900 outb(TIMER_CNTR0, timer0_max_count >> 8); 901 CLOCK_UNLOCK(); 902 write_eflags(ef); 903} 904 905/* 906 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 907 * XXX initialization of other timers is unintentionally left blank. 908 */ 909void 910startrtclock() 911{ 912 u_int delta, freq; 913 914#ifdef PC98 915 findcpuspeed(); 916 if (pc98_machine_type & M_8M) 917 timer_freq = 1996800L; /* 1.9968 MHz */ 918 else 919 timer_freq = 2457600L; /* 2.4576 MHz */ 920#endif /* PC98 */ 921 922 if (cpu_feature & CPUID_TSC) 923 tsc_present = 1; 924 else 925 tsc_present = 0; 926 927#ifndef PC98 928 writertc(RTC_STATUSA, rtc_statusa); 929 writertc(RTC_STATUSB, RTCSB_24HR); 930#endif 931 932 set_timer_freq(timer_freq, hz); 933 freq = calibrate_clocks(); 934#ifdef CLK_CALIBRATION_LOOP 935 if (bootverbose) { 936 printf( 937 "Press a key on the console to abort clock calibration\n"); 938 while (cncheckc() == -1) 939 calibrate_clocks(); 940 } 941#endif 942 943 /* 944 * Use the calibrated i8254 frequency if it seems reasonable. 945 * Otherwise use the default, and don't use the calibrated i586 946 * frequency. 947 */ 948 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 949 if (delta < timer_freq / 100) { 950#ifndef CLK_USE_I8254_CALIBRATION 951 if (bootverbose) 952 printf( 953"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 954 freq = timer_freq; 955#endif 956 timer_freq = freq; 957 } else { 958 if (bootverbose) 959 printf( 960 "%d Hz differs from default of %d Hz by more than 1%%\n", 961 freq, timer_freq); 962 tsc_freq = 0; 963 } 964 965 set_timer_freq(timer_freq, hz); 966 i8254_timecounter.tc_frequency = timer_freq; 967 tc_init(&i8254_timecounter); 968 969#ifndef CLK_USE_TSC_CALIBRATION 970 if (tsc_freq != 0) { 971 if (bootverbose) 972 printf( 973"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 974 tsc_freq = 0; 975 } 976#endif 977 if (tsc_present && tsc_freq == 0) { 978 /* 979 * Calibration of the i586 clock relative to the mc146818A 980 * clock failed. Do a less accurate calibration relative 981 * to the i8254 clock. 982 */ 983 u_int64_t old_tsc = rdtsc(); 984 985 DELAY(1000000); 986 tsc_freq = rdtsc() - old_tsc; 987#ifdef CLK_USE_TSC_CALIBRATION 988 if (bootverbose) 989 printf("TSC clock: %u Hz (Method B)\n", tsc_freq); 990#endif 991 } 992 993#if !defined(SMP) 994 /* 995 * We can not use the TSC in SMP mode, until we figure out a 996 * cheap (impossible), reliable and precise (yeah right!) way 997 * to synchronize the TSCs of all the CPUs. 998 * Curse Intel for leaving the counter out of the I/O APIC. 999 */ 1000 1001#if NAPM > 0 1002 /* 1003 * We can not use the TSC if we support APM. Precise timekeeping 1004 * on an APM'ed machine is at best a fools pursuit, since 1005 * any and all of the time spent in various SMM code can't 1006 * be reliably accounted for. Reading the RTC is your only 1007 * source of reliable time info. The i8254 looses too of course 1008 * but we need to have some kind of time... 1009 * We don't know at this point whether APM is going to be used 1010 * or not, nor when it might be activated. Play it safe. 1011 */ 1012 return; 1013#endif /* NAPM > 0 */ 1014 1015 if (tsc_present && tsc_freq != 0 && !tsc_is_broken) { 1016 tsc_timecounter.tc_frequency = tsc_freq; 1017 tc_init(&tsc_timecounter); 1018 } 1019 1020#endif /* !defined(SMP) */ 1021} 1022 1023#ifdef PC98 1024static void 1025rtc_serialcombit(int i) 1026{ 1027 outb(IO_RTC, ((i&0x01)<<5)|0x07); 1028 DELAY(1); 1029 outb(IO_RTC, ((i&0x01)<<5)|0x17); 1030 DELAY(1); 1031 outb(IO_RTC, ((i&0x01)<<5)|0x07); 1032 DELAY(1); 1033} 1034 1035static void 1036rtc_serialcom(int i) 1037{ 1038 rtc_serialcombit(i&0x01); 1039 rtc_serialcombit((i&0x02)>>1); 1040 rtc_serialcombit((i&0x04)>>2); 1041 rtc_serialcombit((i&0x08)>>3); 1042 outb(IO_RTC, 0x07); 1043 DELAY(1); 1044 outb(IO_RTC, 0x0f); 1045 DELAY(1); 1046 outb(IO_RTC, 0x07); 1047 DELAY(1); 1048} 1049 1050static void 1051rtc_outb(int val) 1052{ 1053 int s; 1054 int sa = 0; 1055 1056 for (s=0;s<8;s++) { 1057 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 1058 outb(IO_RTC, sa); /* set DI & CLK 0 */ 1059 DELAY(1); 1060 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 1061 DELAY(1); 1062 } 1063 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 1064} 1065 1066static int 1067rtc_inb(void) 1068{ 1069 int s; 1070 int sa = 0; 1071 1072 for (s=0;s<8;s++) { 1073 sa |= ((inb(0x33) & 0x01) << s); 1074 outb(IO_RTC, 0x17); /* CLK 1 */ 1075 DELAY(1); 1076 outb(IO_RTC, 0x07); /* CLK 0 */ 1077 DELAY(2); 1078 } 1079 return sa; 1080} 1081#endif /* PC-98 */ 1082 1083/* 1084 * Initialize the time of day register, based on the time base which is, e.g. 1085 * from a filesystem. 1086 */ 1087void 1088inittodr(time_t base) 1089{ 1090 unsigned long sec, days; 1091#ifndef PC98 1092 int yd; 1093#endif 1094 int year, month; 1095 int y, m, s; 1096 struct timespec ts; 1097#ifdef PC98 1098 int second, min, hour; 1099#endif 1100 1101 if (base) { 1102 s = splclock(); 1103 ts.tv_sec = base; 1104 ts.tv_nsec = 0; 1105 tc_setclock(&ts); 1106 splx(s); 1107 } 1108 1109#ifdef PC98 1110 rtc_serialcom(0x03); /* Time Read */ 1111 rtc_serialcom(0x01); /* Register shift command. */ 1112 DELAY(20); 1113 1114 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 1115 min = bcd2bin(rtc_inb() & 0xff); /* min */ 1116 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 1117 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 1118 1119 month = (rtc_inb() >> 4) & 0x0f; /* month */ 1120 for (m = 1; m < month; m++) 1121 days += daysinmonth[m-1]; 1122 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 1123 /* 2000 year problem */ 1124 if (year < 1995) 1125 year += 100; 1126 if (year < 1970) 1127 goto wrong_time; 1128 for (y = 1970; y < year; y++) 1129 days += DAYSPERYEAR + LEAPYEAR(y); 1130 if ((month > 2) && LEAPYEAR(year)) 1131 days ++; 1132 sec = ((( days * 24 + 1133 hour) * 60 + 1134 min) * 60 + 1135 second); 1136 /* sec now contains the number of seconds, since Jan 1 1970, 1137 in the local time zone */ 1138#else /* IBM-PC */ 1139 /* Look if we have a RTC present and the time is valid */ 1140 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 1141 goto wrong_time; 1142 1143 /* wait for time update to complete */ 1144 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 1145 s = splhigh(); 1146 while (rtcin(RTC_STATUSA) & RTCSA_TUP) { 1147 splx(s); 1148 s = splhigh(); 1149 } 1150 1151 days = 0; 1152#ifdef USE_RTC_CENTURY 1153 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 1154#else 1155 year = readrtc(RTC_YEAR) + 1900; 1156 if (year < 1970) 1157 year += 100; 1158#endif 1159 if (year < 1970) { 1160 splx(s); 1161 goto wrong_time; 1162 } 1163 month = readrtc(RTC_MONTH); 1164 for (m = 1; m < month; m++) 1165 days += daysinmonth[m-1]; 1166 if ((month > 2) && LEAPYEAR(year)) 1167 days ++; 1168 days += readrtc(RTC_DAY) - 1; 1169 yd = days; 1170 for (y = 1970; y < year; y++) 1171 days += DAYSPERYEAR + LEAPYEAR(y); 1172 sec = ((( days * 24 + 1173 readrtc(RTC_HRS)) * 60 + 1174 readrtc(RTC_MIN)) * 60 + 1175 readrtc(RTC_SEC)); 1176 /* sec now contains the number of seconds, since Jan 1 1970, 1177 in the local time zone */ 1178#endif 1179 1180 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1181 1182 y = time_second - sec; 1183 if (y <= -2 || y >= 2) { 1184 /* badly off, adjust it */ 1185 ts.tv_sec = sec; 1186 ts.tv_nsec = 0; 1187 tc_setclock(&ts); 1188 } 1189 splx(s); 1190 return; 1191 1192wrong_time: 1193 printf("Invalid time in real time clock.\n"); 1194 printf("Check and reset the date immediately!\n"); 1195} 1196 1197/* 1198 * Write system time back to RTC 1199 */ 1200void 1201resettodr() 1202{ 1203 unsigned long tm; 1204 int y, m, s; 1205#ifdef PC98 1206 int wd; 1207#endif 1208 1209 if (disable_rtc_set) 1210 return; 1211 1212 s = splclock(); 1213 tm = time_second; 1214 splx(s); 1215 1216#ifdef PC98 1217 rtc_serialcom(0x01); /* Register shift command. */ 1218 1219 /* Calculate local time to put in RTC */ 1220 1221 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1222 1223 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1224 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1225 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1226 1227 /* We have now the days since 01-01-1970 in tm */ 1228 wd = (tm+4)%7; 1229 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1230 tm >= m; 1231 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1232 tm -= m; 1233 1234 /* Now we have the years in y and the day-of-the-year in tm */ 1235 for (m = 0; ; m++) { 1236 int ml; 1237 1238 ml = daysinmonth[m]; 1239 if (m == 1 && LEAPYEAR(y)) 1240 ml++; 1241 if (tm < ml) 1242 break; 1243 tm -= ml; 1244 } 1245 1246 m++; 1247 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1248 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1249 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1250 1251 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1252 rtc_serialcom(0x00); /* Register hold command. */ 1253#else 1254 /* Disable RTC updates and interrupts. */ 1255 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1256 1257 /* Calculate local time to put in RTC */ 1258 1259 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1260 1261 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1262 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1263 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1264 1265 /* We have now the days since 01-01-1970 in tm */ 1266 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1267 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1268 tm >= m; 1269 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1270 tm -= m; 1271 1272 /* Now we have the years in y and the day-of-the-year in tm */ 1273 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1274#ifdef USE_RTC_CENTURY 1275 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1276#endif 1277 for (m = 0; ; m++) { 1278 int ml; 1279 1280 ml = daysinmonth[m]; 1281 if (m == 1 && LEAPYEAR(y)) 1282 ml++; 1283 if (tm < ml) 1284 break; 1285 tm -= ml; 1286 } 1287 1288 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1289 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1290 1291 /* Reenable RTC updates and interrupts. */ 1292 writertc(RTC_STATUSB, rtc_statusb); 1293#endif 1294} 1295 1296 1297/* 1298 * Start both clocks running. 1299 */ 1300void 1301cpu_initclocks() 1302{ 1303#ifdef APIC_IO 1304 int apic_8254_trial; 1305 struct intrec *clkdesc; 1306#endif /* APIC_IO */ 1307#ifndef PC98 1308 int diag; 1309 1310 if (statclock_disable) { 1311 /* 1312 * The stat interrupt mask is different without the 1313 * statistics clock. Also, don't set the interrupt 1314 * flag which would normally cause the RTC to generate 1315 * interrupts. 1316 */ 1317 stat_imask = HWI_MASK | SWI_MASK; 1318 rtc_statusb = RTCSB_24HR; 1319 } else { 1320 /* Setting stathz to nonzero early helps avoid races. */ 1321 stathz = RTC_NOPROFRATE; 1322 profhz = RTC_PROFRATE; 1323 } 1324#endif 1325 1326 /* Finish initializing 8253 timer 0. */ 1327#ifdef APIC_IO 1328 1329 apic_8254_intr = isa_apic_irq(0); 1330 apic_8254_trial = 0; 1331 if (apic_8254_intr >= 0 ) { 1332 if (apic_int_type(0, 0) == 3) 1333 apic_8254_trial = 1; 1334 } else { 1335 /* look for ExtInt on pin 0 */ 1336 if (apic_int_type(0, 0) == 3) { 1337 apic_8254_intr = apic_irq(0, 0); 1338 setup_8254_mixed_mode(); 1339 } else 1340 panic("APIC_IO: Cannot route 8254 interrupt to CPU"); 1341 } 1342 1343 clkdesc = inthand_add("clk", apic_8254_intr, (inthand2_t *)clkintr, 1344 NULL, &clk_imask, INTR_EXCL); 1345 INTREN(1 << apic_8254_intr); 1346 1347#else /* APIC_IO */ 1348 1349 inthand_add("clk", 0, (inthand2_t *)clkintr, NULL, &clk_imask, 1350 INTR_EXCL); 1351 INTREN(IRQ0); 1352 1353#endif /* APIC_IO */ 1354 1355#ifndef PC98 1356 /* Initialize RTC. */ 1357 writertc(RTC_STATUSA, rtc_statusa); 1358 writertc(RTC_STATUSB, RTCSB_24HR); 1359 1360 /* Don't bother enabling the statistics clock. */ 1361 if (statclock_disable) 1362 return; 1363 diag = rtcin(RTC_DIAG); 1364 if (diag != 0) 1365 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1366 1367#ifdef APIC_IO 1368 if (isa_apic_irq(8) != 8) 1369 panic("APIC RTC != 8"); 1370#endif /* APIC_IO */ 1371 1372 inthand_add("rtc", 8, (inthand2_t *)rtcintr, NULL, &stat_imask, 1373 INTR_EXCL); 1374 1375#ifdef APIC_IO 1376 INTREN(APIC_IRQ8); 1377#else 1378 INTREN(IRQ8); 1379#endif /* APIC_IO */ 1380 1381 writertc(RTC_STATUSB, rtc_statusb); 1382#endif /* !PC98 */ 1383 1384#ifdef APIC_IO 1385 if (apic_8254_trial) { 1386 1387 printf("APIC_IO: Testing 8254 interrupt delivery\n"); 1388 while (read_intr_count(8) < 6) 1389 ; /* nothing */ 1390 if (read_intr_count(apic_8254_intr) < 3) { 1391 /* 1392 * The MP table is broken. 1393 * The 8254 was not connected to the specified pin 1394 * on the IO APIC. 1395 * Workaround: Limited variant of mixed mode. 1396 */ 1397 INTRDIS(1 << apic_8254_intr); 1398 inthand_remove(clkdesc); 1399 printf("APIC_IO: Broken MP table detected: " 1400 "8254 is not connected to " 1401 "IOAPIC #%d intpin %d\n", 1402 int_to_apicintpin[apic_8254_intr].ioapic, 1403 int_to_apicintpin[apic_8254_intr].int_pin); 1404 /* 1405 * Revoke current ISA IRQ 0 assignment and 1406 * configure a fallback interrupt routing from 1407 * the 8254 Timer via the 8259 PIC to the 1408 * an ExtInt interrupt line on IOAPIC #0 intpin 0. 1409 * We reuse the low level interrupt handler number. 1410 */ 1411 if (apic_irq(0, 0) < 0) { 1412 revoke_apic_irq(apic_8254_intr); 1413 assign_apic_irq(0, 0, apic_8254_intr); 1414 } 1415 apic_8254_intr = apic_irq(0, 0); 1416 setup_8254_mixed_mode(); 1417 inthand_add("clk", apic_8254_intr, 1418 (inthand2_t *)clkintr, 1419 NULL, &clk_imask, INTR_EXCL); 1420 INTREN(1 << apic_8254_intr); 1421 } 1422 1423 } 1424 if (apic_int_type(0, 0) != 3 || 1425 int_to_apicintpin[apic_8254_intr].ioapic != 0 || 1426 int_to_apicintpin[apic_8254_intr].int_pin != 0) 1427 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n", 1428 int_to_apicintpin[apic_8254_intr].ioapic, 1429 int_to_apicintpin[apic_8254_intr].int_pin); 1430 else 1431 printf("APIC_IO: " 1432 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n"); 1433#endif 1434 1435} 1436 1437#ifdef APIC_IO 1438static u_long 1439read_intr_count(int vec) 1440{ 1441 u_long *up; 1442 up = intr_countp[vec]; 1443 if (up) 1444 return *up; 1445 return 0UL; 1446} 1447 1448static void 1449setup_8254_mixed_mode() 1450{ 1451 /* 1452 * Allow 8254 timer to INTerrupt 8259: 1453 * re-initialize master 8259: 1454 * reset; prog 4 bytes, single ICU, edge triggered 1455 */ 1456 outb(IO_ICU1, 0x13); 1457#ifdef PC98 1458 outb(IO_ICU1 + 2, NRSVIDT); /* start vector (unused) */ 1459 outb(IO_ICU1 + 2, 0x00); /* ignore slave */ 1460 outb(IO_ICU1 + 2, 0x03); /* auto EOI, 8086 */ 1461 outb(IO_ICU1 + 2, 0xfe); /* unmask INT0 */ 1462#else 1463 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */ 1464 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1465 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1466 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1467#endif 1468 /* program IO APIC for type 3 INT on INT0 */ 1469 if (ext_int_setup(0, 0) < 0) 1470 panic("8254 redirect via APIC pin0 impossible!"); 1471} 1472#endif 1473 1474void 1475setstatclockrate(int newhz) 1476{ 1477#ifndef PC98 1478 if (newhz == RTC_PROFRATE) 1479 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1480 else 1481 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1482 writertc(RTC_STATUSA, rtc_statusa); 1483#endif 1484} 1485 1486static int 1487sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1488{ 1489 int error; 1490 u_int freq; 1491 1492 /* 1493 * Use `i8254' instead of `timer' in external names because `timer' 1494 * is is too generic. Should use it everywhere. 1495 */ 1496 freq = timer_freq; 1497 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 1498 if (error == 0 && req->newptr != NULL) { 1499 if (timer0_state != RELEASED) 1500 return (EBUSY); /* too much trouble to handle */ 1501 set_timer_freq(freq, hz); 1502 i8254_timecounter.tc_frequency = freq; 1503 tc_update(&i8254_timecounter); 1504 } 1505 return (error); 1506} 1507 1508SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1509 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1510 1511static int 1512sysctl_machdep_tsc_freq SYSCTL_HANDLER_ARGS 1513{ 1514 int error; 1515 u_int freq; 1516 1517 if (tsc_timecounter.tc_frequency == 0) 1518 return (EOPNOTSUPP); 1519 freq = tsc_freq; 1520 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 1521 if (error == 0 && req->newptr != NULL) { 1522 tsc_freq = freq; 1523 tsc_timecounter.tc_frequency = tsc_freq; 1524 tc_update(&tsc_timecounter); 1525 } 1526 return (error); 1527} 1528 1529SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW, 1530 0, sizeof(u_int), sysctl_machdep_tsc_freq, "I", ""); 1531 1532static unsigned 1533i8254_get_timecount(struct timecounter *tc) 1534{ 1535 u_int count; 1536 u_long ef; 1537 u_int high, low; 1538 1539 ef = read_eflags(); 1540 disable_intr(); 1541 1542 /* Select timer0 and latch counter value. */ 1543 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 1544 1545 low = inb(TIMER_CNTR0); 1546 high = inb(TIMER_CNTR0); 1547 count = timer0_max_count - ((high << 8) | low); 1548 if (count < i8254_lastcount || 1549 (!i8254_ticked && (clkintr_pending || 1550 ((count < 20 || (!(ef & PSL_I) && count < timer0_max_count / 2u)) && 1551#ifdef APIC_IO 1552#define lapic_irr1 ((volatile u_int *)&lapic)[0x210 / 4] /* XXX XXX */ 1553 /* XXX this assumes that apic_8254_intr is < 24. */ 1554 (lapic_irr1 & (1 << apic_8254_intr)))) 1555#else 1556 (inb(IO_ICU1) & 1))) 1557#endif 1558 )) { 1559 i8254_ticked = 1; 1560 i8254_offset += timer0_max_count; 1561 } 1562 i8254_lastcount = count; 1563 count += i8254_offset; 1564 CLOCK_UNLOCK(); 1565 write_eflags(ef); 1566 return (count); 1567} 1568 1569static unsigned 1570tsc_get_timecount(struct timecounter *tc) 1571{ 1572 return (rdtsc()); 1573} 1574