pcrtc.c revision 50869
1168404Spjd/*- 2168404Spjd * Copyright (c) 1990 The Regents of the University of California. 3168404Spjd * All rights reserved. 4168404Spjd * 5168404Spjd * This code is derived from software contributed to Berkeley by 6168404Spjd * William Jolitz and Don Ahn. 7168404Spjd * 8168404Spjd * Redistribution and use in source and binary forms, with or without 9168404Spjd * modification, are permitted provided that the following conditions 10168404Spjd * are met: 11168404Spjd * 1. Redistributions of source code must retain the above copyright 12168404Spjd * notice, this list of conditions and the following disclaimer. 13168404Spjd * 2. Redistributions in binary form must reproduce the above copyright 14168404Spjd * notice, this list of conditions and the following disclaimer in the 15168404Spjd * documentation and/or other materials provided with the distribution. 16168404Spjd * 3. All advertising materials mentioning features or use of this software 17168404Spjd * must display the following acknowledgement: 18168404Spjd * This product includes software developed by the University of 19168404Spjd * California, Berkeley and its contributors. 20168404Spjd * 4. Neither the name of the University nor the names of its contributors 21168404Spjd * may be used to endorse or promote products derived from this software 22219089Spjd * without specific prior written permission. 23339140Smav * 24251478Sdelphij * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25286575Smav * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26168404Spjd * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27168404Spjd * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28168404Spjd * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29168404Spjd * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30168404Spjd * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31168404Spjd * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32168404Spjd * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33168404Spjd * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34168404Spjd * SUCH DAMAGE. 35168404Spjd * 36168404Spjd * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37168404Spjd * $FreeBSD: head/sys/pc98/cbus/pcrtc.c 50869 1999-09-04 01:39:52Z kato $ 38219089Spjd */ 39307265Smav 40168404Spjd/* 41168404Spjd * Routines to handle clock hardware. 42168404Spjd */ 43168404Spjd 44168404Spjd/* 45168404Spjd * inittodr, settodr and support routines written 46168404Spjd * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47168404Spjd * 48168404Spjd * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49168404Spjd */ 50168404Spjd 51168404Spjd/* 52168404Spjd * modified for PC98 by Kakefuda 53168404Spjd */ 54168404Spjd 55168404Spjd#include "opt_clock.h" 56168404Spjd#include "apm.h" 57168404Spjd 58168404Spjd#include <sys/param.h> 59219089Spjd#include <sys/systm.h> 60168404Spjd#include <sys/time.h> 61168404Spjd#include <sys/kernel.h> 62168404Spjd#ifndef SMP 63168404Spjd#include <sys/lock.h> 64168404Spjd#endif 65219089Spjd#include <sys/sysctl.h> 66219089Spjd#include <sys/cons.h> 67219089Spjd 68219089Spjd#include <machine/clock.h> 69219089Spjd#ifdef CLK_CALIBRATION_LOOP 70219089Spjd#endif 71270383Sdelphij#include <machine/cputypes.h> 72270383Sdelphij#include <machine/frame.h> 73270383Sdelphij#include <machine/ipl.h> 74270383Sdelphij#include <machine/limits.h> 75168404Spjd#include <machine/md_var.h> 76168404Spjd#include <machine/psl.h> 77270383Sdelphij#ifdef APIC_IO 78168404Spjd#include <machine/segments.h> 79168404Spjd#endif 80219089Spjd#if defined(SMP) || defined(APIC_IO) 81168404Spjd#include <machine/smp.h> 82168404Spjd#endif /* SMP || APIC_IO */ 83168404Spjd#include <machine/specialreg.h> 84168404Spjd 85168404Spjd#include <i386/isa/icu.h> 86339109Smav#ifdef PC98 87339109Smav#include <pc98/pc98/pc98.h> 88339109Smav#include <pc98/pc98/pc98_machdep.h> 89339109Smav#include <i386/isa/isa_device.h> 90339109Smav#else 91339109Smav#include <i386/isa/isa.h> 92339109Smav#include <isa/rtc.h> 93168404Spjd#endif 94168404Spjd#include <i386/isa/timerreg.h> 95168404Spjd 96168404Spjd#include <i386/isa/intr_machdep.h> 97168404Spjd 98168404Spjd#include "mca.h" 99168404Spjd#if NMCA > 0 100168404Spjd#include <i386/isa/mca_machdep.h> 101168404Spjd#endif 102168404Spjd 103168404Spjd#ifdef SMP 104168404Spjd#define disable_intr() CLOCK_DISABLE_INTR() 105168404Spjd#define enable_intr() CLOCK_ENABLE_INTR() 106168404Spjd 107168404Spjd#ifdef APIC_IO 108168404Spjd#include <i386/isa/intr_machdep.h> 109168404Spjd/* The interrupt triggered by the 8254 (timer) chip */ 110168404Spjdint apic_8254_intr; 111168404Spjdstatic u_long read_intr_count __P((int vec)); 112168404Spjdstatic void setup_8254_mixed_mode __P((void)); 113168404Spjd#endif 114168404Spjd#endif /* SMP */ 115168404Spjd 116168404Spjd/* 117168404Spjd * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 118168404Spjd * can use a simple formula for leap years. 119168404Spjd */ 120168404Spjd#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 121168404Spjd#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 122168404Spjd 123168404Spjd#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 124168404Spjd 125168404Spjd/* 126168404Spjd * Time in timer cycles that it takes for microtime() to disable interrupts 127168404Spjd * and latch the count. microtime() currently uses "cli; outb ..." so it 128168404Spjd * normally takes less than 2 timer cycles. Add a few for cache misses. 129258632Savg * Add a few more to allow for latency in bogus calls to microtime() with 130258632Savg * interrupts already disabled. 131258632Savg */ 132304137Savg#define TIMER0_LATCH_COUNT 20 133304137Savg 134304137Savg/* 135168404Spjd * Maximum frequency that we are willing to allow for timer0. Must be 136168404Spjd * low enough to guarantee that the timer interrupt handler returns 137168404Spjd * before the next timer interrupt. 138168404Spjd */ 139168404Spjd#define TIMER0_MAX_FREQ 20000 140168404Spjd 141168404Spjdint adjkerntz; /* local offset from GMT in seconds */ 142168404Spjdint clkintr_pending; 143168404Spjdint disable_rtc_set; /* disable resettodr() if != 0 */ 144168404Spjdvolatile u_int idelayed; 145168404Spjdint statclock_disable; 146168404Spjdu_int stat_imask = SWI_CLOCK_MASK; 147168404Spjd#ifndef TIMER_FREQ 148168404Spjd#ifdef PC98 149168404Spjd#define TIMER_FREQ 2457600; 150168404Spjd#else /* IBM-PC */ 151168404Spjd#define TIMER_FREQ 1193182; 152168404Spjd#endif /* PC98 */ 153168404Spjd#endif 154219089Spjdu_int timer_freq = TIMER_FREQ; 155243524Smmint timer0_max_count; 156168404Spjdu_int tsc_freq; 157168404Spjdint tsc_is_broken; 158168404Spjdint wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 159168404Spjd 160168404Spjdstatic int beeping = 0; 161168404Spjdstatic u_int clk_imask = HWI_MASK | SWI_MASK; 162168404Spjdstatic const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 163168404Spjdstatic u_int hardclock_max_count; 164168404Spjdstatic u_int32_t i8254_lastcount; 165168404Spjdstatic u_int32_t i8254_offset; 166168404Spjdstatic int i8254_ticked; 167168404Spjd/* 168168404Spjd * XXX new_function and timer_func should not handle clockframes, but 169168404Spjd * timer_func currently needs to hold hardclock to handle the 170219089Spjd * timer0_state == 0 case. We should use register_intr()/unregister_intr() 171168404Spjd * to switch between clkintr() and a slightly different timerintr(). 172168404Spjd */ 173219089Spjdstatic void (*new_function) __P((struct clockframe *frame)); 174168404Spjdstatic u_int new_rate; 175219089Spjd#ifndef PC98 176168404Spjdstatic u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 177168404Spjdstatic u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 178168404Spjd#endif 179219089Spjdstatic u_int timer0_prescaler_count; 180168404Spjd 181168404Spjd/* Values for timerX_state: */ 182219089Spjd#define RELEASED 0 183219089Spjd#define RELEASE_PENDING 1 184168404Spjd#define ACQUIRED 2 185168404Spjd#define ACQUIRE_PENDING 3 186168404Spjd 187168404Spjdstatic u_char timer0_state; 188168404Spjd#ifdef PC98 189168404Spjdstatic u_char timer1_state; 190168404Spjd#endif 191168404Spjdstatic u_char timer2_state; 192168404Spjdstatic void (*timer_func) __P((struct clockframe *frame)) = hardclock; 193168404Spjd#ifdef PC98 194168404Spjdstatic void rtc_serialcombit __P((int)); 195168404Spjdstatic void rtc_serialcom __P((int)); 196168404Spjdstatic int rtc_inb __P((void)); 197168404Spjdstatic void rtc_outb __P((int)); 198168404Spjd#endif 199168404Spjdstatic u_int tsc_present; 200168404Spjd 201168404Spjdstatic unsigned i8254_get_timecount __P((struct timecounter *tc)); 202168404Spjdstatic unsigned tsc_get_timecount __P((struct timecounter *tc)); 203168404Spjdstatic void set_timer_freq(u_int freq, int intr_freq); 204168404Spjd 205168404Spjdstatic struct timecounter tsc_timecounter = { 206168404Spjd tsc_get_timecount, /* get_timecount */ 207168404Spjd 0, /* no poll_pps */ 208168404Spjd ~0u, /* counter_mask */ 209168404Spjd 0, /* frequency */ 210168404Spjd "TSC" /* name */ 211168404Spjd}; 212168404Spjd 213168404SpjdSYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD, 214168404Spjd &tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", ""); 215168404Spjd 216168404Spjdstatic struct timecounter i8254_timecounter = { 217168404Spjd i8254_get_timecount, /* get_timecount */ 218168404Spjd 0, /* no poll_pps */ 219168404Spjd ~0u, /* counter_mask */ 220168404Spjd 0, /* frequency */ 221168404Spjd "i8254" /* name */ 222168404Spjd}; 223168404Spjd 224168404SpjdSYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD, 225168404Spjd &i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", ""); 226168404Spjd 227168404Spjdstatic void 228168404Spjdclkintr(struct clockframe frame) 229168404Spjd{ 230168404Spjd if (timecounter->tc_get_timecount == i8254_get_timecount) { 231168404Spjd disable_intr(); 232168404Spjd if (i8254_ticked) 233168404Spjd i8254_ticked = 0; 234168404Spjd else { 235168404Spjd i8254_offset += timer0_max_count; 236168404Spjd i8254_lastcount = 0; 237269229Sdelphij } 238168404Spjd clkintr_pending = 0; 239339109Smav enable_intr(); 240307265Smav } 241307265Smav timer_func(&frame); 242339109Smav switch (timer0_state) { 243339109Smav 244339109Smav case RELEASED: 245168404Spjd setdelayed(); 246168404Spjd break; 247286575Smav 248286575Smav case ACQUIRED: 249168404Spjd if ((timer0_prescaler_count += timer0_max_count) 250289309Smav >= hardclock_max_count) { 251289309Smav timer0_prescaler_count -= hardclock_max_count; 252289309Smav hardclock(&frame); 253289309Smav setdelayed(); 254289309Smav } 255289309Smav break; 256289309Smav 257289309Smav case ACQUIRE_PENDING: 258289309Smav disable_intr(); 259289309Smav i8254_offset = i8254_get_timecount(NULL); 260168404Spjd i8254_lastcount = 0; 261168404Spjd timer0_max_count = TIMER_DIV(new_rate); 262289309Smav outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 263289309Smav outb(TIMER_CNTR0, timer0_max_count & 0xff); 264289309Smav outb(TIMER_CNTR0, timer0_max_count >> 8); 265289309Smav enable_intr(); 266289309Smav timer_func = new_function; 267289309Smav timer0_state = ACQUIRED; 268289309Smav setdelayed(); 269168404Spjd break; 270168404Spjd 271168404Spjd case RELEASE_PENDING: 272168404Spjd if ((timer0_prescaler_count += timer0_max_count) 273168404Spjd >= hardclock_max_count) { 274168404Spjd disable_intr(); 275168404Spjd i8254_offset = i8254_get_timecount(NULL); 276168404Spjd i8254_lastcount = 0; 277168404Spjd timer0_max_count = hardclock_max_count; 278168404Spjd outb(TIMER_MODE, 279168404Spjd TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 280168404Spjd outb(TIMER_CNTR0, timer0_max_count & 0xff); 281286705Smav outb(TIMER_CNTR0, timer0_max_count >> 8); 282168404Spjd enable_intr(); 283168404Spjd timer0_prescaler_count = 0; 284185029Spjd timer_func = hardclock; 285219089Spjd timer0_state = RELEASED; 286219089Spjd hardclock(&frame); 287168404Spjd setdelayed(); 288219089Spjd } 289219089Spjd break; 290168404Spjd } 291168404Spjd#if NMCA > 0 292168404Spjd /* Reset clock interrupt by asserting bit 7 of port 0x61 */ 293286705Smav if (MCA_system) 294286705Smav outb(0x61, inb(0x61) | 0x80); 295168404Spjd#endif 296168404Spjd} 297286705Smav 298286705Smav/* 299168404Spjd * The acquire and release functions must be called at ipl >= splclock(). 300168404Spjd */ 301286541Smavint 302286541Smavacquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 303168404Spjd{ 304168404Spjd static int old_rate; 305168404Spjd 306339140Smav if (rate <= 0 || rate > TIMER0_MAX_FREQ) 307168404Spjd return (-1); 308286541Smav switch (timer0_state) { 309286541Smav 310168404Spjd case RELEASED: 311168404Spjd timer0_state = ACQUIRE_PENDING; 312219089Spjd break; 313168404Spjd 314168404Spjd case RELEASE_PENDING: 315209962Smm if (rate != old_rate) 316168404Spjd return (-1); 317219089Spjd /* 318268075Sdelphij * The timer has been released recently, but is being 319268075Sdelphij * re-acquired before the release completed. In this 320268075Sdelphij * case, we simply reclaim it as if it had not been 321168404Spjd * released at all. 322307265Smav */ 323168404Spjd timer0_state = ACQUIRED; 324168404Spjd break; 325168404Spjd 326284593Savg default: 327219089Spjd return (-1); /* busy */ 328168404Spjd } 329332525Smav new_function = function; 330332525Smav old_rate = new_rate = rate; 331185029Spjd return (0); 332168404Spjd} 333168404Spjd 334168404Spjd#ifdef PC98 335168404Spjdint 336219089Spjdacquire_timer1(int mode) 337219089Spjd{ 338219089Spjd 339219089Spjd if (timer1_state != RELEASED) 340219089Spjd return (-1); 341219089Spjd timer1_state = ACQUIRED; 342168404Spjd 343168404Spjd /* 344168404Spjd * This access to the timer registers is as atomic as possible 345219089Spjd * because it is a single instruction. We could do better if we 346168404Spjd * knew the rate. Use of splclock() limits glitches to 10-100us, 347219089Spjd * and this is probably good enough for timer2, so we aren't as 348248571Smm * careful with it as with timer0. 349185029Spjd */ 350219089Spjd outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 351219089Spjd 352248571Smm return (0); 353219089Spjd} 354185029Spjd#endif 355219089Spjd 356219089Spjdint 357248571Smmacquire_timer2(int mode) 358219089Spjd{ 359219089Spjd 360325931Savg if (timer2_state != RELEASED) 361325931Savg return (-1); 362325931Savg timer2_state = ACQUIRED; 363325931Savg 364325931Savg /* 365325931Savg * This access to the timer registers is as atomic as possible 366168404Spjd * because it is a single instruction. We could do better if we 367168404Spjd * knew the rate. Use of splclock() limits glitches to 10-100us, 368168404Spjd * and this is probably good enough for timer2, so we aren't as 369168404Spjd * careful with it as with timer0. 370168404Spjd */ 371168404Spjd outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 372168404Spjd 373168404Spjd return (0); 374168404Spjd} 375168404Spjd 376168404Spjdint 377168404Spjdrelease_timer0() 378168404Spjd{ 379168404Spjd switch (timer0_state) { 380168404Spjd 381168404Spjd case ACQUIRED: 382168404Spjd timer0_state = RELEASE_PENDING; 383168404Spjd break; 384168404Spjd 385168404Spjd case ACQUIRE_PENDING: 386168404Spjd /* Nothing happened yet, release quickly. */ 387168404Spjd timer0_state = RELEASED; 388168404Spjd break; 389168404Spjd 390168404Spjd default: 391168404Spjd return (-1); 392260150Sdelphij } 393168404Spjd return (0); 394168404Spjd} 395219089Spjd 396168404Spjd#ifdef PC98 397168404Spjdint 398168404Spjdrelease_timer1() 399168404Spjd{ 400168404Spjd 401168404Spjd if (timer1_state != ACQUIRED) 402168404Spjd return (-1); 403168404Spjd timer1_state = RELEASED; 404168404Spjd outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 405168404Spjd return (0); 406168404Spjd} 407168404Spjd#endif 408168404Spjd 409168404Spjdint 410168404Spjdrelease_timer2() 411168404Spjd{ 412168404Spjd 413168404Spjd if (timer2_state != ACQUIRED) 414 return (-1); 415 timer2_state = RELEASED; 416 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 417 return (0); 418} 419 420#ifndef PC98 421/* 422 * This routine receives statistical clock interrupts from the RTC. 423 * As explained above, these occur at 128 interrupts per second. 424 * When profiling, we receive interrupts at a rate of 1024 Hz. 425 * 426 * This does not actually add as much overhead as it sounds, because 427 * when the statistical clock is active, the hardclock driver no longer 428 * needs to keep (inaccurate) statistics on its own. This decouples 429 * statistics gathering from scheduling interrupts. 430 * 431 * The RTC chip requires that we read status register C (RTC_INTR) 432 * to acknowledge an interrupt, before it will generate the next one. 433 * Under high interrupt load, rtcintr() can be indefinitely delayed and 434 * the clock can tick immediately after the read from RTC_INTR. In this 435 * case, the mc146818A interrupt signal will not drop for long enough 436 * to register with the 8259 PIC. If an interrupt is missed, the stat 437 * clock will halt, considerably degrading system performance. This is 438 * why we use 'while' rather than a more straightforward 'if' below. 439 * Stat clock ticks can still be lost, causing minor loss of accuracy 440 * in the statistics, but the stat clock will no longer stop. 441 */ 442static void 443rtcintr(struct clockframe frame) 444{ 445 while (rtcin(RTC_INTR) & RTCIR_PERIOD) 446 statclock(&frame); 447} 448 449#include "opt_ddb.h" 450#ifdef DDB 451#include <ddb/ddb.h> 452 453DB_SHOW_COMMAND(rtc, rtc) 454{ 455 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 456 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 457 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 458 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 459} 460#endif /* DDB */ 461#endif /* for PC98 */ 462 463static int 464getit(void) 465{ 466 u_long ef; 467 int high, low; 468 469 ef = read_eflags(); 470 disable_intr(); 471 472 /* Select timer0 and latch counter value. */ 473 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 474 475 low = inb(TIMER_CNTR0); 476 high = inb(TIMER_CNTR0); 477 478 CLOCK_UNLOCK(); 479 write_eflags(ef); 480 return ((high << 8) | low); 481} 482 483/* 484 * Wait "n" microseconds. 485 * Relies on timer 1 counting down from (timer_freq / hz) 486 * Note: timer had better have been programmed before this is first used! 487 */ 488void 489DELAY(int n) 490{ 491 int delta, prev_tick, tick, ticks_left; 492 493#ifdef DELAYDEBUG 494 int getit_calls = 1; 495 int n1; 496 static int state = 0; 497 498 if (state == 0) { 499 state = 1; 500 for (n1 = 1; n1 <= 10000000; n1 *= 10) 501 DELAY(n1); 502 state = 2; 503 } 504 if (state == 1) 505 printf("DELAY(%d)...", n); 506#endif 507 /* 508 * Guard against the timer being uninitialized if we are called 509 * early for console i/o. 510 */ 511 if (timer0_max_count == 0) 512 set_timer_freq(timer_freq, hz); 513 514 /* 515 * Read the counter first, so that the rest of the setup overhead is 516 * counted. Guess the initial overhead is 20 usec (on most systems it 517 * takes about 1.5 usec for each of the i/o's in getit(). The loop 518 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 519 * multiplications and divisions to scale the count take a while). 520 */ 521 prev_tick = getit(); 522 n -= 0; /* XXX actually guess no initial overhead */ 523 /* 524 * Calculate (n * (timer_freq / 1e6)) without using floating point 525 * and without any avoidable overflows. 526 */ 527 if (n <= 0) 528 ticks_left = 0; 529 else if (n < 256) 530 /* 531 * Use fixed point to avoid a slow division by 1000000. 532 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 533 * 2^15 is the first power of 2 that gives exact results 534 * for n between 0 and 256. 535 */ 536 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 537 else 538 /* 539 * Don't bother using fixed point, although gcc-2.7.2 540 * generates particularly poor code for the long long 541 * division, since even the slow way will complete long 542 * before the delay is up (unless we're interrupted). 543 */ 544 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 545 / 1000000; 546 547 while (ticks_left > 0) { 548 tick = getit(); 549#ifdef DELAYDEBUG 550 ++getit_calls; 551#endif 552 delta = prev_tick - tick; 553 prev_tick = tick; 554 if (delta < 0) { 555 delta += timer0_max_count; 556 /* 557 * Guard against timer0_max_count being wrong. 558 * This shouldn't happen in normal operation, 559 * but it may happen if set_timer_freq() is 560 * traced. 561 */ 562 if (delta < 0) 563 delta = 0; 564 } 565 ticks_left -= delta; 566 } 567#ifdef DELAYDEBUG 568 if (state == 1) 569 printf(" %d calls to getit() at %d usec each\n", 570 getit_calls, (n + 5) / getit_calls); 571#endif 572} 573 574static void 575sysbeepstop(void *chan) 576{ 577#ifdef PC98 /* PC98 */ 578 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 579 release_timer1(); 580#else 581 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 582 release_timer2(); 583#endif 584 beeping = 0; 585} 586 587int 588sysbeep(int pitch, int period) 589{ 590 int x = splclock(); 591 592#ifdef PC98 593 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 594 if (!beeping) { 595 /* Something else owns it. */ 596 splx(x); 597 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 598 } 599 disable_intr(); 600 outb(0x3fdb, pitch); 601 outb(0x3fdb, (pitch>>8)); 602 enable_intr(); 603 if (!beeping) { 604 /* enable counter1 output to speaker */ 605 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 606 beeping = period; 607 timeout(sysbeepstop, (void *)NULL, period); 608 } 609#else 610 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 611 if (!beeping) { 612 /* Something else owns it. */ 613 splx(x); 614 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 615 } 616 disable_intr(); 617 outb(TIMER_CNTR2, pitch); 618 outb(TIMER_CNTR2, (pitch>>8)); 619 enable_intr(); 620 if (!beeping) { 621 /* enable counter2 output to speaker */ 622 outb(IO_PPI, inb(IO_PPI) | 3); 623 beeping = period; 624 timeout(sysbeepstop, (void *)NULL, period); 625 } 626#endif 627 splx(x); 628 return (0); 629} 630 631#ifndef PC98 632/* 633 * RTC support routines 634 */ 635 636int 637rtcin(reg) 638 int reg; 639{ 640 u_char val; 641 642 outb(IO_RTC, reg); 643 inb(0x84); 644 val = inb(IO_RTC + 1); 645 inb(0x84); 646 return (val); 647} 648 649static __inline void 650writertc(u_char reg, u_char val) 651{ 652 inb(0x84); 653 outb(IO_RTC, reg); 654 inb(0x84); 655 outb(IO_RTC + 1, val); 656 inb(0x84); /* XXX work around wrong order in rtcin() */ 657} 658 659static __inline int 660readrtc(int port) 661{ 662 return(bcd2bin(rtcin(port))); 663} 664#endif 665 666#ifdef PC98 667unsigned int delaycount; 668#define FIRST_GUESS 0x2000 669static void findcpuspeed(void) 670{ 671 int i; 672 int remainder; 673 674 /* Put counter in count down mode */ 675 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 676 outb(TIMER_CNTR0, 0xff); 677 outb(TIMER_CNTR0, 0xff); 678 for (i = FIRST_GUESS; i; i--) 679 ; 680 remainder = getit(); 681 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 682} 683#endif 684 685#ifdef PC98 686static u_int 687calibrate_clocks(void) 688{ 689 int timeout; 690 u_int count, prev_count, tot_count; 691 u_short sec, start_sec; 692 693 if (bootverbose) 694 printf("Calibrating clock(s) ... "); 695 /* Check ARTIC. */ 696 if (!(PC98_SYSTEM_PARAMETER(0x458) & 0x80) && 697 !(PC98_SYSTEM_PARAMETER(0x45b) & 0x04)) 698 goto fail; 699 timeout = 100000000; 700 701 /* Read the ARTIC. */ 702 sec = inw(0x5e); 703 704 /* Wait for the ARTIC to changes. */ 705 start_sec = sec; 706 for (;;) { 707 sec = inw(0x5e); 708 if (sec != start_sec) 709 break; 710 if (--timeout == 0) 711 goto fail; 712 } 713 prev_count = getit(); 714 if (prev_count == 0 || prev_count > timer0_max_count) 715 goto fail; 716 tot_count = 0; 717 718 if (tsc_present) 719 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 720 start_sec = sec; 721 for (;;) { 722 sec = inw(0x5e); 723 count = getit(); 724 if (count == 0 || count > timer0_max_count) 725 goto fail; 726 if (count > prev_count) 727 tot_count += prev_count - (count - timer0_max_count); 728 else 729 tot_count += prev_count - count; 730 prev_count = count; 731 if ((sec == start_sec + 1200) || 732 (sec < start_sec && 733 (u_int)sec + 0x10000 == (u_int)start_sec + 1200)) 734 break; 735 if (--timeout == 0) 736 goto fail; 737 } 738 /* 739 * Read the cpu cycle counter. The timing considerations are 740 * similar to those for the i8254 clock. 741 */ 742 if (tsc_present) 743 tsc_freq = rdtsc(); 744 745 if (bootverbose) { 746 if (tsc_present) 747 printf("TSC clock: %u Hz, ", tsc_freq); 748 printf("i8254 clock: %u Hz\n", tot_count); 749 } 750 return (tot_count); 751 752fail: 753 if (bootverbose) 754 printf("failed, using default i8254 clock of %u Hz\n", 755 timer_freq); 756 return (timer_freq); 757} 758#else 759static u_int 760calibrate_clocks(void) 761{ 762 u_int64_t old_tsc; 763 u_int count, prev_count, tot_count; 764 int sec, start_sec, timeout; 765 766 if (bootverbose) 767 printf("Calibrating clock(s) ... "); 768 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 769 goto fail; 770 timeout = 100000000; 771 772 /* Read the mc146818A seconds counter. */ 773 for (;;) { 774 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 775 sec = rtcin(RTC_SEC); 776 break; 777 } 778 if (--timeout == 0) 779 goto fail; 780 } 781 782 /* Wait for the mC146818A seconds counter to change. */ 783 start_sec = sec; 784 for (;;) { 785 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 786 sec = rtcin(RTC_SEC); 787 if (sec != start_sec) 788 break; 789 } 790 if (--timeout == 0) 791 goto fail; 792 } 793 794 /* Start keeping track of the i8254 counter. */ 795 prev_count = getit(); 796 if (prev_count == 0 || prev_count > timer0_max_count) 797 goto fail; 798 tot_count = 0; 799 800 if (tsc_present) 801 old_tsc = rdtsc(); 802 else 803 old_tsc = 0; /* shut up gcc */ 804 805 /* 806 * Wait for the mc146818A seconds counter to change. Read the i8254 807 * counter for each iteration since this is convenient and only 808 * costs a few usec of inaccuracy. The timing of the final reads 809 * of the counters almost matches the timing of the initial reads, 810 * so the main cause of inaccuracy is the varying latency from 811 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 812 * rtcin(RTC_SEC) that returns a changed seconds count. The 813 * maximum inaccuracy from this cause is < 10 usec on 486's. 814 */ 815 start_sec = sec; 816 for (;;) { 817 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 818 sec = rtcin(RTC_SEC); 819 count = getit(); 820 if (count == 0 || count > timer0_max_count) 821 goto fail; 822 if (count > prev_count) 823 tot_count += prev_count - (count - timer0_max_count); 824 else 825 tot_count += prev_count - count; 826 prev_count = count; 827 if (sec != start_sec) 828 break; 829 if (--timeout == 0) 830 goto fail; 831 } 832 833 /* 834 * Read the cpu cycle counter. The timing considerations are 835 * similar to those for the i8254 clock. 836 */ 837 if (tsc_present) 838 tsc_freq = rdtsc() - old_tsc; 839 840 if (bootverbose) { 841 if (tsc_present) 842 printf("TSC clock: %u Hz, ", tsc_freq); 843 printf("i8254 clock: %u Hz\n", tot_count); 844 } 845 return (tot_count); 846 847fail: 848 if (bootverbose) 849 printf("failed, using default i8254 clock of %u Hz\n", 850 timer_freq); 851 return (timer_freq); 852} 853#endif /* !PC98 */ 854 855static void 856set_timer_freq(u_int freq, int intr_freq) 857{ 858 u_long ef; 859 int new_timer0_max_count; 860 861 ef = read_eflags(); 862 disable_intr(); 863 timer_freq = freq; 864 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 865 if (new_timer0_max_count != timer0_max_count) { 866 timer0_max_count = new_timer0_max_count; 867 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 868 outb(TIMER_CNTR0, timer0_max_count & 0xff); 869 outb(TIMER_CNTR0, timer0_max_count >> 8); 870 } 871 CLOCK_UNLOCK(); 872 write_eflags(ef); 873} 874 875/* 876 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 877 * XXX initialization of other timers is unintentionally left blank. 878 */ 879void 880startrtclock() 881{ 882 u_int delta, freq; 883 884#ifdef PC98 885 findcpuspeed(); 886 if (pc98_machine_type & M_8M) 887 timer_freq = 1996800L; /* 1.9968 MHz */ 888 else 889 timer_freq = 2457600L; /* 2.4576 MHz */ 890#endif /* PC98 */ 891 892 if (cpu_feature & CPUID_TSC) 893 tsc_present = 1; 894 else 895 tsc_present = 0; 896 897#ifndef PC98 898 writertc(RTC_STATUSA, rtc_statusa); 899 writertc(RTC_STATUSB, RTCSB_24HR); 900#endif 901 902 set_timer_freq(timer_freq, hz); 903 freq = calibrate_clocks(); 904#ifdef CLK_CALIBRATION_LOOP 905 if (bootverbose) { 906 printf( 907 "Press a key on the console to abort clock calibration\n"); 908 while (cncheckc() == -1) 909 calibrate_clocks(); 910 } 911#endif 912 913 /* 914 * Use the calibrated i8254 frequency if it seems reasonable. 915 * Otherwise use the default, and don't use the calibrated i586 916 * frequency. 917 */ 918 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 919 if (delta < timer_freq / 100) { 920#ifndef CLK_USE_I8254_CALIBRATION 921 if (bootverbose) 922 printf( 923"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 924 freq = timer_freq; 925#endif 926 timer_freq = freq; 927 } else { 928 if (bootverbose) 929 printf( 930 "%d Hz differs from default of %d Hz by more than 1%%\n", 931 freq, timer_freq); 932 tsc_freq = 0; 933 } 934 935 set_timer_freq(timer_freq, hz); 936 i8254_timecounter.tc_frequency = timer_freq; 937 init_timecounter(&i8254_timecounter); 938 939#ifndef CLK_USE_TSC_CALIBRATION 940 if (tsc_freq != 0) { 941 if (bootverbose) 942 printf( 943"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 944 tsc_freq = 0; 945 } 946#endif 947 if (tsc_present && tsc_freq == 0) { 948 /* 949 * Calibration of the i586 clock relative to the mc146818A 950 * clock failed. Do a less accurate calibration relative 951 * to the i8254 clock. 952 */ 953 u_int64_t old_tsc = rdtsc(); 954 955 DELAY(1000000); 956 tsc_freq = rdtsc() - old_tsc; 957#ifdef CLK_USE_TSC_CALIBRATION 958 if (bootverbose) 959 printf("TSC clock: %u Hz (Method B)\n", tsc_freq); 960#endif 961 } 962 963#if !defined(SMP) 964 /* 965 * We can not use the TSC in SMP mode, until we figure out a 966 * cheap (impossible), reliable and precise (yeah right!) way 967 * to synchronize the TSCs of all the CPUs. 968 * Curse Intel for leaving the counter out of the I/O APIC. 969 */ 970 971#if NAPM > 0 972 /* 973 * We can not use the TSC if we support APM. Precise timekeeping 974 * on an APM'ed machine is at best a fools pursuit, since 975 * any and all of the time spent in various SMM code can't 976 * be reliably accounted for. Reading the RTC is your only 977 * source of reliable time info. The i8254 looses too of course 978 * but we need to have some kind of time... 979 * We don't know at this point whether APM is going to be used 980 * or not, nor when it might be activated. Play it safe. 981 */ 982 return; 983#endif /* NAPM > 0 */ 984 985 if (tsc_present && tsc_freq != 0 && !tsc_is_broken) { 986 tsc_timecounter.tc_frequency = tsc_freq; 987 init_timecounter(&tsc_timecounter); 988 } 989 990#endif /* !defined(SMP) */ 991} 992 993#ifdef PC98 994static void 995rtc_serialcombit(int i) 996{ 997 outb(IO_RTC, ((i&0x01)<<5)|0x07); 998 DELAY(1); 999 outb(IO_RTC, ((i&0x01)<<5)|0x17); 1000 DELAY(1); 1001 outb(IO_RTC, ((i&0x01)<<5)|0x07); 1002 DELAY(1); 1003} 1004 1005static void 1006rtc_serialcom(int i) 1007{ 1008 rtc_serialcombit(i&0x01); 1009 rtc_serialcombit((i&0x02)>>1); 1010 rtc_serialcombit((i&0x04)>>2); 1011 rtc_serialcombit((i&0x08)>>3); 1012 outb(IO_RTC, 0x07); 1013 DELAY(1); 1014 outb(IO_RTC, 0x0f); 1015 DELAY(1); 1016 outb(IO_RTC, 0x07); 1017 DELAY(1); 1018} 1019 1020static void 1021rtc_outb(int val) 1022{ 1023 int s; 1024 int sa = 0; 1025 1026 for (s=0;s<8;s++) { 1027 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 1028 outb(IO_RTC, sa); /* set DI & CLK 0 */ 1029 DELAY(1); 1030 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 1031 DELAY(1); 1032 } 1033 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 1034} 1035 1036static int 1037rtc_inb(void) 1038{ 1039 int s; 1040 int sa = 0; 1041 1042 for (s=0;s<8;s++) { 1043 sa |= ((inb(0x33) & 0x01) << s); 1044 outb(IO_RTC, 0x17); /* CLK 1 */ 1045 DELAY(1); 1046 outb(IO_RTC, 0x07); /* CLK 0 */ 1047 DELAY(2); 1048 } 1049 return sa; 1050} 1051#endif /* PC-98 */ 1052 1053/* 1054 * Initialize the time of day register, based on the time base which is, e.g. 1055 * from a filesystem. 1056 */ 1057void 1058inittodr(time_t base) 1059{ 1060 unsigned long sec, days; 1061#ifndef PC98 1062 int yd; 1063#endif 1064 int year, month; 1065 int y, m, s; 1066 struct timespec ts; 1067#ifdef PC98 1068 int second, min, hour; 1069#endif 1070 1071 if (base) { 1072 s = splclock(); 1073 ts.tv_sec = base; 1074 ts.tv_nsec = 0; 1075 set_timecounter(&ts); 1076 splx(s); 1077 } 1078 1079#ifdef PC98 1080 rtc_serialcom(0x03); /* Time Read */ 1081 rtc_serialcom(0x01); /* Register shift command. */ 1082 DELAY(20); 1083 1084 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 1085 min = bcd2bin(rtc_inb() & 0xff); /* min */ 1086 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 1087 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 1088 1089 month = (rtc_inb() >> 4) & 0x0f; /* month */ 1090 for (m = 1; m < month; m++) 1091 days += daysinmonth[m-1]; 1092 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 1093 /* 2000 year problem */ 1094 if (year < 1995) 1095 year += 100; 1096 if (year < 1970) 1097 goto wrong_time; 1098 for (y = 1970; y < year; y++) 1099 days += DAYSPERYEAR + LEAPYEAR(y); 1100 if ((month > 2) && LEAPYEAR(year)) 1101 days ++; 1102 sec = ((( days * 24 + 1103 hour) * 60 + 1104 min) * 60 + 1105 second); 1106 /* sec now contains the number of seconds, since Jan 1 1970, 1107 in the local time zone */ 1108#else /* IBM-PC */ 1109 /* Look if we have a RTC present and the time is valid */ 1110 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 1111 goto wrong_time; 1112 1113 /* wait for time update to complete */ 1114 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 1115 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 1116 1117 days = 0; 1118#ifdef USE_RTC_CENTURY 1119 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 1120#else 1121 year = readrtc(RTC_YEAR) + 1900; 1122 if (year < 1970) 1123 year += 100; 1124#endif 1125 if (year < 1970) 1126 goto wrong_time; 1127 month = readrtc(RTC_MONTH); 1128 for (m = 1; m < month; m++) 1129 days += daysinmonth[m-1]; 1130 if ((month > 2) && LEAPYEAR(year)) 1131 days ++; 1132 days += readrtc(RTC_DAY) - 1; 1133 yd = days; 1134 for (y = 1970; y < year; y++) 1135 days += DAYSPERYEAR + LEAPYEAR(y); 1136 sec = ((( days * 24 + 1137 readrtc(RTC_HRS)) * 60 + 1138 readrtc(RTC_MIN)) * 60 + 1139 readrtc(RTC_SEC)); 1140 /* sec now contains the number of seconds, since Jan 1 1970, 1141 in the local time zone */ 1142#endif 1143 1144 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1145 1146 y = time_second - sec; 1147 if (y <= -2 || y >= 2) { 1148 /* badly off, adjust it */ 1149 s = splclock(); 1150 ts.tv_sec = sec; 1151 ts.tv_nsec = 0; 1152 set_timecounter(&ts); 1153 splx(s); 1154 } 1155 return; 1156 1157wrong_time: 1158 printf("Invalid time in real time clock.\n"); 1159 printf("Check and reset the date immediately!\n"); 1160} 1161 1162/* 1163 * Write system time back to RTC 1164 */ 1165void 1166resettodr() 1167{ 1168 unsigned long tm; 1169 int y, m, s; 1170#ifdef PC98 1171 int wd; 1172#endif 1173 1174 if (disable_rtc_set) 1175 return; 1176 1177 s = splclock(); 1178 tm = time_second; 1179 splx(s); 1180 1181#ifdef PC98 1182 rtc_serialcom(0x01); /* Register shift command. */ 1183 1184 /* Calculate local time to put in RTC */ 1185 1186 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1187 1188 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1189 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1190 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1191 1192 /* We have now the days since 01-01-1970 in tm */ 1193 wd = (tm+4)%7; 1194 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1195 tm >= m; 1196 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1197 tm -= m; 1198 1199 /* Now we have the years in y and the day-of-the-year in tm */ 1200 for (m = 0; ; m++) { 1201 int ml; 1202 1203 ml = daysinmonth[m]; 1204 if (m == 1 && LEAPYEAR(y)) 1205 ml++; 1206 if (tm < ml) 1207 break; 1208 tm -= ml; 1209 } 1210 1211 m++; 1212 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1213 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1214 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1215 1216 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1217 rtc_serialcom(0x00); /* Register hold command. */ 1218#else 1219 /* Disable RTC updates and interrupts. */ 1220 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1221 1222 /* Calculate local time to put in RTC */ 1223 1224 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1225 1226 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1227 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1228 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1229 1230 /* We have now the days since 01-01-1970 in tm */ 1231 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1232 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1233 tm >= m; 1234 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1235 tm -= m; 1236 1237 /* Now we have the years in y and the day-of-the-year in tm */ 1238 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1239#ifdef USE_RTC_CENTURY 1240 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1241#endif 1242 for (m = 0; ; m++) { 1243 int ml; 1244 1245 ml = daysinmonth[m]; 1246 if (m == 1 && LEAPYEAR(y)) 1247 ml++; 1248 if (tm < ml) 1249 break; 1250 tm -= ml; 1251 } 1252 1253 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1254 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1255 1256 /* Reenable RTC updates and interrupts. */ 1257 writertc(RTC_STATUSB, rtc_statusb); 1258#endif 1259} 1260 1261 1262/* 1263 * Start both clocks running. 1264 */ 1265void 1266cpu_initclocks() 1267{ 1268#ifdef APIC_IO 1269 int apic_8254_trial; 1270 struct intrec *clkdesc; 1271#endif /* APIC_IO */ 1272#ifndef PC98 1273 int diag; 1274 1275 if (statclock_disable) { 1276 /* 1277 * The stat interrupt mask is different without the 1278 * statistics clock. Also, don't set the interrupt 1279 * flag which would normally cause the RTC to generate 1280 * interrupts. 1281 */ 1282 stat_imask = HWI_MASK | SWI_MASK; 1283 rtc_statusb = RTCSB_24HR; 1284 } else { 1285 /* Setting stathz to nonzero early helps avoid races. */ 1286 stathz = RTC_NOPROFRATE; 1287 profhz = RTC_PROFRATE; 1288 } 1289#endif 1290 1291 /* Finish initializing 8253 timer 0. */ 1292#ifdef APIC_IO 1293 1294 apic_8254_intr = isa_apic_irq(0); 1295 apic_8254_trial = 0; 1296 if (apic_8254_intr >= 0 ) { 1297 if (apic_int_type(0, 0) == 3) 1298 apic_8254_trial = 1; 1299 } else { 1300 /* look for ExtInt on pin 0 */ 1301 if (apic_int_type(0, 0) == 3) { 1302 apic_8254_intr = 0; 1303 setup_8254_mixed_mode(); 1304 } else 1305 panic("APIC_IO: Cannot route 8254 interrupt to CPU"); 1306 } 1307 1308 clkdesc = inthand_add("clk", apic_8254_intr, (inthand2_t *)clkintr, 1309 NULL, &clk_imask, INTR_EXCL); 1310 INTREN(1 << apic_8254_intr); 1311 1312#else /* APIC_IO */ 1313 1314 inthand_add("clk", 0, (inthand2_t *)clkintr, NULL, &clk_imask, 1315 INTR_EXCL); 1316 INTREN(IRQ0); 1317 1318#endif /* APIC_IO */ 1319 1320#ifndef PC98 1321 /* Initialize RTC. */ 1322 writertc(RTC_STATUSA, rtc_statusa); 1323 writertc(RTC_STATUSB, RTCSB_24HR); 1324 1325 /* Don't bother enabling the statistics clock. */ 1326 if (statclock_disable) 1327 return; 1328 diag = rtcin(RTC_DIAG); 1329 if (diag != 0) 1330 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1331 1332#ifdef APIC_IO 1333 if (isa_apic_irq(8) != 8) 1334 panic("APIC RTC != 8"); 1335#endif /* APIC_IO */ 1336 1337 inthand_add("rtc", 8, (inthand2_t *)rtcintr, NULL, &stat_imask, 1338 INTR_EXCL); 1339 1340#ifdef APIC_IO 1341 INTREN(APIC_IRQ8); 1342#else 1343 INTREN(IRQ8); 1344#endif /* APIC_IO */ 1345 1346 writertc(RTC_STATUSB, rtc_statusb); 1347#endif /* !PC98 */ 1348 1349#ifdef APIC_IO 1350 if (apic_8254_trial) { 1351 1352 printf("APIC_IO: Testing 8254 interrupt delivery\n"); 1353 while (read_intr_count(8) < 6) 1354 ; /* nothing */ 1355 if (read_intr_count(apic_8254_intr) < 3) { 1356 /* 1357 * The MP table is broken. 1358 * The 8254 was not connected to the specified pin 1359 * on the IO APIC. 1360 * Workaround: Limited variant of mixed mode. 1361 */ 1362 INTRDIS(1 << apic_8254_intr); 1363 inthand_remove(clkdesc); 1364 printf("APIC_IO: Broken MP table detected: " 1365 "8254 is not connected to IO APIC int pin %d\n", 1366 apic_8254_intr); 1367 1368 apic_8254_intr = 0; 1369 setup_8254_mixed_mode(); 1370 inthand_add("clk", apic_8254_intr,(inthand2_t *)clkintr, 1371 NULL, &clk_imask, INTR_EXCL); 1372 INTREN(1 << apic_8254_intr); 1373 } 1374 1375 } 1376 if (apic_8254_intr) 1377 printf("APIC_IO: routing 8254 via pin %d\n",apic_8254_intr); 1378 else 1379 printf("APIC_IO: routing 8254 via 8259 on pin 0\n"); 1380#endif 1381 1382} 1383 1384#ifdef APIC_IO 1385static u_long 1386read_intr_count(int vec) 1387{ 1388 u_long *up; 1389 up = intr_countp[vec]; 1390 if (up) 1391 return *up; 1392 return 0UL; 1393} 1394 1395static void 1396setup_8254_mixed_mode() 1397{ 1398 /* 1399 * Allow 8254 timer to INTerrupt 8259: 1400 * re-initialize master 8259: 1401 * reset; prog 4 bytes, single ICU, edge triggered 1402 */ 1403 outb(IO_ICU1, 0x13); 1404#ifdef PC98 1405 outb(IO_ICU1 + 2, NRSVIDT); /* start vector (unused) */ 1406 outb(IO_ICU1 + 2, 0x00); /* ignore slave */ 1407 outb(IO_ICU1 + 2, 0x03); /* auto EOI, 8086 */ 1408 outb(IO_ICU1 + 2, 0xfe); /* unmask INT0 */ 1409#else 1410 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */ 1411 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1412 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1413 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1414#endif 1415 /* program IO APIC for type 3 INT on INT0 */ 1416 if (ext_int_setup(0, 0) < 0) 1417 panic("8254 redirect via APIC pin0 impossible!"); 1418} 1419#endif 1420 1421void 1422setstatclockrate(int newhz) 1423{ 1424#ifndef PC98 1425 if (newhz == RTC_PROFRATE) 1426 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1427 else 1428 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1429 writertc(RTC_STATUSA, rtc_statusa); 1430#endif 1431} 1432 1433static int 1434sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1435{ 1436 int error; 1437 u_int freq; 1438 1439 /* 1440 * Use `i8254' instead of `timer' in external names because `timer' 1441 * is is too generic. Should use it everywhere. 1442 */ 1443 freq = timer_freq; 1444 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 1445 if (error == 0 && req->newptr != NULL) { 1446 if (timer0_state != RELEASED) 1447 return (EBUSY); /* too much trouble to handle */ 1448 set_timer_freq(freq, hz); 1449 i8254_timecounter.tc_frequency = freq; 1450 update_timecounter(&i8254_timecounter); 1451 } 1452 return (error); 1453} 1454 1455SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1456 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1457 1458static int 1459sysctl_machdep_tsc_freq SYSCTL_HANDLER_ARGS 1460{ 1461 int error; 1462 u_int freq; 1463 1464 if (tsc_timecounter.tc_frequency == 0) 1465 return (EOPNOTSUPP); 1466 freq = tsc_freq; 1467 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 1468 if (error == 0 && req->newptr != NULL) { 1469 tsc_freq = freq; 1470 tsc_timecounter.tc_frequency = tsc_freq; 1471 update_timecounter(&tsc_timecounter); 1472 } 1473 return (error); 1474} 1475 1476SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW, 1477 0, sizeof(u_int), sysctl_machdep_tsc_freq, "I", ""); 1478 1479static unsigned 1480i8254_get_timecount(struct timecounter *tc) 1481{ 1482 u_int count; 1483 u_long ef; 1484 u_int high, low; 1485 1486 ef = read_eflags(); 1487 disable_intr(); 1488 1489 /* Select timer0 and latch counter value. */ 1490 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 1491 1492 low = inb(TIMER_CNTR0); 1493 high = inb(TIMER_CNTR0); 1494 count = timer0_max_count - ((high << 8) | low); 1495 if (count < i8254_lastcount || 1496 (!i8254_ticked && (clkintr_pending || 1497 ((count < 20 || (!(ef & PSL_I) && count < timer0_max_count / 2u)) && 1498#ifdef APIC_IO 1499#define lapic_irr1 ((volatile u_int *)&lapic)[0x210 / 4] /* XXX XXX */ 1500 /* XXX this assumes that apic_8254_intr is < 24. */ 1501 (lapic_irr1 & (1 << apic_8254_intr)))) 1502#else 1503 (inb(IO_ICU1) & 1))) 1504#endif 1505 )) { 1506 i8254_ticked = 1; 1507 i8254_offset += timer0_max_count; 1508 } 1509 i8254_lastcount = count; 1510 count += i8254_offset; 1511 CLOCK_UNLOCK(); 1512 write_eflags(ef); 1513 return (count); 1514} 1515 1516static unsigned 1517tsc_get_timecount(struct timecounter *tc) 1518{ 1519 return (rdtsc()); 1520} 1521