pcrtc.c revision 36254
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $Id: clock.c,v 1.53 1998/05/04 07:47:24 kato Exp $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51/* 52 * modified for PC98 by Kakefuda 53 */ 54 55#include "opt_clock.h" 56#include "apm.h" 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/time.h> 61#include <sys/kernel.h> 62#ifndef SMP 63#include <sys/lock.h> 64#endif 65#include <sys/sysctl.h> 66 67#include <machine/clock.h> 68#ifdef CLK_CALIBRATION_LOOP 69#include <machine/cons.h> 70#endif 71#include <machine/cputypes.h> 72#include <machine/frame.h> 73#include <machine/ipl.h> 74#include <machine/limits.h> 75#include <machine/md_var.h> 76#if NAPM > 0 77#include <machine/apm_bios.h> 78#include <i386/apm/apm_setup.h> 79#endif 80#ifdef APIC_IO 81#include <machine/segments.h> 82#endif 83#if defined(SMP) || defined(APIC_IO) 84#include <machine/smp.h> 85#endif /* SMP || APIC_IO */ 86#include <machine/specialreg.h> 87 88#include <i386/isa/icu.h> 89#ifdef PC98 90#include <pc98/pc98/pc98.h> 91#include <pc98/pc98/pc98_machdep.h> 92#include <i386/isa/isa_device.h> 93#else 94#include <i386/isa/isa.h> 95#include <i386/isa/rtc.h> 96#endif 97#include <i386/isa/timerreg.h> 98 99#include <sys/interrupt.h> 100 101#ifdef SMP 102#define disable_intr() CLOCK_DISABLE_INTR() 103#define enable_intr() CLOCK_ENABLE_INTR() 104 105#ifdef APIC_IO 106#include <i386/isa/intr_machdep.h> 107/* The interrupt triggered by the 8254 (timer) chip */ 108int apic_8254_intr; 109static u_long read_intr_count __P((int vec)); 110static void setup_8254_mixed_mode __P((void)); 111#endif 112#endif /* SMP */ 113 114/* 115 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 116 * can use a simple formula for leap years. 117 */ 118#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 119#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 120 121#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 122 123/* 124 * Time in timer cycles that it takes for microtime() to disable interrupts 125 * and latch the count. microtime() currently uses "cli; outb ..." so it 126 * normally takes less than 2 timer cycles. Add a few for cache misses. 127 * Add a few more to allow for latency in bogus calls to microtime() with 128 * interrupts already disabled. 129 */ 130#define TIMER0_LATCH_COUNT 20 131 132/* 133 * Maximum frequency that we are willing to allow for timer0. Must be 134 * low enough to guarantee that the timer interrupt handler returns 135 * before the next timer interrupt. 136 */ 137#define TIMER0_MAX_FREQ 20000 138 139int adjkerntz; /* local offset from GMT in seconds */ 140int disable_rtc_set; /* disable resettodr() if != 0 */ 141u_int idelayed; 142int statclock_disable; 143u_int stat_imask = SWI_CLOCK_MASK; 144#ifndef TIMER_FREQ 145#ifdef PC98 146#define TIMER_FREQ 2457600; 147#else /* IBM-PC */ 148#define TIMER_FREQ 1193182; 149#endif /* PC98 */ 150#endif 151u_int timer_freq = TIMER_FREQ; 152int timer0_max_count; 153u_int tsc_freq; 154int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 155 156static int beeping = 0; 157static u_int clk_imask = HWI_MASK | SWI_MASK; 158static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 159static u_int hardclock_max_count; 160static u_int32_t i8254_lastcount; 161static u_int32_t i8254_offset; 162static int i8254_ticked; 163/* 164 * XXX new_function and timer_func should not handle clockframes, but 165 * timer_func currently needs to hold hardclock to handle the 166 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 167 * to switch between clkintr() and a slightly different timerintr(). 168 */ 169static void (*new_function) __P((struct clockframe *frame)); 170static u_int new_rate; 171#ifndef PC98 172static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 173static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 174#endif 175static u_int timer0_prescaler_count; 176 177/* Values for timerX_state: */ 178#define RELEASED 0 179#define RELEASE_PENDING 1 180#define ACQUIRED 2 181#define ACQUIRE_PENDING 3 182 183static u_char timer0_state; 184#ifdef PC98 185static u_char timer1_state; 186#endif 187static u_char timer2_state; 188static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 189#ifdef PC98 190static void rtc_serialcombit __P((int)); 191static void rtc_serialcom __P((int)); 192static int rtc_inb __P((void)); 193static void rtc_outb __P((int)); 194#endif 195static u_int tsc_present; 196 197static unsigned i8254_get_timecount __P((void)); 198static unsigned tsc_get_timecount __P((void)); 199static void set_timer_freq(u_int freq, int intr_freq); 200 201static struct timecounter tsc_timecounter[3] = { 202 tsc_get_timecount, /* get_timecount */ 203 ~0u, /* counter_mask */ 204 0, /* frequency */ 205 "TSC" /* name */ 206}; 207 208SYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD, 209 tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", ""); 210 211static struct timecounter i8254_timecounter[3] = { 212 i8254_get_timecount, /* get_timecount */ 213 ~0u, /* counter_mask */ 214 0, /* frequency */ 215 "i8254" /* name */ 216}; 217 218SYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD, 219 i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", ""); 220 221static void 222clkintr(struct clockframe frame) 223{ 224 if (!i8254_ticked) 225 i8254_offset += timer0_max_count; 226 else 227 i8254_ticked = 0; 228 i8254_lastcount = 0; 229 timer_func(&frame); 230 switch (timer0_state) { 231 232 case RELEASED: 233 setdelayed(); 234 break; 235 236 case ACQUIRED: 237 if ((timer0_prescaler_count += timer0_max_count) 238 >= hardclock_max_count) { 239 timer0_prescaler_count -= hardclock_max_count; 240 hardclock(&frame); 241 setdelayed(); 242 } 243 break; 244 245 case ACQUIRE_PENDING: 246 setdelayed(); 247 timer0_max_count = TIMER_DIV(new_rate); 248 disable_intr(); 249 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 250 outb(TIMER_CNTR0, timer0_max_count & 0xff); 251 outb(TIMER_CNTR0, timer0_max_count >> 8); 252 enable_intr(); 253 timer0_prescaler_count = 0; 254 timer_func = new_function; 255 timer0_state = ACQUIRED; 256 break; 257 258 case RELEASE_PENDING: 259 if ((timer0_prescaler_count += timer0_max_count) 260 >= hardclock_max_count) { 261 timer0_prescaler_count -= hardclock_max_count; 262#ifdef FIXME 263 /* 264 * XXX: This magic doesn't work, but It shouldn't be 265 * needed now anyway since we will not be able to 266 * aquire the i8254 if it is used for timecounting. 267 */ 268 /* 269 * See microtime.s for this magic. 270 */ 271#ifdef PC98 272 if (pc98_machine_type & M_8M) { 273 /* PC98_8M */ 274 time.tv_usec += (16411 * timer0_prescaler_count) >> 15; 275 } else { 276 time.tv_usec += (6667 * timer0_prescaler_count) >> 14; 277 } 278#else /* IBM-PC */ 279 time.tv_usec += (27465 * timer0_prescaler_count) >> 15; 280#endif 281 if (time.tv_usec >= 1000000) 282 time.tv_usec -= 1000000; 283#endif 284 hardclock(&frame); 285 setdelayed(); 286 timer0_max_count = hardclock_max_count; 287 disable_intr(); 288 outb(TIMER_MODE, 289 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 290 outb(TIMER_CNTR0, timer0_max_count & 0xff); 291 outb(TIMER_CNTR0, timer0_max_count >> 8); 292 enable_intr(); 293 timer0_prescaler_count = 0; 294 timer_func = hardclock; 295 timer0_state = RELEASED; 296 } 297 break; 298 } 299} 300 301/* 302 * The acquire and release functions must be called at ipl >= splclock(). 303 */ 304int 305acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 306{ 307 static int old_rate; 308 309 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 310 return (-1); 311 if (strcmp(timecounter->name, "i8254") == 0) 312 return (-1); 313 switch (timer0_state) { 314 315 case RELEASED: 316 timer0_state = ACQUIRE_PENDING; 317 break; 318 319 case RELEASE_PENDING: 320 if (rate != old_rate) 321 return (-1); 322 /* 323 * The timer has been released recently, but is being 324 * re-acquired before the release completed. In this 325 * case, we simply reclaim it as if it had not been 326 * released at all. 327 */ 328 timer0_state = ACQUIRED; 329 break; 330 331 default: 332 return (-1); /* busy */ 333 } 334 new_function = function; 335 old_rate = new_rate = rate; 336 return (0); 337} 338 339#ifdef PC98 340int 341acquire_timer1(int mode) 342{ 343 344 if (timer1_state != RELEASED) 345 return (-1); 346 timer1_state = ACQUIRED; 347 348 /* 349 * This access to the timer registers is as atomic as possible 350 * because it is a single instruction. We could do better if we 351 * knew the rate. Use of splclock() limits glitches to 10-100us, 352 * and this is probably good enough for timer2, so we aren't as 353 * careful with it as with timer0. 354 */ 355 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 356 357 return (0); 358} 359#endif 360 361int 362acquire_timer2(int mode) 363{ 364 365 if (timer2_state != RELEASED) 366 return (-1); 367 timer2_state = ACQUIRED; 368 369 /* 370 * This access to the timer registers is as atomic as possible 371 * because it is a single instruction. We could do better if we 372 * knew the rate. Use of splclock() limits glitches to 10-100us, 373 * and this is probably good enough for timer2, so we aren't as 374 * careful with it as with timer0. 375 */ 376 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 377 378 return (0); 379} 380 381int 382release_timer0() 383{ 384 switch (timer0_state) { 385 386 case ACQUIRED: 387 timer0_state = RELEASE_PENDING; 388 break; 389 390 case ACQUIRE_PENDING: 391 /* Nothing happened yet, release quickly. */ 392 timer0_state = RELEASED; 393 break; 394 395 default: 396 return (-1); 397 } 398 return (0); 399} 400 401#ifdef PC98 402int 403release_timer1() 404{ 405 406 if (timer1_state != ACQUIRED) 407 return (-1); 408 timer1_state = RELEASED; 409 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 410 return (0); 411} 412#endif 413 414int 415release_timer2() 416{ 417 418 if (timer2_state != ACQUIRED) 419 return (-1); 420 timer2_state = RELEASED; 421 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 422 return (0); 423} 424 425#ifndef PC98 426/* 427 * This routine receives statistical clock interrupts from the RTC. 428 * As explained above, these occur at 128 interrupts per second. 429 * When profiling, we receive interrupts at a rate of 1024 Hz. 430 * 431 * This does not actually add as much overhead as it sounds, because 432 * when the statistical clock is active, the hardclock driver no longer 433 * needs to keep (inaccurate) statistics on its own. This decouples 434 * statistics gathering from scheduling interrupts. 435 * 436 * The RTC chip requires that we read status register C (RTC_INTR) 437 * to acknowledge an interrupt, before it will generate the next one. 438 * Under high interrupt load, rtcintr() can be indefinitely delayed and 439 * the clock can tick immediately after the read from RTC_INTR. In this 440 * case, the mc146818A interrupt signal will not drop for long enough 441 * to register with the 8259 PIC. If an interrupt is missed, the stat 442 * clock will halt, considerably degrading system performance. This is 443 * why we use 'while' rather than a more straightforward 'if' below. 444 * Stat clock ticks can still be lost, causing minor loss of accuracy 445 * in the statistics, but the stat clock will no longer stop. 446 */ 447static void 448rtcintr(struct clockframe frame) 449{ 450 while (rtcin(RTC_INTR) & RTCIR_PERIOD) 451 statclock(&frame); 452} 453 454#include "opt_ddb.h" 455#ifdef DDB 456#include <ddb/ddb.h> 457 458DB_SHOW_COMMAND(rtc, rtc) 459{ 460 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 461 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 462 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 463 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 464} 465#endif /* DDB */ 466#endif /* for PC98 */ 467 468static int 469getit(void) 470{ 471 u_long ef; 472 int high, low; 473 474 ef = read_eflags(); 475 disable_intr(); 476 477 /* Select timer0 and latch counter value. */ 478 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 479 480 low = inb(TIMER_CNTR0); 481 high = inb(TIMER_CNTR0); 482 483 CLOCK_UNLOCK(); 484 write_eflags(ef); 485 return ((high << 8) | low); 486} 487 488/* 489 * Wait "n" microseconds. 490 * Relies on timer 1 counting down from (timer_freq / hz) 491 * Note: timer had better have been programmed before this is first used! 492 */ 493void 494DELAY(int n) 495{ 496 int delta, prev_tick, tick, ticks_left; 497 498#ifdef DELAYDEBUG 499 int getit_calls = 1; 500 int n1; 501 static int state = 0; 502 503 if (state == 0) { 504 state = 1; 505 for (n1 = 1; n1 <= 10000000; n1 *= 10) 506 DELAY(n1); 507 state = 2; 508 } 509 if (state == 1) 510 printf("DELAY(%d)...", n); 511#endif 512 /* 513 * Guard against the timer being uninitialized if we are called 514 * early for console i/o. 515 */ 516 if (timer0_max_count == 0) 517 set_timer_freq(timer_freq, hz); 518 519 /* 520 * Read the counter first, so that the rest of the setup overhead is 521 * counted. Guess the initial overhead is 20 usec (on most systems it 522 * takes about 1.5 usec for each of the i/o's in getit(). The loop 523 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 524 * multiplications and divisions to scale the count take a while). 525 */ 526 prev_tick = getit(); 527 n -= 0; /* XXX actually guess no initial overhead */ 528 /* 529 * Calculate (n * (timer_freq / 1e6)) without using floating point 530 * and without any avoidable overflows. 531 */ 532 if (n <= 0) 533 ticks_left = 0; 534 else if (n < 256) 535 /* 536 * Use fixed point to avoid a slow division by 1000000. 537 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 538 * 2^15 is the first power of 2 that gives exact results 539 * for n between 0 and 256. 540 */ 541 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 542 else 543 /* 544 * Don't bother using fixed point, although gcc-2.7.2 545 * generates particularly poor code for the long long 546 * division, since even the slow way will complete long 547 * before the delay is up (unless we're interrupted). 548 */ 549 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 550 / 1000000; 551 552 while (ticks_left > 0) { 553 tick = getit(); 554#ifdef DELAYDEBUG 555 ++getit_calls; 556#endif 557 delta = prev_tick - tick; 558 prev_tick = tick; 559 if (delta < 0) { 560 delta += timer0_max_count; 561 /* 562 * Guard against timer0_max_count being wrong. 563 * This shouldn't happen in normal operation, 564 * but it may happen if set_timer_freq() is 565 * traced. 566 */ 567 if (delta < 0) 568 delta = 0; 569 } 570 ticks_left -= delta; 571 } 572#ifdef DELAYDEBUG 573 if (state == 1) 574 printf(" %d calls to getit() at %d usec each\n", 575 getit_calls, (n + 5) / getit_calls); 576#endif 577} 578 579static void 580sysbeepstop(void *chan) 581{ 582#ifdef PC98 /* PC98 */ 583 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 584 release_timer1(); 585#else 586 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 587 release_timer2(); 588#endif 589 beeping = 0; 590} 591 592int 593sysbeep(int pitch, int period) 594{ 595 int x = splclock(); 596 597#ifdef PC98 598 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 599 if (!beeping) { 600 /* Something else owns it. */ 601 splx(x); 602 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 603 } 604 disable_intr(); 605 outb(0x3fdb, pitch); 606 outb(0x3fdb, (pitch>>8)); 607 enable_intr(); 608 if (!beeping) { 609 /* enable counter1 output to speaker */ 610 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 611 beeping = period; 612 timeout(sysbeepstop, (void *)NULL, period); 613 } 614#else 615 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 616 if (!beeping) { 617 /* Something else owns it. */ 618 splx(x); 619 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 620 } 621 disable_intr(); 622 outb(TIMER_CNTR2, pitch); 623 outb(TIMER_CNTR2, (pitch>>8)); 624 enable_intr(); 625 if (!beeping) { 626 /* enable counter2 output to speaker */ 627 outb(IO_PPI, inb(IO_PPI) | 3); 628 beeping = period; 629 timeout(sysbeepstop, (void *)NULL, period); 630 } 631#endif 632 splx(x); 633 return (0); 634} 635 636#ifndef PC98 637/* 638 * RTC support routines 639 */ 640 641int 642rtcin(reg) 643 int reg; 644{ 645 u_char val; 646 647 outb(IO_RTC, reg); 648 inb(0x84); 649 val = inb(IO_RTC + 1); 650 inb(0x84); 651 return (val); 652} 653 654static __inline void 655writertc(u_char reg, u_char val) 656{ 657 inb(0x84); 658 outb(IO_RTC, reg); 659 inb(0x84); 660 outb(IO_RTC + 1, val); 661 inb(0x84); /* XXX work around wrong order in rtcin() */ 662} 663 664static __inline int 665readrtc(int port) 666{ 667 return(bcd2bin(rtcin(port))); 668} 669#endif 670 671#ifdef PC98 672unsigned int delaycount; 673#define FIRST_GUESS 0x2000 674static void findcpuspeed(void) 675{ 676 int i; 677 int remainder; 678 679 /* Put counter in count down mode */ 680 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 681 outb(TIMER_CNTR0, 0xff); 682 outb(TIMER_CNTR0, 0xff); 683 for (i = FIRST_GUESS; i; i--) 684 ; 685 remainder = getit(); 686 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 687} 688#endif 689 690#ifndef PC98 691static u_int 692calibrate_clocks(void) 693{ 694 u_int count, prev_count, tot_count; 695 int sec, start_sec, timeout; 696 697 if (bootverbose) 698 printf("Calibrating clock(s) ... "); 699 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 700 goto fail; 701 timeout = 100000000; 702 703 /* Read the mc146818A seconds counter. */ 704 for (;;) { 705 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 706 sec = rtcin(RTC_SEC); 707 break; 708 } 709 if (--timeout == 0) 710 goto fail; 711 } 712 713 /* Wait for the mC146818A seconds counter to change. */ 714 start_sec = sec; 715 for (;;) { 716 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 717 sec = rtcin(RTC_SEC); 718 if (sec != start_sec) 719 break; 720 } 721 if (--timeout == 0) 722 goto fail; 723 } 724 725 /* Start keeping track of the i8254 counter. */ 726 prev_count = getit(); 727 if (prev_count == 0 || prev_count > timer0_max_count) 728 goto fail; 729 tot_count = 0; 730 731 if (tsc_present) 732 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 733 734 /* 735 * Wait for the mc146818A seconds counter to change. Read the i8254 736 * counter for each iteration since this is convenient and only 737 * costs a few usec of inaccuracy. The timing of the final reads 738 * of the counters almost matches the timing of the initial reads, 739 * so the main cause of inaccuracy is the varying latency from 740 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 741 * rtcin(RTC_SEC) that returns a changed seconds count. The 742 * maximum inaccuracy from this cause is < 10 usec on 486's. 743 */ 744 start_sec = sec; 745 for (;;) { 746 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 747 sec = rtcin(RTC_SEC); 748 count = getit(); 749 if (count == 0 || count > timer0_max_count) 750 goto fail; 751 if (count > prev_count) 752 tot_count += prev_count - (count - timer0_max_count); 753 else 754 tot_count += prev_count - count; 755 prev_count = count; 756 if (sec != start_sec) 757 break; 758 if (--timeout == 0) 759 goto fail; 760 } 761 762 /* 763 * Read the cpu cycle counter. The timing considerations are 764 * similar to those for the i8254 clock. 765 */ 766 if (tsc_present) 767 tsc_freq = rdtsc(); 768 769 if (bootverbose) { 770 if (tsc_present) 771 printf("TSC clock: %u Hz, ", tsc_freq); 772 printf("i8254 clock: %u Hz\n", tot_count); 773 } 774 return (tot_count); 775 776fail: 777 if (bootverbose) 778 printf("failed, using default i8254 clock of %u Hz\n", 779 timer_freq); 780 return (timer_freq); 781} 782#endif /* !PC98 */ 783 784static void 785set_timer_freq(u_int freq, int intr_freq) 786{ 787 u_long ef; 788 int new_timer0_max_count; 789 790 ef = read_eflags(); 791 disable_intr(); 792 timer_freq = freq; 793 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 794 if (new_timer0_max_count != timer0_max_count) { 795 timer0_max_count = new_timer0_max_count; 796 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 797 outb(TIMER_CNTR0, timer0_max_count & 0xff); 798 outb(TIMER_CNTR0, timer0_max_count >> 8); 799 } 800 CLOCK_UNLOCK(); 801 write_eflags(ef); 802} 803 804/* 805 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 806 * XXX initialization of other timers is unintentionally left blank. 807 */ 808void 809startrtclock() 810{ 811 u_int delta, freq; 812 813#ifdef PC98 814 findcpuspeed(); 815 if (pc98_machine_type & M_8M) 816 timer_freq = 1996800L; /* 1.9968 MHz */ 817 else 818 timer_freq = 2457600L; /* 2.4576 MHz */ 819#endif /* PC98 */ 820 821 if (cpu_feature & CPUID_TSC) 822 tsc_present = 1; 823 else 824 tsc_present = 0; 825 826#ifndef PC98 827 writertc(RTC_STATUSA, rtc_statusa); 828 writertc(RTC_STATUSB, RTCSB_24HR); 829#endif 830 831#ifndef PC98 832 set_timer_freq(timer_freq, hz); 833 freq = calibrate_clocks(); 834#ifdef CLK_CALIBRATION_LOOP 835 if (bootverbose) { 836 printf( 837 "Press a key on the console to abort clock calibration\n"); 838 while (cncheckc() == -1) 839 calibrate_clocks(); 840 } 841#endif 842 843 /* 844 * Use the calibrated i8254 frequency if it seems reasonable. 845 * Otherwise use the default, and don't use the calibrated i586 846 * frequency. 847 */ 848 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 849 if (delta < timer_freq / 100) { 850#ifndef CLK_USE_I8254_CALIBRATION 851 if (bootverbose) 852 printf( 853"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 854 freq = timer_freq; 855#endif 856 timer_freq = freq; 857 } else { 858 if (bootverbose) 859 printf( 860 "%d Hz differs from default of %d Hz by more than 1%%\n", 861 freq, timer_freq); 862 tsc_freq = 0; 863 } 864#endif 865 866 set_timer_freq(timer_freq, hz); 867 i8254_timecounter[0].frequency = timer_freq; 868 init_timecounter(i8254_timecounter); 869 870#ifndef CLK_USE_TSC_CALIBRATION 871 if (tsc_freq != 0) { 872 if (bootverbose) 873 printf( 874"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 875 tsc_freq = 0; 876 } 877#endif 878 if (tsc_present && tsc_freq == 0) { 879 /* 880 * Calibration of the i586 clock relative to the mc146818A 881 * clock failed. Do a less accurate calibration relative 882 * to the i8254 clock. 883 */ 884 wrmsr(0x10, 0LL); /* XXX */ 885 DELAY(1000000); 886 tsc_freq = rdtsc(); 887#ifdef CLK_USE_TSC_CALIBRATION 888 if (bootverbose) 889 printf("TSC clock: %u Hz (Method B)\n", tsc_freq); 890#endif 891 } 892 893#if !defined(SMP) 894 /* 895 * We can not use the TSC in SMP mode, until we figure out a 896 * cheap (impossible), reliable and precise (yeah right!) way 897 * to synchronize the TSCs of all the CPUs. 898 * Curse Intel for leaving the counter out of the I/O APIC. 899 */ 900 901#if NAPM > 0 902 /* 903 * We can not use the TSC if we found an APM bios. Too many 904 * of them lie about their ability&intention to fiddle the CPU 905 * clock for us to rely on this. Precise timekeeping on an 906 * APM'ed machine is at best a fools pursuit anyway, since 907 * any and all of the time spent in various SMM code can't 908 * be reliably accounted for. Reading the RTC is your only 909 * source of reliable time info. The i8254 looses too of course 910 * but we need to have some kind of time... 911 */ 912 if (apm_version != APMINI_CANTFIND) 913 return; 914#endif /* NAPM > 0 */ 915 916 if (tsc_present && tsc_freq != 0) { 917 tsc_timecounter[0].frequency = tsc_freq; 918 init_timecounter(tsc_timecounter); 919 } 920 921#endif /* !defined(SMP) */ 922} 923 924#ifdef PC98 925static void 926rtc_serialcombit(int i) 927{ 928 outb(IO_RTC, ((i&0x01)<<5)|0x07); 929 DELAY(1); 930 outb(IO_RTC, ((i&0x01)<<5)|0x17); 931 DELAY(1); 932 outb(IO_RTC, ((i&0x01)<<5)|0x07); 933 DELAY(1); 934} 935 936static void 937rtc_serialcom(int i) 938{ 939 rtc_serialcombit(i&0x01); 940 rtc_serialcombit((i&0x02)>>1); 941 rtc_serialcombit((i&0x04)>>2); 942 rtc_serialcombit((i&0x08)>>3); 943 outb(IO_RTC, 0x07); 944 DELAY(1); 945 outb(IO_RTC, 0x0f); 946 DELAY(1); 947 outb(IO_RTC, 0x07); 948 DELAY(1); 949} 950 951static void 952rtc_outb(int val) 953{ 954 int s; 955 int sa = 0; 956 957 for (s=0;s<8;s++) { 958 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 959 outb(IO_RTC, sa); /* set DI & CLK 0 */ 960 DELAY(1); 961 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 962 DELAY(1); 963 } 964 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 965} 966 967static int 968rtc_inb(void) 969{ 970 int s; 971 int sa = 0; 972 973 for (s=0;s<8;s++) { 974 sa |= ((inb(0x33) & 0x01) << s); 975 outb(IO_RTC, 0x17); /* CLK 1 */ 976 DELAY(1); 977 outb(IO_RTC, 0x07); /* CLK 0 */ 978 DELAY(2); 979 } 980 return sa; 981} 982#endif /* PC-98 */ 983 984/* 985 * Initialize the time of day register, based on the time base which is, e.g. 986 * from a filesystem. 987 */ 988void 989inittodr(time_t base) 990{ 991 unsigned long sec, days; 992 int yd; 993 int year, month; 994 int y, m, s; 995 struct timespec ts; 996#ifdef PC98 997 int second, min, hour; 998#endif 999 1000 if (base) { 1001 s = splclock(); 1002 ts.tv_sec = base; 1003 ts.tv_nsec = 0; 1004 set_timecounter(&ts); 1005 splx(s); 1006 } 1007 1008#ifdef PC98 1009 rtc_serialcom(0x03); /* Time Read */ 1010 rtc_serialcom(0x01); /* Register shift command. */ 1011 DELAY(20); 1012 1013 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 1014 min = bcd2bin(rtc_inb() & 0xff); /* min */ 1015 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 1016 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 1017 1018 month = (rtc_inb() >> 4) & 0x0f; /* month */ 1019 for (m = 1; m < month; m++) 1020 days += daysinmonth[m-1]; 1021 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 1022 /* 2000 year problem */ 1023 if (year < 1995) 1024 year += 100; 1025 if (year < 1970) 1026 goto wrong_time; 1027 for (y = 1970; y < year; y++) 1028 days += DAYSPERYEAR + LEAPYEAR(y); 1029 if ((month > 2) && LEAPYEAR(year)) 1030 days ++; 1031 sec = ((( days * 24 + 1032 hour) * 60 + 1033 min) * 60 + 1034 second); 1035 /* sec now contains the number of seconds, since Jan 1 1970, 1036 in the local time zone */ 1037#else /* IBM-PC */ 1038 /* Look if we have a RTC present and the time is valid */ 1039 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 1040 goto wrong_time; 1041 1042 /* wait for time update to complete */ 1043 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 1044 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 1045 1046 days = 0; 1047#ifdef USE_RTC_CENTURY 1048 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 1049#else 1050 year = readrtc(RTC_YEAR) + 1900; 1051 if (year < 1970) 1052 year += 100; 1053#endif 1054 if (year < 1970) 1055 goto wrong_time; 1056 month = readrtc(RTC_MONTH); 1057 for (m = 1; m < month; m++) 1058 days += daysinmonth[m-1]; 1059 if ((month > 2) && LEAPYEAR(year)) 1060 days ++; 1061 days += readrtc(RTC_DAY) - 1; 1062 yd = days; 1063 for (y = 1970; y < year; y++) 1064 days += DAYSPERYEAR + LEAPYEAR(y); 1065 sec = ((( days * 24 + 1066 readrtc(RTC_HRS)) * 60 + 1067 readrtc(RTC_MIN)) * 60 + 1068 readrtc(RTC_SEC)); 1069 /* sec now contains the number of seconds, since Jan 1 1970, 1070 in the local time zone */ 1071#endif 1072 1073 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1074 1075 y = time_second - sec; 1076 if (y <= -2 || y >= 2) { 1077 /* badly off, adjust it */ 1078 s = splclock(); 1079 ts.tv_sec = sec; 1080 ts.tv_nsec = 0; 1081 set_timecounter(&ts); 1082 splx(s); 1083 } 1084 return; 1085 1086wrong_time: 1087 printf("Invalid time in real time clock.\n"); 1088 printf("Check and reset the date immediately!\n"); 1089} 1090 1091/* 1092 * Write system time back to RTC 1093 */ 1094void 1095resettodr() 1096{ 1097 unsigned long tm; 1098 int y, m, s; 1099#ifdef PC98 1100 int wd; 1101#endif 1102 1103 if (disable_rtc_set) 1104 return; 1105 1106 s = splclock(); 1107 tm = time_second; 1108 splx(s); 1109 1110#ifdef PC98 1111 rtc_serialcom(0x01); /* Register shift command. */ 1112 1113 /* Calculate local time to put in RTC */ 1114 1115 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1116 1117 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1118 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1119 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1120 1121 /* We have now the days since 01-01-1970 in tm */ 1122 wd = (tm+4)%7; 1123 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1124 tm >= m; 1125 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1126 tm -= m; 1127 1128 /* Now we have the years in y and the day-of-the-year in tm */ 1129 for (m = 0; ; m++) { 1130 int ml; 1131 1132 ml = daysinmonth[m]; 1133 if (m == 1 && LEAPYEAR(y)) 1134 ml++; 1135 if (tm < ml) 1136 break; 1137 tm -= ml; 1138 } 1139 1140 m++; 1141 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1142 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1143 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1144 1145 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1146 rtc_serialcom(0x00); /* Register hold command. */ 1147#else 1148 /* Disable RTC updates and interrupts. */ 1149 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1150 1151 /* Calculate local time to put in RTC */ 1152 1153 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1154 1155 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1156 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1157 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1158 1159 /* We have now the days since 01-01-1970 in tm */ 1160 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1161 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1162 tm >= m; 1163 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1164 tm -= m; 1165 1166 /* Now we have the years in y and the day-of-the-year in tm */ 1167 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1168#ifdef USE_RTC_CENTURY 1169 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1170#endif 1171 for (m = 0; ; m++) { 1172 int ml; 1173 1174 ml = daysinmonth[m]; 1175 if (m == 1 && LEAPYEAR(y)) 1176 ml++; 1177 if (tm < ml) 1178 break; 1179 tm -= ml; 1180 } 1181 1182 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1183 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1184 1185 /* Reenable RTC updates and interrupts. */ 1186 writertc(RTC_STATUSB, rtc_statusb); 1187#endif 1188} 1189 1190 1191/* 1192 * Start both clocks running. 1193 */ 1194void 1195cpu_initclocks() 1196{ 1197#ifdef APIC_IO 1198 int apic_8254_trial; 1199#endif /* APIC_IO */ 1200#ifndef PC98 1201 int diag; 1202 1203 if (statclock_disable) { 1204 /* 1205 * The stat interrupt mask is different without the 1206 * statistics clock. Also, don't set the interrupt 1207 * flag which would normally cause the RTC to generate 1208 * interrupts. 1209 */ 1210 stat_imask = HWI_MASK | SWI_MASK; 1211 rtc_statusb = RTCSB_24HR; 1212 } else { 1213 /* Setting stathz to nonzero early helps avoid races. */ 1214 stathz = RTC_NOPROFRATE; 1215 profhz = RTC_PROFRATE; 1216 } 1217#endif 1218 1219 /* Finish initializing 8253 timer 0. */ 1220#ifdef APIC_IO 1221 1222 apic_8254_intr = isa_apic_pin(0); 1223 apic_8254_trial = 0; 1224 if (apic_8254_intr >= 0 ) { 1225 if (apic_int_type(0, 0) == 3) 1226 apic_8254_trial = 1; 1227 } else { 1228 /* look for ExtInt on pin 0 */ 1229 if (apic_int_type(0, 0) == 3) { 1230 apic_8254_intr = 0; 1231 setup_8254_mixed_mode(); 1232 } else 1233 panic("APIC_IO: Cannot route 8254 interrupt to CPU"); 1234 } 1235 1236 register_intr(/* irq */ apic_8254_intr, /* XXX id */ 0, /* flags */ 0, 1237 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1238 /* unit */ 0); 1239 INTREN(1 << apic_8254_intr); 1240 1241#else /* APIC_IO */ 1242 1243 register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, 1244 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1245 /* unit */ 0); 1246 INTREN(IRQ0); 1247 1248#endif /* APIC_IO */ 1249 1250#ifndef PC98 1251 /* Initialize RTC. */ 1252 writertc(RTC_STATUSA, rtc_statusa); 1253 writertc(RTC_STATUSB, RTCSB_24HR); 1254 1255 /* Don't bother enabling the statistics clock. */ 1256 if (statclock_disable) 1257 return; 1258 diag = rtcin(RTC_DIAG); 1259 if (diag != 0) 1260 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1261 1262#ifdef APIC_IO 1263 if (isa_apic_pin(8) != 8) 1264 panic("APIC RTC != 8"); 1265#endif /* APIC_IO */ 1266 1267 register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, 1268 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1269 /* unit */ 0); 1270 1271#ifdef APIC_IO 1272 INTREN(APIC_IRQ8); 1273#else 1274 INTREN(IRQ8); 1275#endif /* APIC_IO */ 1276 1277 writertc(RTC_STATUSB, rtc_statusb); 1278#endif /* !PC98 */ 1279 1280#ifdef APIC_IO 1281 if (apic_8254_trial) { 1282 1283 printf("APIC_IO: Testing 8254 interrupt delivery\n"); 1284 while (read_intr_count(8) < 6) 1285 ; /* nothing */ 1286 if (read_intr_count(apic_8254_intr) < 3) { 1287 /* 1288 * The MP table is broken. 1289 * The 8254 was not connected to the specified pin 1290 * on the IO APIC. 1291 * Workaround: Limited variant of mixed mode. 1292 */ 1293 INTRDIS(1 << apic_8254_intr); 1294 unregister_intr(apic_8254_intr, 1295 /* XXX */ (inthand2_t *) clkintr); 1296 printf("APIC_IO: Broken MP table detected: " 1297 "8254 is not connected to IO APIC int pin %d\n", 1298 apic_8254_intr); 1299 1300 apic_8254_intr = 0; 1301 setup_8254_mixed_mode(); 1302 register_intr(/* irq */ apic_8254_intr, /* XXX id */ 0, /* flags */ 0, 1303 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1304 /* unit */ 0); 1305 INTREN(1 << apic_8254_intr); 1306 } 1307 1308 } 1309 if (apic_8254_intr) 1310 printf("APIC_IO: routing 8254 via pin %d\n",apic_8254_intr); 1311 else 1312 printf("APIC_IO: routing 8254 via 8259 on pin 0\n"); 1313#endif 1314 1315} 1316 1317#ifdef APIC_IO 1318static u_long 1319read_intr_count(int vec) 1320{ 1321 u_long *up; 1322 up = intr_countp[vec]; 1323 if (up) 1324 return *up; 1325 return 0UL; 1326} 1327 1328static void 1329setup_8254_mixed_mode() 1330{ 1331 /* 1332 * Allow 8254 timer to INTerrupt 8259: 1333 * re-initialize master 8259: 1334 * reset; prog 4 bytes, single ICU, edge triggered 1335 */ 1336 outb(IO_ICU1, 0x13); 1337#ifdef PC98 1338 outb(IO_ICU1 + 2, NRSVIDT); /* start vector (unused) */ 1339 outb(IO_ICU1 + 2, 0x00); /* ignore slave */ 1340 outb(IO_ICU1 + 2, 0x03); /* auto EOI, 8086 */ 1341 outb(IO_ICU1 + 2, 0xfe); /* unmask INT0 */ 1342#else 1343 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */ 1344 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1345 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1346 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1347#endif 1348 /* program IO APIC for type 3 INT on INT0 */ 1349 if (ext_int_setup(0, 0) < 0) 1350 panic("8254 redirect via APIC pin0 impossible!"); 1351} 1352#endif 1353 1354void 1355setstatclockrate(int newhz) 1356{ 1357#ifndef PC98 1358 if (newhz == RTC_PROFRATE) 1359 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1360 else 1361 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1362 writertc(RTC_STATUSA, rtc_statusa); 1363#endif 1364} 1365 1366static int 1367sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1368{ 1369 int error; 1370 u_int freq; 1371 1372 /* 1373 * Use `i8254' instead of `timer' in external names because `timer' 1374 * is is too generic. Should use it everywhere. 1375 */ 1376 freq = timer_freq; 1377 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1378 if (error == 0 && req->newptr != NULL) { 1379 if (timer0_state != RELEASED) 1380 return (EBUSY); /* too much trouble to handle */ 1381 set_timer_freq(freq, hz); 1382 i8254_timecounter[0].frequency = freq; 1383 } 1384 return (error); 1385} 1386 1387SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1388 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1389 1390static int 1391sysctl_machdep_tsc_freq SYSCTL_HANDLER_ARGS 1392{ 1393 int error; 1394 u_int freq; 1395 1396 if (!tsc_present) 1397 return (EOPNOTSUPP); 1398 freq = tsc_freq; 1399 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1400 if (error == 0 && req->newptr != NULL) { 1401 tsc_freq = freq; 1402 tsc_timecounter[0].frequency = tsc_freq; 1403 } 1404 return (error); 1405} 1406 1407SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW, 1408 0, sizeof(u_int), sysctl_machdep_tsc_freq, "I", ""); 1409 1410static u_int 1411i8254_get_timecount(void) 1412{ 1413 u_int count; 1414 u_long ef; 1415 u_int high, low; 1416 1417 ef = read_eflags(); 1418 disable_intr(); 1419 1420 /* Select timer0 and latch counter value. */ 1421 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 1422 1423 low = inb(TIMER_CNTR0); 1424 high = inb(TIMER_CNTR0); 1425 1426 count = hardclock_max_count - ((high << 8) | low); 1427 if (count < i8254_lastcount) { 1428 i8254_ticked = 1; 1429 i8254_offset += hardclock_max_count; 1430 } 1431 1432 i8254_lastcount = count; 1433 count += i8254_offset; 1434 CLOCK_UNLOCK(); 1435 write_eflags(ef); 1436 return (count); 1437} 1438 1439static u_int 1440tsc_get_timecount(void) 1441{ 1442 return (rdtsc()); 1443} 1444