pcrtc.c revision 34594
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $Id: clock.c,v 1.48 1998/03/07 15:43:43 kato Exp $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51/* 52 * modified for PC98 by Kakefuda 53 */ 54 55#include "opt_clock.h" 56#include "apm.h" 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/time.h> 61#include <sys/kernel.h> 62#ifndef SMP 63#include <sys/lock.h> 64#endif 65#include <sys/sysctl.h> 66 67#include <machine/clock.h> 68#ifdef CLK_CALIBRATION_LOOP 69#include <machine/cons.h> 70#endif 71#include <machine/cputypes.h> 72#include <machine/frame.h> 73#include <machine/ipl.h> 74#include <machine/limits.h> 75#include <machine/md_var.h> 76#ifdef APIC_IO 77#include <machine/segments.h> 78#endif 79#if defined(SMP) || defined(APIC_IO) 80#include <machine/smp.h> 81#endif /* SMP || APIC_IO */ 82#include <machine/specialreg.h> 83 84#include <i386/isa/icu.h> 85#ifdef PC98 86#include <pc98/pc98/pc98.h> 87#include <pc98/pc98/pc98_machdep.h> 88#include <i386/isa/isa_device.h> 89#else 90#include <i386/isa/isa.h> 91#include <i386/isa/rtc.h> 92#endif 93#include <i386/isa/timerreg.h> 94 95#include <sys/interrupt.h> 96 97#ifdef SMP 98#define disable_intr() CLOCK_DISABLE_INTR() 99#define enable_intr() CLOCK_ENABLE_INTR() 100 101#ifdef APIC_IO 102#include <i386/isa/intr_machdep.h> 103/* The interrupt triggered by the 8254 (timer) chip */ 104int apic_8254_intr; 105static u_long read_intr_count __P((int vec)); 106static void setup_8254_mixed_mode __P((void)); 107#endif 108#endif /* SMP */ 109 110/* 111 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 112 * can use a simple formula for leap years. 113 */ 114#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 115#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 116 117#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 118 119/* 120 * Time in timer cycles that it takes for microtime() to disable interrupts 121 * and latch the count. microtime() currently uses "cli; outb ..." so it 122 * normally takes less than 2 timer cycles. Add a few for cache misses. 123 * Add a few more to allow for latency in bogus calls to microtime() with 124 * interrupts already disabled. 125 */ 126#define TIMER0_LATCH_COUNT 20 127 128/* 129 * Maximum frequency that we are willing to allow for timer0. Must be 130 * low enough to guarantee that the timer interrupt handler returns 131 * before the next timer interrupt. 132 */ 133#define TIMER0_MAX_FREQ 20000 134 135int adjkerntz; /* local offset from GMT in seconds */ 136int disable_rtc_set; /* disable resettodr() if != 0 */ 137u_int idelayed; 138int statclock_disable; 139u_int stat_imask = SWI_CLOCK_MASK; 140#ifndef TIMER_FREQ 141#ifdef PC98 142#ifndef AUTO_CLOCK 143#ifndef PC98_8M 144#define TIMER_FREQ 2457600; 145#else /* !PC98_8M */ 146#define TIMER_FREQ 1996800; 147#endif /* PC98_8M */ 148#else /* AUTO_CLOCK */ 149#define TIMER_FREQ 2457600; 150#endif /* AUTO_CLOCK */ 151#else /* IBM-PC */ 152#define TIMER_FREQ 1193182; 153#endif /* PC98 */ 154#endif 155u_int timer_freq = TIMER_FREQ; 156int timer0_max_count; 157u_int tsc_freq; 158int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 159 160static int beeping = 0; 161static u_int clk_imask = HWI_MASK | SWI_MASK; 162static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 163static u_int hardclock_max_count; 164static u_int32_t i8254_lastcount; 165static u_int32_t i8254_offset; 166static int i8254_ticked; 167/* 168 * XXX new_function and timer_func should not handle clockframes, but 169 * timer_func currently needs to hold hardclock to handle the 170 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 171 * to switch between clkintr() and a slightly different timerintr(). 172 */ 173static void (*new_function) __P((struct clockframe *frame)); 174static u_int new_rate; 175#ifndef PC98 176static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 177static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 178#endif 179static u_int timer0_prescaler_count; 180 181/* Values for timerX_state: */ 182#define RELEASED 0 183#define RELEASE_PENDING 1 184#define ACQUIRED 2 185#define ACQUIRE_PENDING 3 186 187static u_char timer0_state; 188#ifdef PC98 189static u_char timer1_state; 190#endif 191static u_char timer2_state; 192static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 193#ifdef PC98 194static void rtc_serialcombit __P((int)); 195static void rtc_serialcom __P((int)); 196static int rtc_inb __P((void)); 197static void rtc_outb __P((int)); 198#endif 199static u_int tsc_present; 200 201static u_int64_t i8254_get_timecount __P((void)); 202static void set_timer_freq(u_int freq, int intr_freq); 203static u_int64_t tsc_get_timecount __P((void)); 204static u_int32_t tsc_get_timedelta __P((struct timecounter *tc)); 205 206static struct timecounter tsc_timecounter[3] = { 207 tsc_get_timedelta, /* get_timedelta */ 208 tsc_get_timecount, /* get_timecount */ 209 ~0, /* counter_mask */ 210 0, /* frequency */ 211 "TSC" /* name */ 212}; 213 214SYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD, 215 tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", ""); 216 217static struct timecounter i8254_timecounter[3] = { 218 0, /* get_timedelta */ 219 i8254_get_timecount, /* get_timecount */ 220 (1ULL << 32) - 1, /* counter_mask */ 221 0, /* frequency */ 222 "i8254" /* name */ 223}; 224 225SYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD, 226 i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", ""); 227 228static void 229clkintr(struct clockframe frame) 230{ 231 if (!i8254_ticked) 232 i8254_offset += timer0_max_count; 233 else 234 i8254_ticked = 0; 235 i8254_lastcount = 0; 236 timer_func(&frame); 237 switch (timer0_state) { 238 239 case RELEASED: 240 setdelayed(); 241 break; 242 243 case ACQUIRED: 244 if ((timer0_prescaler_count += timer0_max_count) 245 >= hardclock_max_count) { 246 timer0_prescaler_count -= hardclock_max_count; 247 hardclock(&frame); 248 setdelayed(); 249 } 250 break; 251 252 case ACQUIRE_PENDING: 253 setdelayed(); 254 timer0_max_count = TIMER_DIV(new_rate); 255 disable_intr(); 256 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 257 outb(TIMER_CNTR0, timer0_max_count & 0xff); 258 outb(TIMER_CNTR0, timer0_max_count >> 8); 259 enable_intr(); 260 timer0_prescaler_count = 0; 261 timer_func = new_function; 262 timer0_state = ACQUIRED; 263 break; 264 265 case RELEASE_PENDING: 266 if ((timer0_prescaler_count += timer0_max_count) 267 >= hardclock_max_count) { 268 timer0_prescaler_count -= hardclock_max_count; 269 /* 270 * See microtime.s for this magic. 271 */ 272#ifdef PC98 273#ifndef AUTO_CLOCK 274#ifndef PC98_8M 275 time.tv_usec += (6667 * timer0_prescaler_count) >> 14; 276#else /* PC98_8M */ 277 time.tv_usec += (16411 * timer0_prescaler_count) >> 15; 278#endif /* PC98_8M */ 279#else /* AUTO_CLOCK */ 280 if (pc98_machine_type & M_8M) { 281 /* PC98_8M */ 282 time.tv_usec += (16411 * timer0_prescaler_count) >> 15; 283 } else { 284 time.tv_usec += (6667 * timer0_prescaler_count) >> 14; 285 } 286#endif /* AUTO_CLOCK */ 287#else /* IBM-PC */ 288 time.tv_usec += (27465 * timer0_prescaler_count) >> 15; 289#endif 290 if (time.tv_usec >= 1000000) 291 time.tv_usec -= 1000000; 292 hardclock(&frame); 293 setdelayed(); 294 timer0_max_count = hardclock_max_count; 295 disable_intr(); 296 outb(TIMER_MODE, 297 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 298 outb(TIMER_CNTR0, timer0_max_count & 0xff); 299 outb(TIMER_CNTR0, timer0_max_count >> 8); 300 enable_intr(); 301 timer0_prescaler_count = 0; 302 timer_func = hardclock; 303 timer0_state = RELEASED; 304 } 305 break; 306 } 307} 308 309/* 310 * The acquire and release functions must be called at ipl >= splclock(). 311 */ 312int 313acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 314{ 315 static int old_rate; 316 317 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 318 return (-1); 319 if (strcmp(timecounter->name, "i8254") == 0) 320 return (-1); 321 switch (timer0_state) { 322 323 case RELEASED: 324 timer0_state = ACQUIRE_PENDING; 325 break; 326 327 case RELEASE_PENDING: 328 if (rate != old_rate) 329 return (-1); 330 /* 331 * The timer has been released recently, but is being 332 * re-acquired before the release completed. In this 333 * case, we simply reclaim it as if it had not been 334 * released at all. 335 */ 336 timer0_state = ACQUIRED; 337 break; 338 339 default: 340 return (-1); /* busy */ 341 } 342 new_function = function; 343 old_rate = new_rate = rate; 344 return (0); 345} 346 347#ifdef PC98 348int 349acquire_timer1(int mode) 350{ 351 352 if (timer1_state != RELEASED) 353 return (-1); 354 timer1_state = ACQUIRED; 355 356 /* 357 * This access to the timer registers is as atomic as possible 358 * because it is a single instruction. We could do better if we 359 * knew the rate. Use of splclock() limits glitches to 10-100us, 360 * and this is probably good enough for timer2, so we aren't as 361 * careful with it as with timer0. 362 */ 363 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 364 365 return (0); 366} 367#endif 368 369int 370acquire_timer2(int mode) 371{ 372 373 if (timer2_state != RELEASED) 374 return (-1); 375 timer2_state = ACQUIRED; 376 377 /* 378 * This access to the timer registers is as atomic as possible 379 * because it is a single instruction. We could do better if we 380 * knew the rate. Use of splclock() limits glitches to 10-100us, 381 * and this is probably good enough for timer2, so we aren't as 382 * careful with it as with timer0. 383 */ 384 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 385 386 return (0); 387} 388 389int 390release_timer0() 391{ 392 switch (timer0_state) { 393 394 case ACQUIRED: 395 timer0_state = RELEASE_PENDING; 396 break; 397 398 case ACQUIRE_PENDING: 399 /* Nothing happened yet, release quickly. */ 400 timer0_state = RELEASED; 401 break; 402 403 default: 404 return (-1); 405 } 406 return (0); 407} 408 409#ifdef PC98 410int 411release_timer1() 412{ 413 414 if (timer1_state != ACQUIRED) 415 return (-1); 416 timer1_state = RELEASED; 417 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 418 return (0); 419} 420#endif 421 422int 423release_timer2() 424{ 425 426 if (timer2_state != ACQUIRED) 427 return (-1); 428 timer2_state = RELEASED; 429 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 430 return (0); 431} 432 433#ifndef PC98 434/* 435 * This routine receives statistical clock interrupts from the RTC. 436 * As explained above, these occur at 128 interrupts per second. 437 * When profiling, we receive interrupts at a rate of 1024 Hz. 438 * 439 * This does not actually add as much overhead as it sounds, because 440 * when the statistical clock is active, the hardclock driver no longer 441 * needs to keep (inaccurate) statistics on its own. This decouples 442 * statistics gathering from scheduling interrupts. 443 * 444 * The RTC chip requires that we read status register C (RTC_INTR) 445 * to acknowledge an interrupt, before it will generate the next one. 446 * Under high interrupt load, rtcintr() can be indefinitely delayed and 447 * the clock can tick immediately after the read from RTC_INTR. In this 448 * case, the mc146818A interrupt signal will not drop for long enough 449 * to register with the 8259 PIC. If an interrupt is missed, the stat 450 * clock will halt, considerably degrading system performance. This is 451 * why we use 'while' rather than a more straightforward 'if' below. 452 * Stat clock ticks can still be lost, causing minor loss of accuracy 453 * in the statistics, but the stat clock will no longer stop. 454 */ 455static void 456rtcintr(struct clockframe frame) 457{ 458 while (rtcin(RTC_INTR) & RTCIR_PERIOD) 459 statclock(&frame); 460} 461 462#include "opt_ddb.h" 463#ifdef DDB 464#include <ddb/ddb.h> 465 466DB_SHOW_COMMAND(rtc, rtc) 467{ 468 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 469 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 470 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 471 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 472} 473#endif /* DDB */ 474#endif /* for PC98 */ 475 476static int 477getit(void) 478{ 479 u_long ef; 480 int high, low; 481 482 ef = read_eflags(); 483 disable_intr(); 484 485 /* Select timer0 and latch counter value. */ 486 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 487 488 low = inb(TIMER_CNTR0); 489 high = inb(TIMER_CNTR0); 490 491 CLOCK_UNLOCK(); 492 write_eflags(ef); 493 return ((high << 8) | low); 494} 495 496/* 497 * Wait "n" microseconds. 498 * Relies on timer 1 counting down from (timer_freq / hz) 499 * Note: timer had better have been programmed before this is first used! 500 */ 501void 502DELAY(int n) 503{ 504 int delta, prev_tick, tick, ticks_left; 505 506#ifdef DELAYDEBUG 507 int getit_calls = 1; 508 int n1; 509 static int state = 0; 510 511 if (state == 0) { 512 state = 1; 513 for (n1 = 1; n1 <= 10000000; n1 *= 10) 514 DELAY(n1); 515 state = 2; 516 } 517 if (state == 1) 518 printf("DELAY(%d)...", n); 519#endif 520 /* 521 * Guard against the timer being uninitialized if we are called 522 * early for console i/o. 523 */ 524 if (timer0_max_count == 0) 525 set_timer_freq(timer_freq, hz); 526 527 /* 528 * Read the counter first, so that the rest of the setup overhead is 529 * counted. Guess the initial overhead is 20 usec (on most systems it 530 * takes about 1.5 usec for each of the i/o's in getit(). The loop 531 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 532 * multiplications and divisions to scale the count take a while). 533 */ 534 prev_tick = getit(); 535 n -= 0; /* XXX actually guess no initial overhead */ 536 /* 537 * Calculate (n * (timer_freq / 1e6)) without using floating point 538 * and without any avoidable overflows. 539 */ 540 if (n <= 0) 541 ticks_left = 0; 542 else if (n < 256) 543 /* 544 * Use fixed point to avoid a slow division by 1000000. 545 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 546 * 2^15 is the first power of 2 that gives exact results 547 * for n between 0 and 256. 548 */ 549 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 550 else 551 /* 552 * Don't bother using fixed point, although gcc-2.7.2 553 * generates particularly poor code for the long long 554 * division, since even the slow way will complete long 555 * before the delay is up (unless we're interrupted). 556 */ 557 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 558 / 1000000; 559 560 while (ticks_left > 0) { 561 tick = getit(); 562#ifdef DELAYDEBUG 563 ++getit_calls; 564#endif 565 delta = prev_tick - tick; 566 prev_tick = tick; 567 if (delta < 0) { 568 delta += timer0_max_count; 569 /* 570 * Guard against timer0_max_count being wrong. 571 * This shouldn't happen in normal operation, 572 * but it may happen if set_timer_freq() is 573 * traced. 574 */ 575 if (delta < 0) 576 delta = 0; 577 } 578 ticks_left -= delta; 579 } 580#ifdef DELAYDEBUG 581 if (state == 1) 582 printf(" %d calls to getit() at %d usec each\n", 583 getit_calls, (n + 5) / getit_calls); 584#endif 585} 586 587static void 588sysbeepstop(void *chan) 589{ 590#ifdef PC98 /* PC98 */ 591 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 592 release_timer1(); 593#else 594 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 595 release_timer2(); 596#endif 597 beeping = 0; 598} 599 600int 601sysbeep(int pitch, int period) 602{ 603 int x = splclock(); 604 605#ifdef PC98 606 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 607 if (!beeping) { 608 /* Something else owns it. */ 609 splx(x); 610 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 611 } 612 disable_intr(); 613 outb(0x3fdb, pitch); 614 outb(0x3fdb, (pitch>>8)); 615 enable_intr(); 616 if (!beeping) { 617 /* enable counter1 output to speaker */ 618 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 619 beeping = period; 620 timeout(sysbeepstop, (void *)NULL, period); 621 } 622#else 623 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 624 if (!beeping) { 625 /* Something else owns it. */ 626 splx(x); 627 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 628 } 629 disable_intr(); 630 outb(TIMER_CNTR2, pitch); 631 outb(TIMER_CNTR2, (pitch>>8)); 632 enable_intr(); 633 if (!beeping) { 634 /* enable counter2 output to speaker */ 635 outb(IO_PPI, inb(IO_PPI) | 3); 636 beeping = period; 637 timeout(sysbeepstop, (void *)NULL, period); 638 } 639#endif 640 splx(x); 641 return (0); 642} 643 644#ifndef PC98 645/* 646 * RTC support routines 647 */ 648 649int 650rtcin(reg) 651 int reg; 652{ 653 u_char val; 654 655 outb(IO_RTC, reg); 656 inb(0x84); 657 val = inb(IO_RTC + 1); 658 inb(0x84); 659 return (val); 660} 661 662static __inline void 663writertc(u_char reg, u_char val) 664{ 665 inb(0x84); 666 outb(IO_RTC, reg); 667 inb(0x84); 668 outb(IO_RTC + 1, val); 669 inb(0x84); /* XXX work around wrong order in rtcin() */ 670} 671 672static __inline int 673readrtc(int port) 674{ 675 return(bcd2bin(rtcin(port))); 676} 677#endif 678 679#ifdef PC98 680unsigned int delaycount; 681#define FIRST_GUESS 0x2000 682static void findcpuspeed(void) 683{ 684 int i; 685 int remainder; 686 687 /* Put counter in count down mode */ 688 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 689 outb(TIMER_CNTR0, 0xff); 690 outb(TIMER_CNTR0, 0xff); 691 for (i = FIRST_GUESS; i; i--) 692 ; 693 remainder = getit(); 694 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 695} 696#endif 697 698#ifndef PC98 699static u_int 700calibrate_clocks(void) 701{ 702 u_int count, prev_count, tot_count; 703 int sec, start_sec, timeout; 704 705 if (bootverbose) 706 printf("Calibrating clock(s) ... "); 707 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 708 goto fail; 709 timeout = 100000000; 710 711 /* Read the mc146818A seconds counter. */ 712 for (;;) { 713 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 714 sec = rtcin(RTC_SEC); 715 break; 716 } 717 if (--timeout == 0) 718 goto fail; 719 } 720 721 /* Wait for the mC146818A seconds counter to change. */ 722 start_sec = sec; 723 for (;;) { 724 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 725 sec = rtcin(RTC_SEC); 726 if (sec != start_sec) 727 break; 728 } 729 if (--timeout == 0) 730 goto fail; 731 } 732 733 /* Start keeping track of the i8254 counter. */ 734 prev_count = getit(); 735 if (prev_count == 0 || prev_count > timer0_max_count) 736 goto fail; 737 tot_count = 0; 738 739 if (tsc_present) 740 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 741 742 /* 743 * Wait for the mc146818A seconds counter to change. Read the i8254 744 * counter for each iteration since this is convenient and only 745 * costs a few usec of inaccuracy. The timing of the final reads 746 * of the counters almost matches the timing of the initial reads, 747 * so the main cause of inaccuracy is the varying latency from 748 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 749 * rtcin(RTC_SEC) that returns a changed seconds count. The 750 * maximum inaccuracy from this cause is < 10 usec on 486's. 751 */ 752 start_sec = sec; 753 for (;;) { 754 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 755 sec = rtcin(RTC_SEC); 756 count = getit(); 757 if (count == 0 || count > timer0_max_count) 758 goto fail; 759 if (count > prev_count) 760 tot_count += prev_count - (count - timer0_max_count); 761 else 762 tot_count += prev_count - count; 763 prev_count = count; 764 if (sec != start_sec) 765 break; 766 if (--timeout == 0) 767 goto fail; 768 } 769 770 /* 771 * Read the cpu cycle counter. The timing considerations are 772 * similar to those for the i8254 clock. 773 */ 774 if (tsc_present) 775 tsc_freq = rdtsc(); 776 777 if (bootverbose) { 778 if (tsc_present) 779 printf("TSC clock: %u Hz, ", tsc_freq); 780 printf("i8254 clock: %u Hz\n", tot_count); 781 } 782 return (tot_count); 783 784fail: 785 if (bootverbose) 786 printf("failed, using default i8254 clock of %u Hz\n", 787 timer_freq); 788 return (timer_freq); 789} 790#endif /* !PC98 */ 791 792static void 793set_timer_freq(u_int freq, int intr_freq) 794{ 795 u_long ef; 796 int new_timer0_max_count; 797 798 ef = read_eflags(); 799 disable_intr(); 800 timer_freq = freq; 801 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 802 if (new_timer0_max_count != timer0_max_count) { 803 timer0_max_count = new_timer0_max_count; 804 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 805 outb(TIMER_CNTR0, timer0_max_count & 0xff); 806 outb(TIMER_CNTR0, timer0_max_count >> 8); 807 } 808 CLOCK_UNLOCK(); 809 write_eflags(ef); 810} 811 812/* 813 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 814 * XXX initialization of other timers is unintentionally left blank. 815 */ 816void 817startrtclock() 818{ 819 u_int delta, freq; 820 821#ifdef PC98 822 findcpuspeed(); 823#ifndef AUTO_CLOCK 824 if (pc98_machine_type & M_8M) { 825#ifndef PC98_8M 826 printf("you must reconfig a kernel with \"PC98_8M\" option.\n"); 827#endif 828 } else { 829#ifdef PC98_8M 830 printf("You must reconfig a kernel without \"PC98_8M\" option.\n"); 831#endif 832 } 833#else /* AUTO_CLOCK */ 834 if (pc98_machine_type & M_8M) 835 timer_freq = 1996800L; /* 1.9968 MHz */ 836 else 837 timer_freq = 2457600L; /* 2.4576 MHz */ 838#endif /* AUTO_CLOCK */ 839#endif /* PC98 */ 840 841 if (cpu_feature & CPUID_TSC) 842 tsc_present = 1; 843 else 844 tsc_present = 0; 845 846#ifdef SMP 847 tsc_present = 0; 848#endif 849#if NAPM > 0 850 tsc_present = 0; 851#endif 852 853#ifndef PC98 854 writertc(RTC_STATUSA, rtc_statusa); 855 writertc(RTC_STATUSB, RTCSB_24HR); 856#endif 857 858#ifndef PC98 859 set_timer_freq(timer_freq, hz); 860 freq = calibrate_clocks(); 861#ifdef CLK_CALIBRATION_LOOP 862 if (bootverbose) { 863 printf( 864 "Press a key on the console to abort clock calibration\n"); 865 while (cncheckc() == -1) 866 calibrate_clocks(); 867 } 868#endif 869 870 /* 871 * Use the calibrated i8254 frequency if it seems reasonable. 872 * Otherwise use the default, and don't use the calibrated i586 873 * frequency. 874 */ 875 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 876 if (delta < timer_freq / 100) { 877#ifndef CLK_USE_I8254_CALIBRATION 878 if (bootverbose) 879 printf( 880"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 881 freq = timer_freq; 882#endif 883 timer_freq = freq; 884 } else { 885 if (bootverbose) 886 printf( 887 "%d Hz differs from default of %d Hz by more than 1%%\n", 888 freq, timer_freq); 889 tsc_freq = 0; 890 } 891#endif 892 893 set_timer_freq(timer_freq, hz); 894 i8254_timecounter[0].frequency = timer_freq; 895 init_timecounter(i8254_timecounter); 896 897#ifndef CLK_USE_TSC_CALIBRATION 898 if (tsc_freq != 0) { 899 if (bootverbose) 900 printf( 901"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 902 tsc_freq = 0; 903 } 904#endif 905 if (tsc_present && tsc_freq == 0) { 906 /* 907 * Calibration of the i586 clock relative to the mc146818A 908 * clock failed. Do a less accurate calibration relative 909 * to the i8254 clock. 910 */ 911 wrmsr(0x10, 0LL); /* XXX */ 912 DELAY(1000000); 913 tsc_freq = rdtsc(); 914#ifdef CLK_USE_TSC_CALIBRATION 915 if (bootverbose) 916 printf("TSC clock: %u Hz (Method B)\n", tsc_freq); 917#endif 918 } 919 if (tsc_present && tsc_freq != 0) { 920 tsc_timecounter[0].frequency = tsc_freq; 921 init_timecounter(tsc_timecounter); 922 } 923} 924 925#ifdef PC98 926static void 927rtc_serialcombit(int i) 928{ 929 outb(IO_RTC, ((i&0x01)<<5)|0x07); 930 DELAY(1); 931 outb(IO_RTC, ((i&0x01)<<5)|0x17); 932 DELAY(1); 933 outb(IO_RTC, ((i&0x01)<<5)|0x07); 934 DELAY(1); 935} 936 937static void 938rtc_serialcom(int i) 939{ 940 rtc_serialcombit(i&0x01); 941 rtc_serialcombit((i&0x02)>>1); 942 rtc_serialcombit((i&0x04)>>2); 943 rtc_serialcombit((i&0x08)>>3); 944 outb(IO_RTC, 0x07); 945 DELAY(1); 946 outb(IO_RTC, 0x0f); 947 DELAY(1); 948 outb(IO_RTC, 0x07); 949 DELAY(1); 950} 951 952static void 953rtc_outb(int val) 954{ 955 int s; 956 int sa = 0; 957 958 for (s=0;s<8;s++) { 959 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 960 outb(IO_RTC, sa); /* set DI & CLK 0 */ 961 DELAY(1); 962 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 963 DELAY(1); 964 } 965 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 966} 967 968static int 969rtc_inb(void) 970{ 971 int s; 972 int sa = 0; 973 974 for (s=0;s<8;s++) { 975 sa |= ((inb(0x33) & 0x01) << s); 976 outb(IO_RTC, 0x17); /* CLK 1 */ 977 DELAY(1); 978 outb(IO_RTC, 0x07); /* CLK 0 */ 979 DELAY(2); 980 } 981 return sa; 982} 983#endif /* PC-98 */ 984 985/* 986 * Initialize the time of day register, based on the time base which is, e.g. 987 * from a filesystem. 988 */ 989void 990inittodr(time_t base) 991{ 992 unsigned long sec, days; 993 int yd; 994 int year, month; 995 int y, m, s; 996 struct timespec ts; 997#ifdef PC98 998 int second, min, hour; 999#endif 1000 1001 if (base) { 1002 s = splclock(); 1003 ts.tv_sec = base; 1004 ts.tv_nsec = 0; 1005 set_timecounter(&ts); 1006 splx(s); 1007 } 1008 1009#ifdef PC98 1010 rtc_serialcom(0x03); /* Time Read */ 1011 rtc_serialcom(0x01); /* Register shift command. */ 1012 DELAY(20); 1013 1014 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 1015 min = bcd2bin(rtc_inb() & 0xff); /* min */ 1016 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 1017 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 1018 1019 month = (rtc_inb() >> 4) & 0x0f; /* month */ 1020 for (m = 1; m < month; m++) 1021 days += daysinmonth[m-1]; 1022 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 1023 /* 2000 year problem */ 1024 if (year < 1995) 1025 year += 100; 1026 if (year < 1970) 1027 goto wrong_time; 1028 for (y = 1970; y < year; y++) 1029 days += DAYSPERYEAR + LEAPYEAR(y); 1030 if ((month > 2) && LEAPYEAR(year)) 1031 days ++; 1032 sec = ((( days * 24 + 1033 hour) * 60 + 1034 min) * 60 + 1035 second); 1036 /* sec now contains the number of seconds, since Jan 1 1970, 1037 in the local time zone */ 1038#else /* IBM-PC */ 1039 /* Look if we have a RTC present and the time is valid */ 1040 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 1041 goto wrong_time; 1042 1043 /* wait for time update to complete */ 1044 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 1045 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 1046 1047 days = 0; 1048#ifdef USE_RTC_CENTURY 1049 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 1050#else 1051 year = readrtc(RTC_YEAR) + 1900; 1052 if (year < 1970) 1053 year += 100; 1054#endif 1055 if (year < 1970) 1056 goto wrong_time; 1057 month = readrtc(RTC_MONTH); 1058 for (m = 1; m < month; m++) 1059 days += daysinmonth[m-1]; 1060 if ((month > 2) && LEAPYEAR(year)) 1061 days ++; 1062 days += readrtc(RTC_DAY) - 1; 1063 yd = days; 1064 for (y = 1970; y < year; y++) 1065 days += DAYSPERYEAR + LEAPYEAR(y); 1066 sec = ((( days * 24 + 1067 readrtc(RTC_HRS)) * 60 + 1068 readrtc(RTC_MIN)) * 60 + 1069 readrtc(RTC_SEC)); 1070 /* sec now contains the number of seconds, since Jan 1 1970, 1071 in the local time zone */ 1072#endif 1073 1074 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1075 1076 y = time.tv_sec - sec; 1077 if (y <= -2 || y >= 2) { 1078 /* badly off, adjust it */ 1079 s = splclock(); 1080 ts.tv_sec = sec; 1081 ts.tv_nsec = 0; 1082 set_timecounter(&ts); 1083 splx(s); 1084 } 1085 return; 1086 1087wrong_time: 1088 printf("Invalid time in real time clock.\n"); 1089 printf("Check and reset the date immediately!\n"); 1090} 1091 1092/* 1093 * Write system time back to RTC 1094 */ 1095void 1096resettodr() 1097{ 1098 unsigned long tm; 1099 int y, m, s; 1100#ifdef PC98 1101 int wd; 1102#endif 1103 1104 if (disable_rtc_set) 1105 return; 1106 1107 s = splclock(); 1108 tm = time.tv_sec; 1109 splx(s); 1110 1111#ifdef PC98 1112 rtc_serialcom(0x01); /* Register shift command. */ 1113 1114 /* Calculate local time to put in RTC */ 1115 1116 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1117 1118 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1119 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1120 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1121 1122 /* We have now the days since 01-01-1970 in tm */ 1123 wd = (tm+4)%7; 1124 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1125 tm >= m; 1126 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1127 tm -= m; 1128 1129 /* Now we have the years in y and the day-of-the-year in tm */ 1130 for (m = 0; ; m++) { 1131 int ml; 1132 1133 ml = daysinmonth[m]; 1134 if (m == 1 && LEAPYEAR(y)) 1135 ml++; 1136 if (tm < ml) 1137 break; 1138 tm -= ml; 1139 } 1140 1141 m++; 1142 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1143 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1144 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1145 1146 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1147 rtc_serialcom(0x00); /* Register hold command. */ 1148#else 1149 /* Disable RTC updates and interrupts. */ 1150 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1151 1152 /* Calculate local time to put in RTC */ 1153 1154 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1155 1156 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1157 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1158 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1159 1160 /* We have now the days since 01-01-1970 in tm */ 1161 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1162 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1163 tm >= m; 1164 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1165 tm -= m; 1166 1167 /* Now we have the years in y and the day-of-the-year in tm */ 1168 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1169#ifdef USE_RTC_CENTURY 1170 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1171#endif 1172 for (m = 0; ; m++) { 1173 int ml; 1174 1175 ml = daysinmonth[m]; 1176 if (m == 1 && LEAPYEAR(y)) 1177 ml++; 1178 if (tm < ml) 1179 break; 1180 tm -= ml; 1181 } 1182 1183 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1184 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1185 1186 /* Reenable RTC updates and interrupts. */ 1187 writertc(RTC_STATUSB, rtc_statusb); 1188#endif 1189} 1190 1191 1192/* 1193 * Start both clocks running. 1194 */ 1195void 1196cpu_initclocks() 1197{ 1198#ifdef APIC_IO 1199 int apic_8254_trial; 1200#endif /* APIC_IO */ 1201#ifndef PC98 1202 int diag; 1203 1204 if (statclock_disable) { 1205 /* 1206 * The stat interrupt mask is different without the 1207 * statistics clock. Also, don't set the interrupt 1208 * flag which would normally cause the RTC to generate 1209 * interrupts. 1210 */ 1211 stat_imask = HWI_MASK | SWI_MASK; 1212 rtc_statusb = RTCSB_24HR; 1213 } else { 1214 /* Setting stathz to nonzero early helps avoid races. */ 1215 stathz = RTC_NOPROFRATE; 1216 profhz = RTC_PROFRATE; 1217 } 1218#endif 1219 1220 /* Finish initializing 8253 timer 0. */ 1221#ifdef APIC_IO 1222 1223 apic_8254_intr = isa_apic_pin(0); 1224 apic_8254_trial = 0; 1225 if (apic_8254_intr >= 0 ) { 1226 if (apic_int_type(0, 0) == 3) 1227 apic_8254_trial = 1; 1228 } else { 1229 /* look for ExtInt on pin 0 */ 1230 if (apic_int_type(0, 0) == 3) { 1231 apic_8254_intr = 0; 1232 setup_8254_mixed_mode(); 1233 } else 1234 panic("APIC_IO: Cannot route 8254 interrupt to CPU"); 1235 } 1236 1237 register_intr(/* irq */ apic_8254_intr, /* XXX id */ 0, /* flags */ 0, 1238 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1239 /* unit */ 0); 1240 INTREN(1 << apic_8254_intr); 1241 1242#else /* APIC_IO */ 1243 1244 register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, 1245 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1246 /* unit */ 0); 1247 INTREN(IRQ0); 1248 1249#endif /* APIC_IO */ 1250 1251#ifndef PC98 1252 /* Initialize RTC. */ 1253 writertc(RTC_STATUSA, rtc_statusa); 1254 writertc(RTC_STATUSB, RTCSB_24HR); 1255 1256 /* Don't bother enabling the statistics clock. */ 1257 if (statclock_disable) 1258 return; 1259 diag = rtcin(RTC_DIAG); 1260 if (diag != 0) 1261 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1262 1263#ifdef APIC_IO 1264 if (isa_apic_pin(8) != 8) 1265 panic("APIC RTC != 8"); 1266#endif /* APIC_IO */ 1267 1268 register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, 1269 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1270 /* unit */ 0); 1271 1272#ifdef APIC_IO 1273 INTREN(APIC_IRQ8); 1274#else 1275 INTREN(IRQ8); 1276#endif /* APIC_IO */ 1277 1278 writertc(RTC_STATUSB, rtc_statusb); 1279#endif /* !PC98 */ 1280 1281#ifdef APIC_IO 1282 if (apic_8254_trial) { 1283 1284 printf("APIC_IO: Testing 8254 interrupt delivery\n"); 1285 __asm __volatile("sti" : : : "memory"); 1286 while (read_intr_count(8) < 6) 1287 __asm __volatile("sti" : : : "memory"); 1288 if (read_intr_count(apic_8254_intr) < 3) { 1289 /* 1290 * The MP table is broken. 1291 * The 8254 was not connected to the specified pin 1292 * on the IO APIC. 1293 * Workaround: Limited variant of mixed mode. 1294 */ 1295 INTRDIS(1 << apic_8254_intr); 1296 unregister_intr(apic_8254_intr, 1297 /* XXX */ (inthand2_t *) clkintr); 1298 printf("APIC_IO: Broken MP table detected: " 1299 "8254 is not connected to IO APIC int pin %d\n", 1300 apic_8254_intr); 1301 1302 apic_8254_intr = 0; 1303 setup_8254_mixed_mode(); 1304 register_intr(/* irq */ apic_8254_intr, /* XXX id */ 0, /* flags */ 0, 1305 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1306 /* unit */ 0); 1307 INTREN(1 << apic_8254_intr); 1308 } 1309 1310 } 1311 if (apic_8254_intr) 1312 printf("APIC_IO: routing 8254 via pin %d\n",apic_8254_intr); 1313 else 1314 printf("APIC_IO: routing 8254 via 8259 on pin 0\n"); 1315#endif 1316 1317} 1318 1319#ifdef APIC_IO 1320static u_long 1321read_intr_count(int vec) 1322{ 1323 u_long *up; 1324 up = intr_countp[vec]; 1325 if (up) 1326 return *up; 1327 return 0UL; 1328} 1329 1330static void 1331setup_8254_mixed_mode() 1332{ 1333 /* 1334 * Allow 8254 timer to INTerrupt 8259: 1335 * re-initialize master 8259: 1336 * reset; prog 4 bytes, single ICU, edge triggered 1337 */ 1338 outb(IO_ICU1, 0x13); 1339#ifdef PC98 1340 outb(IO_ICU1 + 2, NRSVIDT); /* start vector (unused) */ 1341 outb(IO_ICU1 + 2, 0x00); /* ignore slave */ 1342 outb(IO_ICU1 + 2, 0x03); /* auto EOI, 8086 */ 1343 outb(IO_ICU1 + 2, 0xfe); /* unmask INT0 */ 1344#else 1345 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */ 1346 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1347 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1348 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1349#endif 1350 /* program IO APIC for type 3 INT on INT0 */ 1351 if (ext_int_setup(0, 0) < 0) 1352 panic("8254 redirect via APIC pin0 impossible!"); 1353} 1354#endif 1355 1356void 1357setstatclockrate(int newhz) 1358{ 1359#ifndef PC98 1360 if (newhz == RTC_PROFRATE) 1361 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1362 else 1363 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1364 writertc(RTC_STATUSA, rtc_statusa); 1365#endif 1366} 1367 1368static int 1369sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1370{ 1371 int error; 1372 u_int freq; 1373 1374 /* 1375 * Use `i8254' instead of `timer' in external names because `timer' 1376 * is is too generic. Should use it everywhere. 1377 */ 1378 freq = timer_freq; 1379 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1380 if (error == 0 && req->newptr != NULL) { 1381 if (timer0_state != RELEASED) 1382 return (EBUSY); /* too much trouble to handle */ 1383 set_timer_freq(freq, hz); 1384 i8254_timecounter[0].frequency = freq; 1385 } 1386 return (error); 1387} 1388 1389SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1390 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1391 1392static int 1393sysctl_machdep_tsc_freq SYSCTL_HANDLER_ARGS 1394{ 1395 int error; 1396 u_int freq; 1397 1398 if (!tsc_present) 1399 return (EOPNOTSUPP); 1400 freq = tsc_freq; 1401 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1402 if (error == 0 && req->newptr != NULL) { 1403 tsc_freq = freq; 1404 tsc_timecounter[0].frequency = tsc_freq; 1405 } 1406 return (error); 1407} 1408 1409SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW, 1410 0, sizeof(u_int), sysctl_machdep_tsc_freq, "I", ""); 1411 1412static u_int64_t 1413i8254_get_timecount(void) 1414{ 1415 u_int32_t count; 1416 u_long ef; 1417 u_int high, low; 1418 1419 ef = read_eflags(); 1420 disable_intr(); 1421 1422 /* Select timer0 and latch counter value. */ 1423 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 1424 1425 low = inb(TIMER_CNTR0); 1426 high = inb(TIMER_CNTR0); 1427 1428 count = hardclock_max_count - ((high << 8) | low); 1429 if (count < i8254_lastcount) { 1430 i8254_ticked = 1; 1431 i8254_offset += hardclock_max_count; 1432 } 1433 1434 i8254_lastcount = count; 1435 count += i8254_offset; 1436 CLOCK_UNLOCK(); 1437 write_eflags(ef); 1438 return (count); 1439} 1440 1441static u_int64_t 1442tsc_get_timecount(void) 1443{ 1444 return ((u_int64_t)rdtsc()); 1445} 1446 1447static u_int32_t 1448tsc_get_timedelta(struct timecounter *tc) 1449{ 1450 return ((u_int64_t)rdtsc() - tc->offset_count); 1451} 1452