pcrtc.c revision 34187
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $Id: clock.c,v 1.47 1998/03/01 05:22:25 kato Exp $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51/* 52 * modified for PC98 by Kakefuda 53 */ 54 55#include "opt_clock.h" 56#include "apm.h" 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/time.h> 61#include <sys/kernel.h> 62#ifndef SMP 63#include <sys/lock.h> 64#endif 65#include <sys/sysctl.h> 66 67#include <machine/clock.h> 68#ifdef CLK_CALIBRATION_LOOP 69#include <machine/cons.h> 70#endif 71#include <machine/cputypes.h> 72#include <machine/frame.h> 73#include <machine/ipl.h> 74#include <machine/limits.h> 75#include <machine/md_var.h> 76#ifdef APIC_IO 77#include <machine/segments.h> 78#endif 79#if defined(SMP) || defined(APIC_IO) 80#include <machine/smp.h> 81#endif /* SMP || APIC_IO */ 82#include <machine/specialreg.h> 83 84#include <i386/isa/icu.h> 85#ifdef PC98 86#include <pc98/pc98/pc98.h> 87#include <pc98/pc98/pc98_machdep.h> 88#include <i386/isa/isa_device.h> 89#else 90#include <i386/isa/isa.h> 91#include <i386/isa/rtc.h> 92#endif 93#include <i386/isa/timerreg.h> 94 95#include <sys/interrupt.h> 96 97#ifdef SMP 98#define disable_intr() CLOCK_DISABLE_INTR() 99#define enable_intr() CLOCK_ENABLE_INTR() 100 101/* The interrupt triggered by the 8254 (timer) chip */ 102int apic_8254_intr; 103#endif /* SMP */ 104 105/* 106 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 107 * can use a simple formula for leap years. 108 */ 109#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 110#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 111 112#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 113 114/* 115 * Time in timer cycles that it takes for microtime() to disable interrupts 116 * and latch the count. microtime() currently uses "cli; outb ..." so it 117 * normally takes less than 2 timer cycles. Add a few for cache misses. 118 * Add a few more to allow for latency in bogus calls to microtime() with 119 * interrupts already disabled. 120 */ 121#define TIMER0_LATCH_COUNT 20 122 123/* 124 * Maximum frequency that we are willing to allow for timer0. Must be 125 * low enough to guarantee that the timer interrupt handler returns 126 * before the next timer interrupt. 127 */ 128#define TIMER0_MAX_FREQ 20000 129 130int adjkerntz; /* local offset from GMT in seconds */ 131int disable_rtc_set; /* disable resettodr() if != 0 */ 132u_int idelayed; 133int statclock_disable; 134u_int stat_imask = SWI_CLOCK_MASK; 135#ifndef TIMER_FREQ 136#ifdef PC98 137#ifndef AUTO_CLOCK 138#ifndef PC98_8M 139#define TIMER_FREQ 2457600; 140#else /* !PC98_8M */ 141#define TIMER_FREQ 1996800; 142#endif /* PC98_8M */ 143#else /* AUTO_CLOCK */ 144#define TIMER_FREQ 2457600; 145#endif /* AUTO_CLOCK */ 146#else /* IBM-PC */ 147#define TIMER_FREQ 1193182; 148#endif /* PC98 */ 149#endif 150u_int timer_freq = TIMER_FREQ; 151int timer0_max_count; 152u_int tsc_freq; 153int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 154 155static int beeping = 0; 156static u_int clk_imask = HWI_MASK | SWI_MASK; 157static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 158static u_int hardclock_max_count; 159static u_int32_t i8254_lastcount; 160static u_int32_t i8254_offset; 161static int i8254_ticked; 162/* 163 * XXX new_function and timer_func should not handle clockframes, but 164 * timer_func currently needs to hold hardclock to handle the 165 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 166 * to switch between clkintr() and a slightly different timerintr(). 167 */ 168static void (*new_function) __P((struct clockframe *frame)); 169static u_int new_rate; 170#ifndef PC98 171static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 172static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 173#endif 174static u_int timer0_prescaler_count; 175 176/* Values for timerX_state: */ 177#define RELEASED 0 178#define RELEASE_PENDING 1 179#define ACQUIRED 2 180#define ACQUIRE_PENDING 3 181 182static u_char timer0_state; 183#ifdef PC98 184static u_char timer1_state; 185#endif 186static u_char timer2_state; 187static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 188#ifdef PC98 189static void rtc_serialcombit __P((int)); 190static void rtc_serialcom __P((int)); 191static int rtc_inb __P((void)); 192static void rtc_outb __P((int)); 193#endif 194static u_int tsc_present; 195 196static u_int64_t i8254_get_timecount __P((void)); 197static void set_timer_freq(u_int freq, int intr_freq); 198static u_int64_t tsc_get_timecount __P((void)); 199static u_int32_t tsc_get_timedelta __P((struct timecounter *tc)); 200 201static struct timecounter tsc_timecounter[3] = { 202 tsc_get_timedelta, /* get_timedelta */ 203 tsc_get_timecount, /* get_timecount */ 204 ~0, /* counter_mask */ 205 0, /* frequency */ 206 "TSC" /* name */ 207}; 208 209SYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD, 210 tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", ""); 211 212static struct timecounter i8254_timecounter[3] = { 213 0, /* get_timedelta */ 214 i8254_get_timecount, /* get_timecount */ 215 (1ULL << 32) - 1, /* counter_mask */ 216 0, /* frequency */ 217 "i8254" /* name */ 218}; 219 220SYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD, 221 i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", ""); 222 223static void 224clkintr(struct clockframe frame) 225{ 226 if (!i8254_ticked) 227 i8254_offset += timer0_max_count; 228 else 229 i8254_ticked = 0; 230 i8254_lastcount = 0; 231 timer_func(&frame); 232 switch (timer0_state) { 233 234 case RELEASED: 235 setdelayed(); 236 break; 237 238 case ACQUIRED: 239 if ((timer0_prescaler_count += timer0_max_count) 240 >= hardclock_max_count) { 241 timer0_prescaler_count -= hardclock_max_count; 242 hardclock(&frame); 243 setdelayed(); 244 } 245 break; 246 247 case ACQUIRE_PENDING: 248 setdelayed(); 249 timer0_max_count = TIMER_DIV(new_rate); 250 disable_intr(); 251 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 252 outb(TIMER_CNTR0, timer0_max_count & 0xff); 253 outb(TIMER_CNTR0, timer0_max_count >> 8); 254 enable_intr(); 255 timer0_prescaler_count = 0; 256 timer_func = new_function; 257 timer0_state = ACQUIRED; 258 break; 259 260 case RELEASE_PENDING: 261 if ((timer0_prescaler_count += timer0_max_count) 262 >= hardclock_max_count) { 263 timer0_prescaler_count -= hardclock_max_count; 264 /* 265 * See microtime.s for this magic. 266 */ 267#ifdef PC98 268#ifndef AUTO_CLOCK 269#ifndef PC98_8M 270 time.tv_usec += (6667 * timer0_prescaler_count) >> 14; 271#else /* PC98_8M */ 272 time.tv_usec += (16411 * timer0_prescaler_count) >> 15; 273#endif /* PC98_8M */ 274#else /* AUTO_CLOCK */ 275 if (pc98_machine_type & M_8M) { 276 /* PC98_8M */ 277 time.tv_usec += (16411 * timer0_prescaler_count) >> 15; 278 } else { 279 time.tv_usec += (6667 * timer0_prescaler_count) >> 14; 280 } 281#endif /* AUTO_CLOCK */ 282#else /* IBM-PC */ 283 time.tv_usec += (27465 * timer0_prescaler_count) >> 15; 284#endif 285 if (time.tv_usec >= 1000000) 286 time.tv_usec -= 1000000; 287 hardclock(&frame); 288 setdelayed(); 289 timer0_max_count = hardclock_max_count; 290 disable_intr(); 291 outb(TIMER_MODE, 292 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 293 outb(TIMER_CNTR0, timer0_max_count & 0xff); 294 outb(TIMER_CNTR0, timer0_max_count >> 8); 295 enable_intr(); 296 timer0_prescaler_count = 0; 297 timer_func = hardclock; 298 timer0_state = RELEASED; 299 } 300 break; 301 } 302} 303 304/* 305 * The acquire and release functions must be called at ipl >= splclock(). 306 */ 307int 308acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 309{ 310 static int old_rate; 311 312 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 313 return (-1); 314 if (strcmp(timecounter->name, "i8254") == 0) 315 return (-1); 316 switch (timer0_state) { 317 318 case RELEASED: 319 timer0_state = ACQUIRE_PENDING; 320 break; 321 322 case RELEASE_PENDING: 323 if (rate != old_rate) 324 return (-1); 325 /* 326 * The timer has been released recently, but is being 327 * re-acquired before the release completed. In this 328 * case, we simply reclaim it as if it had not been 329 * released at all. 330 */ 331 timer0_state = ACQUIRED; 332 break; 333 334 default: 335 return (-1); /* busy */ 336 } 337 new_function = function; 338 old_rate = new_rate = rate; 339 return (0); 340} 341 342#ifdef PC98 343int 344acquire_timer1(int mode) 345{ 346 347 if (timer1_state != RELEASED) 348 return (-1); 349 timer1_state = ACQUIRED; 350 351 /* 352 * This access to the timer registers is as atomic as possible 353 * because it is a single instruction. We could do better if we 354 * knew the rate. Use of splclock() limits glitches to 10-100us, 355 * and this is probably good enough for timer2, so we aren't as 356 * careful with it as with timer0. 357 */ 358 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 359 360 return (0); 361} 362#endif 363 364int 365acquire_timer2(int mode) 366{ 367 368 if (timer2_state != RELEASED) 369 return (-1); 370 timer2_state = ACQUIRED; 371 372 /* 373 * This access to the timer registers is as atomic as possible 374 * because it is a single instruction. We could do better if we 375 * knew the rate. Use of splclock() limits glitches to 10-100us, 376 * and this is probably good enough for timer2, so we aren't as 377 * careful with it as with timer0. 378 */ 379 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 380 381 return (0); 382} 383 384int 385release_timer0() 386{ 387 switch (timer0_state) { 388 389 case ACQUIRED: 390 timer0_state = RELEASE_PENDING; 391 break; 392 393 case ACQUIRE_PENDING: 394 /* Nothing happened yet, release quickly. */ 395 timer0_state = RELEASED; 396 break; 397 398 default: 399 return (-1); 400 } 401 return (0); 402} 403 404#ifdef PC98 405int 406release_timer1() 407{ 408 409 if (timer1_state != ACQUIRED) 410 return (-1); 411 timer1_state = RELEASED; 412 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 413 return (0); 414} 415#endif 416 417int 418release_timer2() 419{ 420 421 if (timer2_state != ACQUIRED) 422 return (-1); 423 timer2_state = RELEASED; 424 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 425 return (0); 426} 427 428#ifndef PC98 429/* 430 * This routine receives statistical clock interrupts from the RTC. 431 * As explained above, these occur at 128 interrupts per second. 432 * When profiling, we receive interrupts at a rate of 1024 Hz. 433 * 434 * This does not actually add as much overhead as it sounds, because 435 * when the statistical clock is active, the hardclock driver no longer 436 * needs to keep (inaccurate) statistics on its own. This decouples 437 * statistics gathering from scheduling interrupts. 438 * 439 * The RTC chip requires that we read status register C (RTC_INTR) 440 * to acknowledge an interrupt, before it will generate the next one. 441 * Under high interrupt load, rtcintr() can be indefinitely delayed and 442 * the clock can tick immediately after the read from RTC_INTR. In this 443 * case, the mc146818A interrupt signal will not drop for long enough 444 * to register with the 8259 PIC. If an interrupt is missed, the stat 445 * clock will halt, considerably degrading system performance. This is 446 * why we use 'while' rather than a more straightforward 'if' below. 447 * Stat clock ticks can still be lost, causing minor loss of accuracy 448 * in the statistics, but the stat clock will no longer stop. 449 */ 450static void 451rtcintr(struct clockframe frame) 452{ 453 while (rtcin(RTC_INTR) & RTCIR_PERIOD) 454 statclock(&frame); 455} 456 457#include "opt_ddb.h" 458#ifdef DDB 459#include <ddb/ddb.h> 460 461DB_SHOW_COMMAND(rtc, rtc) 462{ 463 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 464 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 465 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 466 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 467} 468#endif /* DDB */ 469#endif /* for PC98 */ 470 471static int 472getit(void) 473{ 474 u_long ef; 475 int high, low; 476 477 ef = read_eflags(); 478 disable_intr(); 479 480 /* Select timer0 and latch counter value. */ 481 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 482 483 low = inb(TIMER_CNTR0); 484 high = inb(TIMER_CNTR0); 485 486 CLOCK_UNLOCK(); 487 write_eflags(ef); 488 return ((high << 8) | low); 489} 490 491/* 492 * Wait "n" microseconds. 493 * Relies on timer 1 counting down from (timer_freq / hz) 494 * Note: timer had better have been programmed before this is first used! 495 */ 496void 497DELAY(int n) 498{ 499 int delta, prev_tick, tick, ticks_left; 500 501#ifdef DELAYDEBUG 502 int getit_calls = 1; 503 int n1; 504 static int state = 0; 505 506 if (state == 0) { 507 state = 1; 508 for (n1 = 1; n1 <= 10000000; n1 *= 10) 509 DELAY(n1); 510 state = 2; 511 } 512 if (state == 1) 513 printf("DELAY(%d)...", n); 514#endif 515 /* 516 * Guard against the timer being uninitialized if we are called 517 * early for console i/o. 518 */ 519 if (timer0_max_count == 0) 520 set_timer_freq(timer_freq, hz); 521 522 /* 523 * Read the counter first, so that the rest of the setup overhead is 524 * counted. Guess the initial overhead is 20 usec (on most systems it 525 * takes about 1.5 usec for each of the i/o's in getit(). The loop 526 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 527 * multiplications and divisions to scale the count take a while). 528 */ 529 prev_tick = getit(); 530 n -= 0; /* XXX actually guess no initial overhead */ 531 /* 532 * Calculate (n * (timer_freq / 1e6)) without using floating point 533 * and without any avoidable overflows. 534 */ 535 if (n <= 0) 536 ticks_left = 0; 537 else if (n < 256) 538 /* 539 * Use fixed point to avoid a slow division by 1000000. 540 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 541 * 2^15 is the first power of 2 that gives exact results 542 * for n between 0 and 256. 543 */ 544 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 545 else 546 /* 547 * Don't bother using fixed point, although gcc-2.7.2 548 * generates particularly poor code for the long long 549 * division, since even the slow way will complete long 550 * before the delay is up (unless we're interrupted). 551 */ 552 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 553 / 1000000; 554 555 while (ticks_left > 0) { 556 tick = getit(); 557#ifdef DELAYDEBUG 558 ++getit_calls; 559#endif 560 delta = prev_tick - tick; 561 prev_tick = tick; 562 if (delta < 0) { 563 delta += timer0_max_count; 564 /* 565 * Guard against timer0_max_count being wrong. 566 * This shouldn't happen in normal operation, 567 * but it may happen if set_timer_freq() is 568 * traced. 569 */ 570 if (delta < 0) 571 delta = 0; 572 } 573 ticks_left -= delta; 574 } 575#ifdef DELAYDEBUG 576 if (state == 1) 577 printf(" %d calls to getit() at %d usec each\n", 578 getit_calls, (n + 5) / getit_calls); 579#endif 580} 581 582static void 583sysbeepstop(void *chan) 584{ 585#ifdef PC98 /* PC98 */ 586 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 587 release_timer1(); 588#else 589 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 590 release_timer2(); 591#endif 592 beeping = 0; 593} 594 595int 596sysbeep(int pitch, int period) 597{ 598 int x = splclock(); 599 600#ifdef PC98 601 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 602 if (!beeping) { 603 /* Something else owns it. */ 604 splx(x); 605 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 606 } 607 disable_intr(); 608 outb(0x3fdb, pitch); 609 outb(0x3fdb, (pitch>>8)); 610 enable_intr(); 611 if (!beeping) { 612 /* enable counter1 output to speaker */ 613 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 614 beeping = period; 615 timeout(sysbeepstop, (void *)NULL, period); 616 } 617#else 618 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 619 if (!beeping) { 620 /* Something else owns it. */ 621 splx(x); 622 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 623 } 624 disable_intr(); 625 outb(TIMER_CNTR2, pitch); 626 outb(TIMER_CNTR2, (pitch>>8)); 627 enable_intr(); 628 if (!beeping) { 629 /* enable counter2 output to speaker */ 630 outb(IO_PPI, inb(IO_PPI) | 3); 631 beeping = period; 632 timeout(sysbeepstop, (void *)NULL, period); 633 } 634#endif 635 splx(x); 636 return (0); 637} 638 639#ifndef PC98 640/* 641 * RTC support routines 642 */ 643 644int 645rtcin(reg) 646 int reg; 647{ 648 u_char val; 649 650 outb(IO_RTC, reg); 651 inb(0x84); 652 val = inb(IO_RTC + 1); 653 inb(0x84); 654 return (val); 655} 656 657static __inline void 658writertc(u_char reg, u_char val) 659{ 660 inb(0x84); 661 outb(IO_RTC, reg); 662 inb(0x84); 663 outb(IO_RTC + 1, val); 664 inb(0x84); /* XXX work around wrong order in rtcin() */ 665} 666 667static __inline int 668readrtc(int port) 669{ 670 return(bcd2bin(rtcin(port))); 671} 672#endif 673 674#ifdef PC98 675unsigned int delaycount; 676#define FIRST_GUESS 0x2000 677static void findcpuspeed(void) 678{ 679 int i; 680 int remainder; 681 682 /* Put counter in count down mode */ 683 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 684 outb(TIMER_CNTR0, 0xff); 685 outb(TIMER_CNTR0, 0xff); 686 for (i = FIRST_GUESS; i; i--) 687 ; 688 remainder = getit(); 689 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 690} 691#endif 692 693#ifndef PC98 694static u_int 695calibrate_clocks(void) 696{ 697 u_int count, prev_count, tot_count; 698 int sec, start_sec, timeout; 699 700 if (bootverbose) 701 printf("Calibrating clock(s) ... "); 702 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 703 goto fail; 704 timeout = 100000000; 705 706 /* Read the mc146818A seconds counter. */ 707 for (;;) { 708 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 709 sec = rtcin(RTC_SEC); 710 break; 711 } 712 if (--timeout == 0) 713 goto fail; 714 } 715 716 /* Wait for the mC146818A seconds counter to change. */ 717 start_sec = sec; 718 for (;;) { 719 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 720 sec = rtcin(RTC_SEC); 721 if (sec != start_sec) 722 break; 723 } 724 if (--timeout == 0) 725 goto fail; 726 } 727 728 /* Start keeping track of the i8254 counter. */ 729 prev_count = getit(); 730 if (prev_count == 0 || prev_count > timer0_max_count) 731 goto fail; 732 tot_count = 0; 733 734 if (tsc_present) 735 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 736 737 /* 738 * Wait for the mc146818A seconds counter to change. Read the i8254 739 * counter for each iteration since this is convenient and only 740 * costs a few usec of inaccuracy. The timing of the final reads 741 * of the counters almost matches the timing of the initial reads, 742 * so the main cause of inaccuracy is the varying latency from 743 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 744 * rtcin(RTC_SEC) that returns a changed seconds count. The 745 * maximum inaccuracy from this cause is < 10 usec on 486's. 746 */ 747 start_sec = sec; 748 for (;;) { 749 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 750 sec = rtcin(RTC_SEC); 751 count = getit(); 752 if (count == 0 || count > timer0_max_count) 753 goto fail; 754 if (count > prev_count) 755 tot_count += prev_count - (count - timer0_max_count); 756 else 757 tot_count += prev_count - count; 758 prev_count = count; 759 if (sec != start_sec) 760 break; 761 if (--timeout == 0) 762 goto fail; 763 } 764 765 /* 766 * Read the cpu cycle counter. The timing considerations are 767 * similar to those for the i8254 clock. 768 */ 769 if (tsc_present) 770 tsc_freq = rdtsc(); 771 772 if (bootverbose) { 773 if (tsc_present) 774 printf("TSC clock: %u Hz, ", tsc_freq); 775 printf("i8254 clock: %u Hz\n", tot_count); 776 } 777 return (tot_count); 778 779fail: 780 if (bootverbose) 781 printf("failed, using default i8254 clock of %u Hz\n", 782 timer_freq); 783 return (timer_freq); 784} 785#endif /* !PC98 */ 786 787static void 788set_timer_freq(u_int freq, int intr_freq) 789{ 790 u_long ef; 791 int new_timer0_max_count; 792 793 ef = read_eflags(); 794 disable_intr(); 795 timer_freq = freq; 796 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 797 if (new_timer0_max_count != timer0_max_count) { 798 timer0_max_count = new_timer0_max_count; 799 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 800 outb(TIMER_CNTR0, timer0_max_count & 0xff); 801 outb(TIMER_CNTR0, timer0_max_count >> 8); 802 } 803 CLOCK_UNLOCK(); 804 write_eflags(ef); 805} 806 807/* 808 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 809 * XXX initialization of other timers is unintentionally left blank. 810 */ 811void 812startrtclock() 813{ 814 u_int delta, freq; 815 816#ifdef PC98 817 findcpuspeed(); 818#ifndef AUTO_CLOCK 819 if (pc98_machine_type & M_8M) { 820#ifndef PC98_8M 821 printf("you must reconfig a kernel with \"PC98_8M\" option.\n"); 822#endif 823 } else { 824#ifdef PC98_8M 825 printf("You must reconfig a kernel without \"PC98_8M\" option.\n"); 826#endif 827 } 828#else /* AUTO_CLOCK */ 829 if (pc98_machine_type & M_8M) 830 timer_freq = 1996800L; /* 1.9968 MHz */ 831 else 832 timer_freq = 2457600L; /* 2.4576 MHz */ 833#endif /* AUTO_CLOCK */ 834#endif /* PC98 */ 835 836 if (cpu_feature & CPUID_TSC) 837 tsc_present = 1; 838 else 839 tsc_present = 0; 840 841#ifdef SMP 842 tsc_present = 0; 843#endif 844#if NAPM > 0 845 tsc_present = 0; 846#endif 847 848#ifndef PC98 849 writertc(RTC_STATUSA, rtc_statusa); 850 writertc(RTC_STATUSB, RTCSB_24HR); 851#endif 852 853#ifndef PC98 854 set_timer_freq(timer_freq, hz); 855 freq = calibrate_clocks(); 856#ifdef CLK_CALIBRATION_LOOP 857 if (bootverbose) { 858 printf( 859 "Press a key on the console to abort clock calibration\n"); 860 while (cncheckc() == -1) 861 calibrate_clocks(); 862 } 863#endif 864 865 /* 866 * Use the calibrated i8254 frequency if it seems reasonable. 867 * Otherwise use the default, and don't use the calibrated i586 868 * frequency. 869 */ 870 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 871 if (delta < timer_freq / 100) { 872#ifndef CLK_USE_I8254_CALIBRATION 873 if (bootverbose) 874 printf( 875"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 876 freq = timer_freq; 877#endif 878 timer_freq = freq; 879 } else { 880 if (bootverbose) 881 printf( 882 "%d Hz differs from default of %d Hz by more than 1%%\n", 883 freq, timer_freq); 884 tsc_freq = 0; 885 } 886#endif 887 888 set_timer_freq(timer_freq, hz); 889 i8254_timecounter[0].frequency = timer_freq; 890 init_timecounter(i8254_timecounter); 891 892#ifndef CLK_USE_TSC_CALIBRATION 893 if (tsc_freq != 0) { 894 if (bootverbose) 895 printf( 896"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 897 tsc_freq = 0; 898 } 899#endif 900 if (tsc_present && tsc_freq == 0) { 901 /* 902 * Calibration of the i586 clock relative to the mc146818A 903 * clock failed. Do a less accurate calibration relative 904 * to the i8254 clock. 905 */ 906 wrmsr(0x10, 0LL); /* XXX */ 907 DELAY(1000000); 908 tsc_freq = rdtsc(); 909#ifdef CLK_USE_TSC_CALIBRATION 910 if (bootverbose) 911 printf("TSC clock: %u Hz (Method B)\n", tsc_freq); 912#endif 913 } 914 if (tsc_present && tsc_freq != 0) { 915 tsc_timecounter[0].frequency = tsc_freq; 916 init_timecounter(tsc_timecounter); 917 } 918} 919 920#ifdef PC98 921static void 922rtc_serialcombit(int i) 923{ 924 outb(IO_RTC, ((i&0x01)<<5)|0x07); 925 DELAY(1); 926 outb(IO_RTC, ((i&0x01)<<5)|0x17); 927 DELAY(1); 928 outb(IO_RTC, ((i&0x01)<<5)|0x07); 929 DELAY(1); 930} 931 932static void 933rtc_serialcom(int i) 934{ 935 rtc_serialcombit(i&0x01); 936 rtc_serialcombit((i&0x02)>>1); 937 rtc_serialcombit((i&0x04)>>2); 938 rtc_serialcombit((i&0x08)>>3); 939 outb(IO_RTC, 0x07); 940 DELAY(1); 941 outb(IO_RTC, 0x0f); 942 DELAY(1); 943 outb(IO_RTC, 0x07); 944 DELAY(1); 945} 946 947static void 948rtc_outb(int val) 949{ 950 int s; 951 int sa = 0; 952 953 for (s=0;s<8;s++) { 954 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 955 outb(IO_RTC, sa); /* set DI & CLK 0 */ 956 DELAY(1); 957 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 958 DELAY(1); 959 } 960 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 961} 962 963static int 964rtc_inb(void) 965{ 966 int s; 967 int sa = 0; 968 969 for (s=0;s<8;s++) { 970 sa |= ((inb(0x33) & 0x01) << s); 971 outb(IO_RTC, 0x17); /* CLK 1 */ 972 DELAY(1); 973 outb(IO_RTC, 0x07); /* CLK 0 */ 974 DELAY(2); 975 } 976 return sa; 977} 978#endif /* PC-98 */ 979 980/* 981 * Initialize the time of day register, based on the time base which is, e.g. 982 * from a filesystem. 983 */ 984void 985inittodr(time_t base) 986{ 987 unsigned long sec, days; 988 int yd; 989 int year, month; 990 int y, m, s; 991 struct timespec ts; 992#ifdef PC98 993 int second, min, hour; 994#endif 995 996 if (base) { 997 s = splclock(); 998 ts.tv_sec = base; 999 ts.tv_nsec = 0; 1000 set_timecounter(&ts); 1001 splx(s); 1002 } 1003 1004#ifdef PC98 1005 rtc_serialcom(0x03); /* Time Read */ 1006 rtc_serialcom(0x01); /* Register shift command. */ 1007 DELAY(20); 1008 1009 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 1010 min = bcd2bin(rtc_inb() & 0xff); /* min */ 1011 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 1012 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 1013 1014 month = (rtc_inb() >> 4) & 0x0f; /* month */ 1015 for (m = 1; m < month; m++) 1016 days += daysinmonth[m-1]; 1017 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 1018 /* 2000 year problem */ 1019 if (year < 1995) 1020 year += 100; 1021 if (year < 1970) 1022 goto wrong_time; 1023 for (y = 1970; y < year; y++) 1024 days += DAYSPERYEAR + LEAPYEAR(y); 1025 if ((month > 2) && LEAPYEAR(year)) 1026 days ++; 1027 sec = ((( days * 24 + 1028 hour) * 60 + 1029 min) * 60 + 1030 second); 1031 /* sec now contains the number of seconds, since Jan 1 1970, 1032 in the local time zone */ 1033#else /* IBM-PC */ 1034 /* Look if we have a RTC present and the time is valid */ 1035 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 1036 goto wrong_time; 1037 1038 /* wait for time update to complete */ 1039 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 1040 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 1041 1042 days = 0; 1043#ifdef USE_RTC_CENTURY 1044 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 1045#else 1046 year = readrtc(RTC_YEAR) + 1900; 1047 if (year < 1970) 1048 year += 100; 1049#endif 1050 if (year < 1970) 1051 goto wrong_time; 1052 month = readrtc(RTC_MONTH); 1053 for (m = 1; m < month; m++) 1054 days += daysinmonth[m-1]; 1055 if ((month > 2) && LEAPYEAR(year)) 1056 days ++; 1057 days += readrtc(RTC_DAY) - 1; 1058 yd = days; 1059 for (y = 1970; y < year; y++) 1060 days += DAYSPERYEAR + LEAPYEAR(y); 1061 sec = ((( days * 24 + 1062 readrtc(RTC_HRS)) * 60 + 1063 readrtc(RTC_MIN)) * 60 + 1064 readrtc(RTC_SEC)); 1065 /* sec now contains the number of seconds, since Jan 1 1970, 1066 in the local time zone */ 1067#endif 1068 1069 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1070 1071 y = time.tv_sec - sec; 1072 if (y <= -2 || y >= 2) { 1073 /* badly off, adjust it */ 1074 s = splclock(); 1075 ts.tv_sec = sec; 1076 ts.tv_nsec = 0; 1077 set_timecounter(&ts); 1078 splx(s); 1079 } 1080 return; 1081 1082wrong_time: 1083 printf("Invalid time in real time clock.\n"); 1084 printf("Check and reset the date immediately!\n"); 1085} 1086 1087/* 1088 * Write system time back to RTC 1089 */ 1090void 1091resettodr() 1092{ 1093 unsigned long tm; 1094 int y, m, s; 1095#ifdef PC98 1096 int wd; 1097#endif 1098 1099 if (disable_rtc_set) 1100 return; 1101 1102 s = splclock(); 1103 tm = time.tv_sec; 1104 splx(s); 1105 1106#ifdef PC98 1107 rtc_serialcom(0x01); /* Register shift command. */ 1108 1109 /* Calculate local time to put in RTC */ 1110 1111 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1112 1113 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1114 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1115 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1116 1117 /* We have now the days since 01-01-1970 in tm */ 1118 wd = (tm+4)%7; 1119 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1120 tm >= m; 1121 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1122 tm -= m; 1123 1124 /* Now we have the years in y and the day-of-the-year in tm */ 1125 for (m = 0; ; m++) { 1126 int ml; 1127 1128 ml = daysinmonth[m]; 1129 if (m == 1 && LEAPYEAR(y)) 1130 ml++; 1131 if (tm < ml) 1132 break; 1133 tm -= ml; 1134 } 1135 1136 m++; 1137 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1138 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1139 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1140 1141 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1142 rtc_serialcom(0x00); /* Register hold command. */ 1143#else 1144 /* Disable RTC updates and interrupts. */ 1145 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1146 1147 /* Calculate local time to put in RTC */ 1148 1149 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1150 1151 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1152 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1153 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1154 1155 /* We have now the days since 01-01-1970 in tm */ 1156 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1157 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1158 tm >= m; 1159 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1160 tm -= m; 1161 1162 /* Now we have the years in y and the day-of-the-year in tm */ 1163 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1164#ifdef USE_RTC_CENTURY 1165 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1166#endif 1167 for (m = 0; ; m++) { 1168 int ml; 1169 1170 ml = daysinmonth[m]; 1171 if (m == 1 && LEAPYEAR(y)) 1172 ml++; 1173 if (tm < ml) 1174 break; 1175 tm -= ml; 1176 } 1177 1178 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1179 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1180 1181 /* Reenable RTC updates and interrupts. */ 1182 writertc(RTC_STATUSB, rtc_statusb); 1183#endif 1184} 1185 1186 1187/* 1188 * Start both clocks running. 1189 */ 1190void 1191cpu_initclocks() 1192{ 1193#ifdef APIC_IO 1194 int x; 1195#endif /* APIC_IO */ 1196#ifndef PC98 1197 int diag; 1198 1199 if (statclock_disable) { 1200 /* 1201 * The stat interrupt mask is different without the 1202 * statistics clock. Also, don't set the interrupt 1203 * flag which would normally cause the RTC to generate 1204 * interrupts. 1205 */ 1206 stat_imask = HWI_MASK | SWI_MASK; 1207 rtc_statusb = RTCSB_24HR; 1208 } else { 1209 /* Setting stathz to nonzero early helps avoid races. */ 1210 stathz = RTC_NOPROFRATE; 1211 profhz = RTC_PROFRATE; 1212 } 1213#endif 1214 1215 /* Finish initializing 8253 timer 0. */ 1216#ifdef APIC_IO 1217 1218 /* 1st look for ExtInt on pin 0 */ 1219 if (apic_int_type(0, 0) == 3) { 1220 /* 1221 * Allow 8254 timer to INTerrupt 8259: 1222 * re-initialize master 8259: 1223 * reset; prog 4 bytes, single ICU, edge triggered 1224 */ 1225 outb(IO_ICU1, 0x13); 1226 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */ 1227 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1228 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1229 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1230 1231 /* program IO APIC for type 3 INT on INT0 */ 1232 if (ext_int_setup(0, 0) < 0) 1233 panic("8254 redirect via APIC pin0 impossible!"); 1234 1235 x = 0; 1236 /* XXX if (bootverbose) */ 1237 printf("APIC_IO: routing 8254 via 8259 on pin 0\n"); 1238 } 1239 1240 /* failing that, look for 8254 on pin 2 */ 1241 else if (isa_apic_pin(0) == 2) { 1242 x = 2; 1243 /* XXX if (bootverbose) */ 1244 printf("APIC_IO: routing 8254 via pin 2\n"); 1245 } 1246 1247 /* better write that 8254 INT discover code... */ 1248 else 1249 panic("neither pin 0 or pin 2 works for 8254"); 1250 1251 apic_8254_intr = x; 1252 1253 register_intr(/* irq */ x, /* XXX id */ 0, /* flags */ 0, 1254 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1255 /* unit */ 0); 1256 INTREN(1 << x); 1257 1258#else /* APIC_IO */ 1259 1260 register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, 1261 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1262 /* unit */ 0); 1263 INTREN(IRQ0); 1264 1265#endif /* APIC_IO */ 1266 1267#ifndef PC98 1268 /* Initialize RTC. */ 1269 writertc(RTC_STATUSA, rtc_statusa); 1270 writertc(RTC_STATUSB, RTCSB_24HR); 1271 1272 /* Don't bother enabling the statistics clock. */ 1273 if (statclock_disable) 1274 return; 1275 diag = rtcin(RTC_DIAG); 1276 if (diag != 0) 1277 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1278 1279#ifdef APIC_IO 1280 if (isa_apic_pin(8) != 8) 1281 panic("APIC RTC != 8"); 1282#endif /* APIC_IO */ 1283 1284 register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, 1285 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1286 /* unit */ 0); 1287 1288#ifdef APIC_IO 1289 INTREN(APIC_IRQ8); 1290#else 1291 INTREN(IRQ8); 1292#endif /* APIC_IO */ 1293 1294 writertc(RTC_STATUSB, rtc_statusb); 1295#endif /* !PC98 */ 1296} 1297 1298void 1299setstatclockrate(int newhz) 1300{ 1301#ifndef PC98 1302 if (newhz == RTC_PROFRATE) 1303 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1304 else 1305 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1306 writertc(RTC_STATUSA, rtc_statusa); 1307#endif 1308} 1309 1310static int 1311sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1312{ 1313 int error; 1314 u_int freq; 1315 1316 /* 1317 * Use `i8254' instead of `timer' in external names because `timer' 1318 * is is too generic. Should use it everywhere. 1319 */ 1320 freq = timer_freq; 1321 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1322 if (error == 0 && req->newptr != NULL) { 1323 if (timer0_state != RELEASED) 1324 return (EBUSY); /* too much trouble to handle */ 1325 set_timer_freq(freq, hz); 1326 i8254_timecounter[0].frequency = freq; 1327 } 1328 return (error); 1329} 1330 1331SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1332 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1333 1334static int 1335sysctl_machdep_tsc_freq SYSCTL_HANDLER_ARGS 1336{ 1337 int error; 1338 u_int freq; 1339 1340 if (!tsc_present) 1341 return (EOPNOTSUPP); 1342 freq = tsc_freq; 1343 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1344 if (error == 0 && req->newptr != NULL) { 1345 tsc_freq = freq; 1346 tsc_timecounter[0].frequency = tsc_freq; 1347 } 1348 return (error); 1349} 1350 1351SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW, 1352 0, sizeof(u_int), sysctl_machdep_tsc_freq, "I", ""); 1353 1354static u_int64_t 1355i8254_get_timecount(void) 1356{ 1357 u_int32_t count; 1358 u_long ef; 1359 u_int high, low; 1360 1361 ef = read_eflags(); 1362 disable_intr(); 1363 1364 /* Select timer0 and latch counter value. */ 1365 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 1366 1367 low = inb(TIMER_CNTR0); 1368 high = inb(TIMER_CNTR0); 1369 1370 count = hardclock_max_count - ((high << 8) | low); 1371 if (count < i8254_lastcount) { 1372 i8254_ticked = 1; 1373 i8254_offset += hardclock_max_count; 1374 } 1375 1376 i8254_lastcount = count; 1377 count += i8254_offset; 1378 CLOCK_UNLOCK(); 1379 write_eflags(ef); 1380 return (count); 1381} 1382 1383static u_int64_t 1384tsc_get_timecount(void) 1385{ 1386 return ((u_int64_t)rdtsc()); 1387} 1388 1389static u_int32_t 1390tsc_get_timedelta(struct timecounter *tc) 1391{ 1392 return ((u_int64_t)rdtsc() - tc->offset_count); 1393} 1394