pcrtc.c revision 33746
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $Id: clock.c,v 1.44 1998/02/21 15:54:23 kato Exp $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51/* 52 * modified for PC98 by Kakefuda 53 */ 54 55#include "opt_clock.h" 56 57#include <sys/param.h> 58#include <sys/systm.h> 59#include <sys/time.h> 60#include <sys/kernel.h> 61#ifndef SMP 62#include <sys/lock.h> 63#endif 64#include <sys/sysctl.h> 65 66#include <machine/clock.h> 67#ifdef CLK_CALIBRATION_LOOP 68#include <machine/cons.h> 69#endif 70#include <machine/cputypes.h> 71#include <machine/frame.h> 72#include <machine/ipl.h> 73#include <machine/limits.h> 74#include <machine/md_var.h> 75#ifdef APIC_IO 76#include <machine/segments.h> 77#endif 78#if defined(SMP) || defined(APIC_IO) 79#include <machine/smp.h> 80#endif /* SMP || APIC_IO */ 81#include <machine/specialreg.h> 82 83#include <i386/isa/icu.h> 84#ifdef PC98 85#include <pc98/pc98/pc98.h> 86#include <pc98/pc98/pc98_machdep.h> 87#include <i386/isa/isa_device.h> 88#else 89#include <i386/isa/isa.h> 90#include <i386/isa/rtc.h> 91#endif 92#include <i386/isa/timerreg.h> 93 94#include <sys/interrupt.h> 95 96#ifdef SMP 97#define disable_intr() CLOCK_DISABLE_INTR() 98#define enable_intr() CLOCK_ENABLE_INTR() 99#endif /* SMP */ 100 101/* 102 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 103 * can use a simple formula for leap years. 104 */ 105#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 106#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 107 108#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 109 110/* 111 * Time in timer cycles that it takes for microtime() to disable interrupts 112 * and latch the count. microtime() currently uses "cli; outb ..." so it 113 * normally takes less than 2 timer cycles. Add a few for cache misses. 114 * Add a few more to allow for latency in bogus calls to microtime() with 115 * interrupts already disabled. 116 */ 117#define TIMER0_LATCH_COUNT 20 118 119/* 120 * Maximum frequency that we are willing to allow for timer0. Must be 121 * low enough to guarantee that the timer interrupt handler returns 122 * before the next timer interrupt. 123 */ 124#define TIMER0_MAX_FREQ 20000 125 126int adjkerntz; /* local offset from GMT in seconds */ 127int disable_rtc_set; /* disable resettodr() if != 0 */ 128u_int idelayed; 129int statclock_disable; 130u_int stat_imask = SWI_CLOCK_MASK; 131#ifndef TIMER_FREQ 132#ifdef PC98 133#ifndef AUTO_CLOCK 134#ifndef PC98_8M 135#define TIMER_FREQ 2457600; 136#else /* !PC98_8M */ 137#define TIMER_FREQ 1996800; 138#endif /* PC98_8M */ 139#else /* AUTO_CLOCK */ 140#define TIMER_FREQ 2457600; 141#endif /* AUTO_CLOCK */ 142#else /* IBM-PC */ 143#define TIMER_FREQ 1193182; 144#endif /* PC98 */ 145#endif 146u_int timer_freq = TIMER_FREQ; 147int timer0_max_count; 148u_int tsc_freq; 149int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 150 151static int beeping = 0; 152static u_int clk_imask = HWI_MASK | SWI_MASK; 153static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 154static u_int hardclock_max_count; 155static u_int32_t i8254_lastcount; 156static u_int32_t i8254_offset; 157static int i8254_ticked; 158/* 159 * XXX new_function and timer_func should not handle clockframes, but 160 * timer_func currently needs to hold hardclock to handle the 161 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 162 * to switch between clkintr() and a slightly different timerintr(). 163 */ 164static void (*new_function) __P((struct clockframe *frame)); 165static u_int new_rate; 166#ifndef PC98 167static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 168static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 169#endif 170static u_int timer0_prescaler_count; 171 172/* Values for timerX_state: */ 173#define RELEASED 0 174#define RELEASE_PENDING 1 175#define ACQUIRED 2 176#define ACQUIRE_PENDING 3 177 178static u_char timer0_state; 179#ifdef PC98 180static u_char timer1_state; 181#endif 182static u_char timer2_state; 183static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 184#ifdef PC98 185static void rtc_serialcombit __P((int)); 186static void rtc_serialcom __P((int)); 187static int rtc_inb __P((void)); 188static void rtc_outb __P((int)); 189#endif 190static u_int tsc_present; 191 192static u_int64_t i8254_get_timecount __P((void)); 193static void set_timer_freq(u_int freq, int intr_freq); 194static u_int64_t tsc_get_timecount __P((void)); 195static u_int32_t tsc_get_timedelta __P((struct timecounter *tc)); 196 197static struct timecounter tsc_timecounter[3] = { 198 tsc_get_timedelta, /* get_timedelta */ 199 tsc_get_timecount, /* get_timecount */ 200 ~0, /* counter_mask */ 201 0, /* frequency */ 202 "TSC" /* name */ 203}; 204 205SYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD, 206 tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", ""); 207 208static struct timecounter i8254_timecounter[3] = { 209 0, /* get_timedelta */ 210 i8254_get_timecount, /* get_timecount */ 211 (1ULL << 32) - 1, /* counter_mask */ 212 0, /* frequency */ 213 "i8254" /* name */ 214}; 215 216SYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD, 217 i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", ""); 218 219static void 220clkintr(struct clockframe frame) 221{ 222 if (!i8254_ticked) 223 i8254_offset += timer0_max_count; 224 else 225 i8254_ticked = 0; 226 timer_func(&frame); 227 switch (timer0_state) { 228 229 case RELEASED: 230 setdelayed(); 231 break; 232 233 case ACQUIRED: 234 if ((timer0_prescaler_count += timer0_max_count) 235 >= hardclock_max_count) { 236 timer0_prescaler_count -= hardclock_max_count; 237 hardclock(&frame); 238 setdelayed(); 239 } 240 break; 241 242 case ACQUIRE_PENDING: 243 setdelayed(); 244 timer0_max_count = TIMER_DIV(new_rate); 245 disable_intr(); 246 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 247 outb(TIMER_CNTR0, timer0_max_count & 0xff); 248 outb(TIMER_CNTR0, timer0_max_count >> 8); 249 enable_intr(); 250 timer0_prescaler_count = 0; 251 timer_func = new_function; 252 timer0_state = ACQUIRED; 253 break; 254 255 case RELEASE_PENDING: 256 if ((timer0_prescaler_count += timer0_max_count) 257 >= hardclock_max_count) { 258 timer0_prescaler_count -= hardclock_max_count; 259 /* 260 * See microtime.s for this magic. 261 */ 262#ifdef PC98 263#ifndef AUTO_CLOCK 264#ifndef PC98_8M 265 time.tv_usec += (6667 * timer0_prescaler_count) >> 14; 266#else /* PC98_8M */ 267 time.tv_usec += (16411 * timer0_prescaler_count) >> 15; 268#endif /* PC98_8M */ 269#else /* AUTO_CLOCK */ 270 if (pc98_machine_type & M_8M) { 271 /* PC98_8M */ 272 time.tv_usec += (16411 * timer0_prescaler_count) >> 15; 273 } else { 274 time.tv_usec += (6667 * timer0_prescaler_count) >> 14; 275 } 276#endif /* AUTO_CLOCK */ 277#else /* IBM-PC */ 278 time.tv_usec += (27465 * timer0_prescaler_count) >> 15; 279#endif 280 if (time.tv_usec >= 1000000) 281 time.tv_usec -= 1000000; 282 hardclock(&frame); 283 setdelayed(); 284 timer0_max_count = hardclock_max_count; 285 disable_intr(); 286 outb(TIMER_MODE, 287 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 288 outb(TIMER_CNTR0, timer0_max_count & 0xff); 289 outb(TIMER_CNTR0, timer0_max_count >> 8); 290 enable_intr(); 291 timer0_prescaler_count = 0; 292 timer_func = hardclock; 293 timer0_state = RELEASED; 294 } 295 break; 296 } 297} 298 299/* 300 * The acquire and release functions must be called at ipl >= splclock(). 301 */ 302int 303acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 304{ 305 static int old_rate; 306 307 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 308 return (-1); 309 if (strcmp(timecounter->name, "i8254") == 0) 310 return (-1); 311 switch (timer0_state) { 312 313 case RELEASED: 314 timer0_state = ACQUIRE_PENDING; 315 break; 316 317 case RELEASE_PENDING: 318 if (rate != old_rate) 319 return (-1); 320 /* 321 * The timer has been released recently, but is being 322 * re-acquired before the release completed. In this 323 * case, we simply reclaim it as if it had not been 324 * released at all. 325 */ 326 timer0_state = ACQUIRED; 327 break; 328 329 default: 330 return (-1); /* busy */ 331 } 332 new_function = function; 333 old_rate = new_rate = rate; 334 return (0); 335} 336 337#ifdef PC98 338int 339acquire_timer1(int mode) 340{ 341 342 if (timer1_state != RELEASED) 343 return (-1); 344 timer1_state = ACQUIRED; 345 346 /* 347 * This access to the timer registers is as atomic as possible 348 * because it is a single instruction. We could do better if we 349 * knew the rate. Use of splclock() limits glitches to 10-100us, 350 * and this is probably good enough for timer2, so we aren't as 351 * careful with it as with timer0. 352 */ 353 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 354 355 return (0); 356} 357#endif 358 359int 360acquire_timer2(int mode) 361{ 362 363 if (timer2_state != RELEASED) 364 return (-1); 365 timer2_state = ACQUIRED; 366 367 /* 368 * This access to the timer registers is as atomic as possible 369 * because it is a single instruction. We could do better if we 370 * knew the rate. Use of splclock() limits glitches to 10-100us, 371 * and this is probably good enough for timer2, so we aren't as 372 * careful with it as with timer0. 373 */ 374 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 375 376 return (0); 377} 378 379int 380release_timer0() 381{ 382 switch (timer0_state) { 383 384 case ACQUIRED: 385 timer0_state = RELEASE_PENDING; 386 break; 387 388 case ACQUIRE_PENDING: 389 /* Nothing happened yet, release quickly. */ 390 timer0_state = RELEASED; 391 break; 392 393 default: 394 return (-1); 395 } 396 return (0); 397} 398 399#ifdef PC98 400int 401release_timer1() 402{ 403 404 if (timer1_state != ACQUIRED) 405 return (-1); 406 timer1_state = RELEASED; 407 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 408 return (0); 409} 410#endif 411 412int 413release_timer2() 414{ 415 416 if (timer2_state != ACQUIRED) 417 return (-1); 418 timer2_state = RELEASED; 419 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 420 return (0); 421} 422 423#ifndef PC98 424/* 425 * This routine receives statistical clock interrupts from the RTC. 426 * As explained above, these occur at 128 interrupts per second. 427 * When profiling, we receive interrupts at a rate of 1024 Hz. 428 * 429 * This does not actually add as much overhead as it sounds, because 430 * when the statistical clock is active, the hardclock driver no longer 431 * needs to keep (inaccurate) statistics on its own. This decouples 432 * statistics gathering from scheduling interrupts. 433 * 434 * The RTC chip requires that we read status register C (RTC_INTR) 435 * to acknowledge an interrupt, before it will generate the next one. 436 * Under high interrupt load, rtcintr() can be indefinitely delayed and 437 * the clock can tick immediately after the read from RTC_INTR. In this 438 * case, the mc146818A interrupt signal will not drop for long enough 439 * to register with the 8259 PIC. If an interrupt is missed, the stat 440 * clock will halt, considerably degrading system performance. This is 441 * why we use 'while' rather than a more straightforward 'if' below. 442 * Stat clock ticks can still be lost, causing minor loss of accuracy 443 * in the statistics, but the stat clock will no longer stop. 444 */ 445static void 446rtcintr(struct clockframe frame) 447{ 448 while (rtcin(RTC_INTR) & RTCIR_PERIOD) 449 statclock(&frame); 450} 451 452#include "opt_ddb.h" 453#ifdef DDB 454#include <ddb/ddb.h> 455 456DB_SHOW_COMMAND(rtc, rtc) 457{ 458 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 459 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 460 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 461 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 462} 463#endif /* DDB */ 464#endif /* for PC98 */ 465 466static int 467getit(void) 468{ 469 u_long ef; 470 int high, low; 471 472 ef = read_eflags(); 473 disable_intr(); 474 475 /* Select timer0 and latch counter value. */ 476 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 477 478 low = inb(TIMER_CNTR0); 479 high = inb(TIMER_CNTR0); 480 481 CLOCK_UNLOCK(); 482 write_eflags(ef); 483 return ((high << 8) | low); 484} 485 486/* 487 * Wait "n" microseconds. 488 * Relies on timer 1 counting down from (timer_freq / hz) 489 * Note: timer had better have been programmed before this is first used! 490 */ 491void 492DELAY(int n) 493{ 494 int delta, prev_tick, tick, ticks_left; 495 496#ifdef DELAYDEBUG 497 int getit_calls = 1; 498 int n1; 499 static int state = 0; 500 501 if (state == 0) { 502 state = 1; 503 for (n1 = 1; n1 <= 10000000; n1 *= 10) 504 DELAY(n1); 505 state = 2; 506 } 507 if (state == 1) 508 printf("DELAY(%d)...", n); 509#endif 510 /* 511 * Guard against the timer being uninitialized if we are called 512 * early for console i/o. 513 */ 514 if (timer0_max_count == 0) 515 set_timer_freq(timer_freq, hz); 516 517 /* 518 * Read the counter first, so that the rest of the setup overhead is 519 * counted. Guess the initial overhead is 20 usec (on most systems it 520 * takes about 1.5 usec for each of the i/o's in getit(). The loop 521 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 522 * multiplications and divisions to scale the count take a while). 523 */ 524 prev_tick = getit(); 525 n -= 0; /* XXX actually guess no initial overhead */ 526 /* 527 * Calculate (n * (timer_freq / 1e6)) without using floating point 528 * and without any avoidable overflows. 529 */ 530 if (n <= 0) 531 ticks_left = 0; 532 else if (n < 256) 533 /* 534 * Use fixed point to avoid a slow division by 1000000. 535 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 536 * 2^15 is the first power of 2 that gives exact results 537 * for n between 0 and 256. 538 */ 539 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 540 else 541 /* 542 * Don't bother using fixed point, although gcc-2.7.2 543 * generates particularly poor code for the long long 544 * division, since even the slow way will complete long 545 * before the delay is up (unless we're interrupted). 546 */ 547 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 548 / 1000000; 549 550 while (ticks_left > 0) { 551 tick = getit(); 552#ifdef DELAYDEBUG 553 ++getit_calls; 554#endif 555 delta = prev_tick - tick; 556 prev_tick = tick; 557 if (delta < 0) { 558 delta += timer0_max_count; 559 /* 560 * Guard against timer0_max_count being wrong. 561 * This shouldn't happen in normal operation, 562 * but it may happen if set_timer_freq() is 563 * traced. 564 */ 565 if (delta < 0) 566 delta = 0; 567 } 568 ticks_left -= delta; 569 } 570#ifdef DELAYDEBUG 571 if (state == 1) 572 printf(" %d calls to getit() at %d usec each\n", 573 getit_calls, (n + 5) / getit_calls); 574#endif 575} 576 577static void 578sysbeepstop(void *chan) 579{ 580#ifdef PC98 /* PC98 */ 581 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 582 release_timer1(); 583#else 584 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 585 release_timer2(); 586#endif 587 beeping = 0; 588} 589 590int 591sysbeep(int pitch, int period) 592{ 593 int x = splclock(); 594 595#ifdef PC98 596 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 597 if (!beeping) { 598 /* Something else owns it. */ 599 splx(x); 600 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 601 } 602 disable_intr(); 603 outb(0x3fdb, pitch); 604 outb(0x3fdb, (pitch>>8)); 605 enable_intr(); 606 if (!beeping) { 607 /* enable counter1 output to speaker */ 608 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 609 beeping = period; 610 timeout(sysbeepstop, (void *)NULL, period); 611 } 612#else 613 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 614 if (!beeping) { 615 /* Something else owns it. */ 616 splx(x); 617 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 618 } 619 disable_intr(); 620 outb(TIMER_CNTR2, pitch); 621 outb(TIMER_CNTR2, (pitch>>8)); 622 enable_intr(); 623 if (!beeping) { 624 /* enable counter2 output to speaker */ 625 outb(IO_PPI, inb(IO_PPI) | 3); 626 beeping = period; 627 timeout(sysbeepstop, (void *)NULL, period); 628 } 629#endif 630 splx(x); 631 return (0); 632} 633 634#ifndef PC98 635/* 636 * RTC support routines 637 */ 638 639int 640rtcin(reg) 641 int reg; 642{ 643 u_char val; 644 645 outb(IO_RTC, reg); 646 inb(0x84); 647 val = inb(IO_RTC + 1); 648 inb(0x84); 649 return (val); 650} 651 652static __inline void 653writertc(u_char reg, u_char val) 654{ 655 inb(0x84); 656 outb(IO_RTC, reg); 657 inb(0x84); 658 outb(IO_RTC + 1, val); 659 inb(0x84); /* XXX work around wrong order in rtcin() */ 660} 661 662static __inline int 663readrtc(int port) 664{ 665 return(bcd2bin(rtcin(port))); 666} 667#endif 668 669#ifdef PC98 670unsigned int delaycount; 671#define FIRST_GUESS 0x2000 672static void findcpuspeed(void) 673{ 674 int i; 675 int remainder; 676 677 /* Put counter in count down mode */ 678 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 679 outb(TIMER_CNTR0, 0xff); 680 outb(TIMER_CNTR0, 0xff); 681 for (i = FIRST_GUESS; i; i--) 682 ; 683 remainder = getit(); 684 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 685} 686#endif 687 688#ifndef PC98 689static u_int 690calibrate_clocks(void) 691{ 692 u_int count, prev_count, tot_count; 693 int sec, start_sec, timeout; 694 695 if (bootverbose) 696 printf("Calibrating clock(s) ... "); 697 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 698 goto fail; 699 timeout = 100000000; 700 701 /* Read the mc146818A seconds counter. */ 702 for (;;) { 703 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 704 sec = rtcin(RTC_SEC); 705 break; 706 } 707 if (--timeout == 0) 708 goto fail; 709 } 710 711 /* Wait for the mC146818A seconds counter to change. */ 712 start_sec = sec; 713 for (;;) { 714 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 715 sec = rtcin(RTC_SEC); 716 if (sec != start_sec) 717 break; 718 } 719 if (--timeout == 0) 720 goto fail; 721 } 722 723 /* Start keeping track of the i8254 counter. */ 724 prev_count = getit(); 725 if (prev_count == 0 || prev_count > timer0_max_count) 726 goto fail; 727 tot_count = 0; 728 729 if (tsc_present) 730 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 731 732 /* 733 * Wait for the mc146818A seconds counter to change. Read the i8254 734 * counter for each iteration since this is convenient and only 735 * costs a few usec of inaccuracy. The timing of the final reads 736 * of the counters almost matches the timing of the initial reads, 737 * so the main cause of inaccuracy is the varying latency from 738 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 739 * rtcin(RTC_SEC) that returns a changed seconds count. The 740 * maximum inaccuracy from this cause is < 10 usec on 486's. 741 */ 742 start_sec = sec; 743 for (;;) { 744 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 745 sec = rtcin(RTC_SEC); 746 count = getit(); 747 if (count == 0 || count > timer0_max_count) 748 goto fail; 749 if (count > prev_count) 750 tot_count += prev_count - (count - timer0_max_count); 751 else 752 tot_count += prev_count - count; 753 prev_count = count; 754 if (sec != start_sec) 755 break; 756 if (--timeout == 0) 757 goto fail; 758 } 759 760 /* 761 * Read the cpu cycle counter. The timing considerations are 762 * similar to those for the i8254 clock. 763 */ 764 if (tsc_present) 765 tsc_freq = rdtsc(); 766 767 if (bootverbose) { 768 printf("i8254 clock: %u Hz\n", tot_count); 769 if (tsc_present) 770 printf("TSC clock: %u Hz, ", tsc_freq); 771 } 772 return (tot_count); 773 774fail: 775 if (bootverbose) 776 printf("failed, using default i8254 clock of %u Hz\n", 777 timer_freq); 778 return (timer_freq); 779} 780#endif /* !PC98 */ 781 782static void 783set_timer_freq(u_int freq, int intr_freq) 784{ 785 u_long ef; 786 int new_timer0_max_count; 787 788 ef = read_eflags(); 789 disable_intr(); 790 timer_freq = freq; 791 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 792 if (new_timer0_max_count != timer0_max_count) { 793 timer0_max_count = new_timer0_max_count; 794 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 795 outb(TIMER_CNTR0, timer0_max_count & 0xff); 796 outb(TIMER_CNTR0, timer0_max_count >> 8); 797 } 798 CLOCK_UNLOCK(); 799 write_eflags(ef); 800} 801 802/* 803 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 804 * XXX initialization of other timers is unintentionally left blank. 805 */ 806void 807startrtclock() 808{ 809 u_int delta, freq; 810 811#ifdef PC98 812 findcpuspeed(); 813#ifndef AUTO_CLOCK 814 if (pc98_machine_type & M_8M) { 815#ifndef PC98_8M 816 printf("you must reconfig a kernel with \"PC98_8M\" option.\n"); 817#endif 818 } else { 819#ifdef PC98_8M 820 printf("You must reconfig a kernel without \"PC98_8M\" option.\n"); 821#endif 822 } 823#else /* AUTO_CLOCK */ 824 if (pc98_machine_type & M_8M) 825 timer_freq = 1996800L; /* 1.9968 MHz */ 826 else 827 timer_freq = 2457600L; /* 2.4576 MHz */ 828#endif /* AUTO_CLOCK */ 829#endif /* PC98 */ 830 831 if (cpu_feature & CPUID_TSC) 832 tsc_present = 1; 833 else 834 tsc_present = 0; 835 836#ifdef SMP 837 tsc_present = 0; 838#endif 839 840#ifndef PC98 841 writertc(RTC_STATUSA, rtc_statusa); 842 writertc(RTC_STATUSB, RTCSB_24HR); 843#endif 844 845#ifndef PC98 846 set_timer_freq(timer_freq, hz); 847 freq = calibrate_clocks(); 848#ifdef CLK_CALIBRATION_LOOP 849 if (bootverbose) { 850 printf( 851 "Press a key on the console to abort clock calibration\n"); 852 while (cncheckc() == -1) 853 calibrate_clocks(); 854 } 855#endif 856 857 /* 858 * Use the calibrated i8254 frequency if it seems reasonable. 859 * Otherwise use the default, and don't use the calibrated i586 860 * frequency. 861 */ 862 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 863 if (delta < timer_freq / 100) { 864#ifndef CLK_USE_I8254_CALIBRATION 865 if (bootverbose) 866 printf( 867"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 868 freq = timer_freq; 869#endif 870 timer_freq = freq; 871 } else { 872 if (bootverbose) 873 printf( 874 "%d Hz differs from default of %d Hz by more than 1%%\n", 875 freq, timer_freq); 876 tsc_freq = 0; 877 } 878#endif 879 880 set_timer_freq(timer_freq, hz); 881 i8254_timecounter[0].frequency = timer_freq; 882 init_timecounter(i8254_timecounter); 883 884#ifndef CLK_USE_TSC_CALIBRATION 885 if (tsc_freq != 0) { 886 if (bootverbose) 887 printf( 888"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 889 tsc_freq = 0; 890 } 891#endif 892 if (tsc_present && tsc_freq == 0) { 893 /* 894 * Calibration of the i586 clock relative to the mc146818A 895 * clock failed. Do a less accurate calibration relative 896 * to the i8254 clock. 897 */ 898 wrmsr(0x10, 0LL); /* XXX */ 899 DELAY(1000000); 900 tsc_freq = rdtsc(); 901#ifdef CLK_USE_TSC_CALIBRATION 902 if (bootverbose) 903 printf("TSC clock: %u Hz (Method B)\n", tsc_freq); 904#endif 905 } 906 if (tsc_present && tsc_freq != 0) { 907 tsc_timecounter[0].frequency = tsc_freq; 908 init_timecounter(tsc_timecounter); 909 } 910} 911 912#ifdef PC98 913static void 914rtc_serialcombit(int i) 915{ 916 outb(IO_RTC, ((i&0x01)<<5)|0x07); 917 DELAY(1); 918 outb(IO_RTC, ((i&0x01)<<5)|0x17); 919 DELAY(1); 920 outb(IO_RTC, ((i&0x01)<<5)|0x07); 921 DELAY(1); 922} 923 924static void 925rtc_serialcom(int i) 926{ 927 rtc_serialcombit(i&0x01); 928 rtc_serialcombit((i&0x02)>>1); 929 rtc_serialcombit((i&0x04)>>2); 930 rtc_serialcombit((i&0x08)>>3); 931 outb(IO_RTC, 0x07); 932 DELAY(1); 933 outb(IO_RTC, 0x0f); 934 DELAY(1); 935 outb(IO_RTC, 0x07); 936 DELAY(1); 937} 938 939static void 940rtc_outb(int val) 941{ 942 int s; 943 int sa = 0; 944 945 for (s=0;s<8;s++) { 946 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 947 outb(IO_RTC, sa); /* set DI & CLK 0 */ 948 DELAY(1); 949 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 950 DELAY(1); 951 } 952 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 953} 954 955static int 956rtc_inb(void) 957{ 958 int s; 959 int sa = 0; 960 961 for (s=0;s<8;s++) { 962 sa |= ((inb(0x33) & 0x01) << s); 963 outb(IO_RTC, 0x17); /* CLK 1 */ 964 DELAY(1); 965 outb(IO_RTC, 0x07); /* CLK 0 */ 966 DELAY(2); 967 } 968 return sa; 969} 970#endif /* PC-98 */ 971 972/* 973 * Initialize the time of day register, based on the time base which is, e.g. 974 * from a filesystem. 975 */ 976void 977inittodr(time_t base) 978{ 979 unsigned long sec, days; 980 int yd; 981 int year, month; 982 int y, m, s; 983 struct timespec ts; 984#ifdef PC98 985 int second, min, hour; 986#endif 987 988 if (base) { 989 s = splclock(); 990 ts.tv_sec = base; 991 ts.tv_nsec = 0; 992 set_timecounter(&ts); 993 splx(s); 994 } 995 996#ifdef PC98 997 rtc_serialcom(0x03); /* Time Read */ 998 rtc_serialcom(0x01); /* Register shift command. */ 999 DELAY(20); 1000 1001 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 1002 min = bcd2bin(rtc_inb() & 0xff); /* min */ 1003 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 1004 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 1005 1006 month = (rtc_inb() >> 4) & 0x0f; /* month */ 1007 for (m = 1; m < month; m++) 1008 days += daysinmonth[m-1]; 1009 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 1010 /* 2000 year problem */ 1011 if (year < 1995) 1012 year += 100; 1013 if (year < 1970) 1014 goto wrong_time; 1015 for (y = 1970; y < year; y++) 1016 days += DAYSPERYEAR + LEAPYEAR(y); 1017 if ((month > 2) && LEAPYEAR(year)) 1018 days ++; 1019 sec = ((( days * 24 + 1020 hour) * 60 + 1021 min) * 60 + 1022 second); 1023 /* sec now contains the number of seconds, since Jan 1 1970, 1024 in the local time zone */ 1025#else /* IBM-PC */ 1026 /* Look if we have a RTC present and the time is valid */ 1027 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 1028 goto wrong_time; 1029 1030 /* wait for time update to complete */ 1031 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 1032 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 1033 1034 days = 0; 1035#ifdef USE_RTC_CENTURY 1036 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 1037#else 1038 year = readrtc(RTC_YEAR) + 1900; 1039 if (year < 1970) 1040 year += 100; 1041#endif 1042 if (year < 1970) 1043 goto wrong_time; 1044 month = readrtc(RTC_MONTH); 1045 for (m = 1; m < month; m++) 1046 days += daysinmonth[m-1]; 1047 if ((month > 2) && LEAPYEAR(year)) 1048 days ++; 1049 days += readrtc(RTC_DAY) - 1; 1050 yd = days; 1051 for (y = 1970; y < year; y++) 1052 days += DAYSPERYEAR + LEAPYEAR(y); 1053 sec = ((( days * 24 + 1054 readrtc(RTC_HRS)) * 60 + 1055 readrtc(RTC_MIN)) * 60 + 1056 readrtc(RTC_SEC)); 1057 /* sec now contains the number of seconds, since Jan 1 1970, 1058 in the local time zone */ 1059#endif 1060 1061 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1062 1063 y = time.tv_sec - sec; 1064 if (y <= -2 || y >= 2) { 1065 /* badly off, adjust it */ 1066 s = splclock(); 1067 ts.tv_sec = sec; 1068 ts.tv_nsec = 0; 1069 set_timecounter(&ts); 1070 splx(s); 1071 } 1072 return; 1073 1074wrong_time: 1075 printf("Invalid time in real time clock.\n"); 1076 printf("Check and reset the date immediately!\n"); 1077} 1078 1079/* 1080 * Write system time back to RTC 1081 */ 1082void 1083resettodr() 1084{ 1085 unsigned long tm; 1086 int y, m, s; 1087#ifdef PC98 1088 int wd; 1089#endif 1090 1091 if (disable_rtc_set) 1092 return; 1093 1094 s = splclock(); 1095 tm = time.tv_sec; 1096 splx(s); 1097 1098#ifdef PC98 1099 rtc_serialcom(0x01); /* Register shift command. */ 1100 1101 /* Calculate local time to put in RTC */ 1102 1103 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1104 1105 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1106 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1107 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1108 1109 /* We have now the days since 01-01-1970 in tm */ 1110 wd = (tm+4)%7; 1111 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1112 tm >= m; 1113 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1114 tm -= m; 1115 1116 /* Now we have the years in y and the day-of-the-year in tm */ 1117 for (m = 0; ; m++) { 1118 int ml; 1119 1120 ml = daysinmonth[m]; 1121 if (m == 1 && LEAPYEAR(y)) 1122 ml++; 1123 if (tm < ml) 1124 break; 1125 tm -= ml; 1126 } 1127 1128 m++; 1129 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1130 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1131 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1132 1133 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1134 rtc_serialcom(0x00); /* Register hold command. */ 1135#else 1136 /* Disable RTC updates and interrupts. */ 1137 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1138 1139 /* Calculate local time to put in RTC */ 1140 1141 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1142 1143 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1144 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1145 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1146 1147 /* We have now the days since 01-01-1970 in tm */ 1148 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1149 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1150 tm >= m; 1151 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1152 tm -= m; 1153 1154 /* Now we have the years in y and the day-of-the-year in tm */ 1155 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1156#ifdef USE_RTC_CENTURY 1157 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1158#endif 1159 for (m = 0; ; m++) { 1160 int ml; 1161 1162 ml = daysinmonth[m]; 1163 if (m == 1 && LEAPYEAR(y)) 1164 ml++; 1165 if (tm < ml) 1166 break; 1167 tm -= ml; 1168 } 1169 1170 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1171 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1172 1173 /* Reenable RTC updates and interrupts. */ 1174 writertc(RTC_STATUSB, rtc_statusb); 1175#endif 1176} 1177 1178 1179/* 1180 * Start both clocks running. 1181 */ 1182void 1183cpu_initclocks() 1184{ 1185#ifdef APIC_IO 1186 int x; 1187#endif /* APIC_IO */ 1188#ifndef PC98 1189 int diag; 1190 1191 if (statclock_disable) { 1192 /* 1193 * The stat interrupt mask is different without the 1194 * statistics clock. Also, don't set the interrupt 1195 * flag which would normally cause the RTC to generate 1196 * interrupts. 1197 */ 1198 stat_imask = HWI_MASK | SWI_MASK; 1199 rtc_statusb = RTCSB_24HR; 1200 } else { 1201 /* Setting stathz to nonzero early helps avoid races. */ 1202 stathz = RTC_NOPROFRATE; 1203 profhz = RTC_PROFRATE; 1204 } 1205#endif 1206 1207 /* Finish initializing 8253 timer 0. */ 1208#ifdef APIC_IO 1209 1210 /* 1st look for ExtInt on pin 0 */ 1211 if (apic_int_type(0, 0) == 3) { 1212 /* 1213 * Allow 8254 timer to INTerrupt 8259: 1214 * re-initialize master 8259: 1215 * reset; prog 4 bytes, single ICU, edge triggered 1216 */ 1217 outb(IO_ICU1, 0x13); 1218 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */ 1219 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1220 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1221 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1222 1223 /* program IO APIC for type 3 INT on INT0 */ 1224 if (ext_int_setup(0, 0) < 0) 1225 panic("8254 redirect via APIC pin0 impossible!"); 1226 1227 x = 0; 1228 /* XXX if (bootverbose) */ 1229 printf("APIC_IO: routing 8254 via 8259 on pin 0\n"); 1230 } 1231 1232 /* failing that, look for 8254 on pin 2 */ 1233 else if (isa_apic_pin(0) == 2) { 1234 x = 2; 1235 /* XXX if (bootverbose) */ 1236 printf("APIC_IO: routing 8254 via pin 2\n"); 1237 } 1238 1239 /* better write that 8254 INT discover code... */ 1240 else 1241 panic("neither pin 0 or pin 2 works for 8254"); 1242 1243 /* setup the vectors */ 1244 vec[x] = (u_int)vec8254; 1245 Xintr8254 = (u_int)ivectors[x]; 1246 mask8254 = (1 << x); 1247 1248 register_intr(/* irq */ x, /* XXX id */ 0, /* flags */ 0, 1249 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1250 /* unit */ 0); 1251 INTREN(mask8254); 1252 1253#else /* APIC_IO */ 1254 1255 register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, 1256 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1257 /* unit */ 0); 1258 INTREN(IRQ0); 1259 1260#endif /* APIC_IO */ 1261 1262#ifndef PC98 1263 /* Initialize RTC. */ 1264 writertc(RTC_STATUSA, rtc_statusa); 1265 writertc(RTC_STATUSB, RTCSB_24HR); 1266 1267 /* Don't bother enabling the statistics clock. */ 1268 if (statclock_disable) 1269 return; 1270 diag = rtcin(RTC_DIAG); 1271 if (diag != 0) 1272 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1273 1274#ifdef APIC_IO 1275 if (isa_apic_pin(8) != 8) 1276 panic("APIC RTC != 8"); 1277#endif /* APIC_IO */ 1278 1279 register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, 1280 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1281 /* unit */ 0); 1282 1283#ifdef APIC_IO 1284 INTREN(APIC_IRQ8); 1285#else 1286 INTREN(IRQ8); 1287#endif /* APIC_IO */ 1288 1289 writertc(RTC_STATUSB, rtc_statusb); 1290#endif /* !PC98 */ 1291} 1292 1293void 1294setstatclockrate(int newhz) 1295{ 1296#ifndef PC98 1297 if (newhz == RTC_PROFRATE) 1298 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1299 else 1300 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1301 writertc(RTC_STATUSA, rtc_statusa); 1302#endif 1303} 1304 1305static int 1306sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1307{ 1308 int error; 1309 u_int freq; 1310 1311 /* 1312 * Use `i8254' instead of `timer' in external names because `timer' 1313 * is is too generic. Should use it everywhere. 1314 */ 1315 freq = timer_freq; 1316 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1317 if (error == 0 && req->newptr != NULL) { 1318 if (timer0_state != RELEASED) 1319 return (EBUSY); /* too much trouble to handle */ 1320 set_timer_freq(freq, hz); 1321 i8254_timecounter[0].frequency = freq; 1322 } 1323 return (error); 1324} 1325 1326SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1327 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1328 1329static int 1330sysctl_machdep_tsc_freq SYSCTL_HANDLER_ARGS 1331{ 1332 int error; 1333 u_int freq; 1334 1335 if (!tsc_present) 1336 return (EOPNOTSUPP); 1337 freq = tsc_freq; 1338 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1339 if (error == 0 && req->newptr != NULL) { 1340 tsc_freq = freq; 1341 tsc_timecounter[0].frequency = tsc_freq; 1342 } 1343 return (error); 1344} 1345 1346SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW, 1347 0, sizeof(u_int), sysctl_machdep_tsc_freq, "I", ""); 1348 1349static u_int64_t 1350i8254_get_timecount(void) 1351{ 1352 u_int32_t count; 1353 u_long ef; 1354 u_int high, low; 1355 1356 ef = read_eflags(); 1357 disable_intr(); 1358 1359 /* Select timer0 and latch counter value. */ 1360 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 1361 1362 low = inb(TIMER_CNTR0); 1363 high = inb(TIMER_CNTR0); 1364 1365 count = hardclock_max_count - ((high << 8) | low); 1366 if (count < i8254_lastcount) { 1367 i8254_ticked = 1; 1368 i8254_offset += hardclock_max_count; 1369 } 1370 1371 i8254_lastcount = count; 1372 count += i8254_offset; 1373 CLOCK_UNLOCK(); 1374 write_eflags(ef); 1375 return (count); 1376} 1377 1378static u_int64_t 1379tsc_get_timecount(void) 1380{ 1381 return ((u_int64_t)rdtsc()); 1382} 1383 1384static u_int32_t 1385tsc_get_timedelta(struct timecounter *tc) 1386{ 1387 return ((u_int64_t)rdtsc() - tc->offset_count); 1388} 1389