pcrtc.c revision 31293
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $Id: clock.c,v 1.36 1997/10/28 14:30:46 kato Exp $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51/* 52 * modified for PC98 by Kakefuda 53 */ 54 55#include "opt_clock.h" 56 57#include <sys/param.h> 58#include <sys/systm.h> 59#include <sys/time.h> 60#include <sys/kernel.h> 61#ifndef SMP 62#include <sys/lock.h> 63#endif 64#include <sys/sysctl.h> 65 66#include <machine/clock.h> 67#ifdef CLK_CALIBRATION_LOOP 68#include <machine/cons.h> 69#endif 70#include <machine/cputypes.h> 71#include <machine/frame.h> 72#include <machine/ipl.h> 73#include <machine/limits.h> 74#ifdef APIC_IO 75#include <machine/segments.h> 76#endif 77#if defined(SMP) || defined(APIC_IO) 78#include <machine/smp.h> 79#endif /* SMP || APIC_IO */ 80 81#include <i386/isa/icu.h> 82#ifdef PC98 83#include <pc98/pc98/pc98.h> 84#include <pc98/pc98/pc98_machdep.h> 85#include <i386/isa/isa_device.h> 86#else 87#include <i386/isa/isa.h> 88#include <i386/isa/rtc.h> 89#endif 90#include <i386/isa/timerreg.h> 91 92#include <sys/interrupt.h> 93 94#ifdef SMP 95#define disable_intr() CLOCK_DISABLE_INTR() 96#define enable_intr() CLOCK_ENABLE_INTR() 97#endif /* SMP */ 98 99/* 100 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 101 * can use a simple formula for leap years. 102 */ 103#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 104#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 105 106#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 107 108/* 109 * Time in timer cycles that it takes for microtime() to disable interrupts 110 * and latch the count. microtime() currently uses "cli; outb ..." so it 111 * normally takes less than 2 timer cycles. Add a few for cache misses. 112 * Add a few more to allow for latency in bogus calls to microtime() with 113 * interrupts already disabled. 114 */ 115#define TIMER0_LATCH_COUNT 20 116 117/* 118 * Maximum frequency that we are willing to allow for timer0. Must be 119 * low enough to guarantee that the timer interrupt handler returns 120 * before the next timer interrupt. Must result in a lower TIMER_DIV 121 * value than TIMER0_LATCH_COUNT so that we don't have to worry about 122 * underflow in the calculation of timer0_overflow_threshold. 123 */ 124#define TIMER0_MAX_FREQ 20000 125 126int adjkerntz; /* local offset from GMT in seconds */ 127int disable_rtc_set; /* disable resettodr() if != 0 */ 128u_int idelayed; 129#if defined(I586_CPU) || defined(I686_CPU) 130#ifndef SMP 131u_int i586_ctr_bias; 132u_int i586_ctr_comultiplier; 133#endif 134u_int i586_ctr_freq; 135#ifndef SMP 136u_int i586_ctr_multiplier; 137#endif 138#endif 139int statclock_disable; 140u_int stat_imask = SWI_CLOCK_MASK; 141#ifdef TIMER_FREQ 142u_int timer_freq = TIMER_FREQ; 143#else 144#ifdef PC98 145#ifndef AUTO_CLOCK 146#ifndef PC98_8M 147u_int timer_freq = 2457600; 148#else /* !PC98_8M */ 149u_int timer_freq = 1996800; 150#endif /* PC98_8M */ 151#else /* AUTO_CLOCK */ 152u_int timer_freq = 2457600; 153#endif /* AUTO_CLOCK */ 154#else /* IBM-PC */ 155u_int timer_freq = 1193182; 156#endif /* PC98 */ 157#endif 158int timer0_max_count; 159u_int timer0_overflow_threshold; 160u_int timer0_prescaler_count; 161int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 162 163static int beeping = 0; 164static u_int clk_imask = HWI_MASK | SWI_MASK; 165static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 166static u_int hardclock_max_count; 167/* 168 * XXX new_function and timer_func should not handle clockframes, but 169 * timer_func currently needs to hold hardclock to handle the 170 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 171 * to switch between clkintr() and a slightly different timerintr(). 172 */ 173static void (*new_function) __P((struct clockframe *frame)); 174static u_int new_rate; 175#ifndef PC98 176static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 177static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 178#endif 179 180/* Values for timerX_state: */ 181#define RELEASED 0 182#define RELEASE_PENDING 1 183#define ACQUIRED 2 184#define ACQUIRE_PENDING 3 185 186static u_char timer0_state; 187#ifdef PC98 188static u_char timer1_state; 189#endif 190static u_char timer2_state; 191static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 192#ifdef PC98 193static void rtc_serialcombit __P((int)); 194static void rtc_serialcom __P((int)); 195static int rtc_inb __P((void)); 196static void rtc_outb __P((int)); 197#endif 198 199#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 200static void set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq); 201#endif 202static void set_timer_freq(u_int freq, int intr_freq); 203 204static void 205clkintr(struct clockframe frame) 206{ 207 timer_func(&frame); 208 switch (timer0_state) { 209 210 case RELEASED: 211 setdelayed(); 212 break; 213 214 case ACQUIRED: 215 if ((timer0_prescaler_count += timer0_max_count) 216 >= hardclock_max_count) { 217 hardclock(&frame); 218 setdelayed(); 219 timer0_prescaler_count -= hardclock_max_count; 220 } 221 break; 222 223 case ACQUIRE_PENDING: 224 setdelayed(); 225 timer0_max_count = TIMER_DIV(new_rate); 226 timer0_overflow_threshold = 227 timer0_max_count - TIMER0_LATCH_COUNT; 228 disable_intr(); 229 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 230 outb(TIMER_CNTR0, timer0_max_count & 0xff); 231 outb(TIMER_CNTR0, timer0_max_count >> 8); 232 enable_intr(); 233 timer0_prescaler_count = 0; 234 timer_func = new_function; 235 timer0_state = ACQUIRED; 236 break; 237 238 case RELEASE_PENDING: 239 if ((timer0_prescaler_count += timer0_max_count) 240 >= hardclock_max_count) { 241 hardclock(&frame); 242 setdelayed(); 243 timer0_max_count = hardclock_max_count; 244 timer0_overflow_threshold = 245 timer0_max_count - TIMER0_LATCH_COUNT; 246 disable_intr(); 247 outb(TIMER_MODE, 248 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 249 outb(TIMER_CNTR0, timer0_max_count & 0xff); 250 outb(TIMER_CNTR0, timer0_max_count >> 8); 251 enable_intr(); 252 /* 253 * See microtime.s for this magic. 254 */ 255#ifdef PC98 256#ifndef AUTO_CLOCK 257#ifndef PC98_8M 258 time.tv_usec += (6667 * 259 (timer0_prescaler_count - hardclock_max_count)) 260 >> 14; 261#else /* PC98_8M */ 262 time.tv_usec += (16411 * 263 (timer0_prescaler_count - hardclock_max_count)) 264 >> 15; 265#endif /* PC98_8M */ 266#else /* AUTO_CLOCK */ 267 if (pc98_machine_type & M_8M) { 268 /* PC98_8M */ 269 time.tv_usec += (16411 * 270 (timer0_prescaler_count - 271 hardclock_max_count)) >> 15; 272 } else { 273 time.tv_usec += (6667 * 274 (timer0_prescaler_count - 275 hardclock_max_count)) >> 14; 276 } 277#endif /* AUTO_CLOCK */ 278#else /* IBM-PC */ 279 time.tv_usec += (27465 * 280 (timer0_prescaler_count - hardclock_max_count)) 281 >> 15; 282#endif /* PC98 */ 283 if (time.tv_usec >= 1000000) 284 time.tv_usec -= 1000000; 285 timer0_prescaler_count = 0; 286 timer_func = hardclock; 287 timer0_state = RELEASED; 288 } 289 break; 290 } 291} 292 293/* 294 * The acquire and release functions must be called at ipl >= splclock(). 295 */ 296int 297acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 298{ 299 static int old_rate; 300 301 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 302 return (-1); 303 switch (timer0_state) { 304 305 case RELEASED: 306 timer0_state = ACQUIRE_PENDING; 307 break; 308 309 case RELEASE_PENDING: 310 if (rate != old_rate) 311 return (-1); 312 /* 313 * The timer has been released recently, but is being 314 * re-acquired before the release completed. In this 315 * case, we simply reclaim it as if it had not been 316 * released at all. 317 */ 318 timer0_state = ACQUIRED; 319 break; 320 321 default: 322 return (-1); /* busy */ 323 } 324 new_function = function; 325 old_rate = new_rate = rate; 326 return (0); 327} 328 329#ifdef PC98 330int 331acquire_timer1(int mode) 332{ 333 334 if (timer1_state != RELEASED) 335 return (-1); 336 timer1_state = ACQUIRED; 337 338 /* 339 * This access to the timer registers is as atomic as possible 340 * because it is a single instruction. We could do better if we 341 * knew the rate. Use of splclock() limits glitches to 10-100us, 342 * and this is probably good enough for timer2, so we aren't as 343 * careful with it as with timer0. 344 */ 345 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 346 347 return (0); 348} 349#endif 350 351int 352acquire_timer2(int mode) 353{ 354 355 if (timer2_state != RELEASED) 356 return (-1); 357 timer2_state = ACQUIRED; 358 359 /* 360 * This access to the timer registers is as atomic as possible 361 * because it is a single instruction. We could do better if we 362 * knew the rate. Use of splclock() limits glitches to 10-100us, 363 * and this is probably good enough for timer2, so we aren't as 364 * careful with it as with timer0. 365 */ 366 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 367 368 return (0); 369} 370 371int 372release_timer0() 373{ 374 switch (timer0_state) { 375 376 case ACQUIRED: 377 timer0_state = RELEASE_PENDING; 378 break; 379 380 case ACQUIRE_PENDING: 381 /* Nothing happened yet, release quickly. */ 382 timer0_state = RELEASED; 383 break; 384 385 default: 386 return (-1); 387 } 388 return (0); 389} 390 391#ifdef PC98 392int 393release_timer1() 394{ 395 396 if (timer1_state != ACQUIRED) 397 return (-1); 398 timer1_state = RELEASED; 399 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 400 return (0); 401} 402#endif 403 404int 405release_timer2() 406{ 407 408 if (timer2_state != ACQUIRED) 409 return (-1); 410 timer2_state = RELEASED; 411 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 412 return (0); 413} 414 415#ifndef PC98 416/* 417 * This routine receives statistical clock interrupts from the RTC. 418 * As explained above, these occur at 128 interrupts per second. 419 * When profiling, we receive interrupts at a rate of 1024 Hz. 420 * 421 * This does not actually add as much overhead as it sounds, because 422 * when the statistical clock is active, the hardclock driver no longer 423 * needs to keep (inaccurate) statistics on its own. This decouples 424 * statistics gathering from scheduling interrupts. 425 * 426 * The RTC chip requires that we read status register C (RTC_INTR) 427 * to acknowledge an interrupt, before it will generate the next one. 428 * Under high interrupt load, rtcintr() can be indefinitely delayed and 429 * the clock can tick immediately after the read from RTC_INTR. In this 430 * case, the mc146818A interrupt signal will not drop for long enough 431 * to register with the 8259 PIC. If an interrupt is missed, the stat 432 * clock will halt, considerably degrading system performance. This is 433 * why we use 'while' rather than a more straightforward 'if' below. 434 * Stat clock ticks can still be lost, causing minor loss of accuracy 435 * in the statistics, but the stat clock will no longer stop. 436 */ 437static void 438rtcintr(struct clockframe frame) 439{ 440 while (rtcin(RTC_INTR) & RTCIR_PERIOD) 441 statclock(&frame); 442} 443 444#include "opt_ddb.h" 445#ifdef DDB 446#include <ddb/ddb.h> 447 448DB_SHOW_COMMAND(rtc, rtc) 449{ 450 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 451 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 452 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 453 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 454} 455#endif /* DDB */ 456#endif /* for PC98 */ 457 458static int 459getit(void) 460{ 461 u_long ef; 462 int high, low; 463 464 ef = read_eflags(); 465 disable_intr(); 466 467 /* Select timer0 and latch counter value. */ 468 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 469 470 low = inb(TIMER_CNTR0); 471 high = inb(TIMER_CNTR0); 472 473 CLOCK_UNLOCK(); 474 write_eflags(ef); 475 return ((high << 8) | low); 476} 477 478/* 479 * Wait "n" microseconds. 480 * Relies on timer 1 counting down from (timer_freq / hz) 481 * Note: timer had better have been programmed before this is first used! 482 */ 483void 484DELAY(int n) 485{ 486 int delta, prev_tick, tick, ticks_left; 487 488#ifdef DELAYDEBUG 489 int getit_calls = 1; 490 int n1; 491 static int state = 0; 492 493 if (state == 0) { 494 state = 1; 495 for (n1 = 1; n1 <= 10000000; n1 *= 10) 496 DELAY(n1); 497 state = 2; 498 } 499 if (state == 1) 500 printf("DELAY(%d)...", n); 501#endif 502 /* 503 * Guard against the timer being uninitialized if we are called 504 * early for console i/o. 505 */ 506 if (timer0_max_count == 0) 507 set_timer_freq(timer_freq, hz); 508 509 /* 510 * Read the counter first, so that the rest of the setup overhead is 511 * counted. Guess the initial overhead is 20 usec (on most systems it 512 * takes about 1.5 usec for each of the i/o's in getit(). The loop 513 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 514 * multiplications and divisions to scale the count take a while). 515 */ 516 prev_tick = getit(); 517 n -= 0; /* XXX actually guess no initial overhead */ 518 /* 519 * Calculate (n * (timer_freq / 1e6)) without using floating point 520 * and without any avoidable overflows. 521 */ 522 if (n <= 0) 523 ticks_left = 0; 524 else if (n < 256) 525 /* 526 * Use fixed point to avoid a slow division by 1000000. 527 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 528 * 2^15 is the first power of 2 that gives exact results 529 * for n between 0 and 256. 530 */ 531 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 532 else 533 /* 534 * Don't bother using fixed point, although gcc-2.7.2 535 * generates particularly poor code for the long long 536 * division, since even the slow way will complete long 537 * before the delay is up (unless we're interrupted). 538 */ 539 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 540 / 1000000; 541 542 while (ticks_left > 0) { 543 tick = getit(); 544#ifdef DELAYDEBUG 545 ++getit_calls; 546#endif 547 delta = prev_tick - tick; 548 prev_tick = tick; 549 if (delta < 0) { 550 delta += timer0_max_count; 551 /* 552 * Guard against timer0_max_count being wrong. 553 * This shouldn't happen in normal operation, 554 * but it may happen if set_timer_freq() is 555 * traced. 556 */ 557 if (delta < 0) 558 delta = 0; 559 } 560 ticks_left -= delta; 561 } 562#ifdef DELAYDEBUG 563 if (state == 1) 564 printf(" %d calls to getit() at %d usec each\n", 565 getit_calls, (n + 5) / getit_calls); 566#endif 567} 568 569static void 570sysbeepstop(void *chan) 571{ 572#ifdef PC98 /* PC98 */ 573 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 574 release_timer1(); 575#else 576 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 577 release_timer2(); 578#endif 579 beeping = 0; 580} 581 582int 583sysbeep(int pitch, int period) 584{ 585 int x = splclock(); 586 587#ifdef PC98 588 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 589 if (!beeping) { 590 /* Something else owns it. */ 591 splx(x); 592 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 593 } 594 disable_intr(); 595 outb(0x3fdb, pitch); 596 outb(0x3fdb, (pitch>>8)); 597 enable_intr(); 598 if (!beeping) { 599 /* enable counter1 output to speaker */ 600 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 601 beeping = period; 602 timeout(sysbeepstop, (void *)NULL, period); 603 } 604#else 605 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 606 if (!beeping) { 607 /* Something else owns it. */ 608 splx(x); 609 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 610 } 611 disable_intr(); 612 outb(TIMER_CNTR2, pitch); 613 outb(TIMER_CNTR2, (pitch>>8)); 614 enable_intr(); 615 if (!beeping) { 616 /* enable counter2 output to speaker */ 617 outb(IO_PPI, inb(IO_PPI) | 3); 618 beeping = period; 619 timeout(sysbeepstop, (void *)NULL, period); 620 } 621#endif 622 splx(x); 623 return (0); 624} 625 626#ifndef PC98 627/* 628 * RTC support routines 629 */ 630 631int 632rtcin(reg) 633 int reg; 634{ 635 u_char val; 636 637 outb(IO_RTC, reg); 638 inb(0x84); 639 val = inb(IO_RTC + 1); 640 inb(0x84); 641 return (val); 642} 643 644static __inline void 645writertc(u_char reg, u_char val) 646{ 647 outb(IO_RTC, reg); 648 outb(IO_RTC + 1, val); 649} 650 651static __inline int 652readrtc(int port) 653{ 654 return(bcd2bin(rtcin(port))); 655} 656#endif 657 658#ifdef PC98 659unsigned int delaycount; 660#define FIRST_GUESS 0x2000 661static void findcpuspeed(void) 662{ 663 int i; 664 int remainder; 665 666 /* Put counter in count down mode */ 667 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 668 outb(TIMER_CNTR0, 0xff); 669 outb(TIMER_CNTR0, 0xff); 670 for (i = FIRST_GUESS; i; i--) 671 ; 672 remainder = getit(); 673 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 674} 675#endif 676 677#ifndef PC98 678static u_int 679calibrate_clocks(void) 680{ 681 u_int count, prev_count, tot_count; 682 int sec, start_sec, timeout; 683 684 if (bootverbose) 685 printf("Calibrating clock(s) ... "); 686 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 687 goto fail; 688 timeout = 100000000; 689 690 /* Read the mc146818A seconds counter. */ 691 for (;;) { 692 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 693 sec = rtcin(RTC_SEC); 694 break; 695 } 696 if (--timeout == 0) 697 goto fail; 698 } 699 700 /* Wait for the mC146818A seconds counter to change. */ 701 start_sec = sec; 702 for (;;) { 703 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 704 sec = rtcin(RTC_SEC); 705 if (sec != start_sec) 706 break; 707 } 708 if (--timeout == 0) 709 goto fail; 710 } 711 712 /* Start keeping track of the i8254 counter. */ 713 prev_count = getit(); 714 if (prev_count == 0 || prev_count > timer0_max_count) 715 goto fail; 716 tot_count = 0; 717 718#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 719 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) 720 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 721#endif 722 723 /* 724 * Wait for the mc146818A seconds counter to change. Read the i8254 725 * counter for each iteration since this is convenient and only 726 * costs a few usec of inaccuracy. The timing of the final reads 727 * of the counters almost matches the timing of the initial reads, 728 * so the main cause of inaccuracy is the varying latency from 729 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 730 * rtcin(RTC_SEC) that returns a changed seconds count. The 731 * maximum inaccuracy from this cause is < 10 usec on 486's. 732 */ 733 start_sec = sec; 734 for (;;) { 735 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 736 sec = rtcin(RTC_SEC); 737 count = getit(); 738 if (count == 0 || count > timer0_max_count) 739 goto fail; 740 if (count > prev_count) 741 tot_count += prev_count - (count - timer0_max_count); 742 else 743 tot_count += prev_count - count; 744 prev_count = count; 745 if (sec != start_sec) 746 break; 747 if (--timeout == 0) 748 goto fail; 749 } 750 751#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 752 /* 753 * Read the cpu cycle counter. The timing considerations are 754 * similar to those for the i8254 clock. 755 */ 756 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) { 757 set_i586_ctr_freq((u_int)rdtsc(), tot_count); 758 if (bootverbose) 759 printf("i586 clock: %u Hz, ", i586_ctr_freq); 760 } 761#endif 762 763 if (bootverbose) 764 printf("i8254 clock: %u Hz\n", tot_count); 765 return (tot_count); 766 767fail: 768 if (bootverbose) 769 printf("failed, using default i8254 clock of %u Hz\n", 770 timer_freq); 771 return (timer_freq); 772} 773#endif /* !PC98 */ 774 775static void 776set_timer_freq(u_int freq, int intr_freq) 777{ 778 u_long ef; 779 780 ef = read_eflags(); 781 disable_intr(); 782 timer_freq = freq; 783 timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 784 timer0_overflow_threshold = timer0_max_count - TIMER0_LATCH_COUNT; 785 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 786 outb(TIMER_CNTR0, timer0_max_count & 0xff); 787 outb(TIMER_CNTR0, timer0_max_count >> 8); 788 CLOCK_UNLOCK(); 789 write_eflags(ef); 790} 791 792/* 793 * Initialize 8253 timer 0 early so that it can be used in DELAY(). 794 * XXX initialization of other timers is unintentionally left blank. 795 */ 796void 797startrtclock() 798{ 799 u_int delta, freq; 800 801#ifdef PC98 802 findcpuspeed(); 803#ifndef AUTO_CLOCK 804 if (pc98_machine_type & M_8M) { 805#ifndef PC98_8M 806 printf("you must reconfig a kernel with \"PC98_8M\" option.\n"); 807#endif 808 } else { 809#ifdef PC98_8M 810 printf("You must reconfig a kernel without \"PC98_8M\" option.\n"); 811#endif 812 } 813#else /* AUTO_CLOCK */ 814 if (pc98_machine_type & M_8M) 815 timer_freq = 1996800L; /* 1.9968 MHz */ 816 else 817 timer_freq = 2457600L; /* 2.4576 MHz */ 818#endif /* AUTO_CLOCK */ 819#endif /* PC98 */ 820 821#ifndef PC98 822 writertc(RTC_STATUSA, rtc_statusa); 823 writertc(RTC_STATUSB, RTCSB_24HR); 824#endif 825 826#ifndef PC98 827 set_timer_freq(timer_freq, hz); 828 freq = calibrate_clocks(); 829#ifdef CLK_CALIBRATION_LOOP 830 if (bootverbose) { 831 printf( 832 "Press a key on the console to abort clock calibration\n"); 833 while (cncheckc() == -1) 834 calibrate_clocks(); 835 } 836#endif 837 838 /* 839 * Use the calibrated i8254 frequency if it seems reasonable. 840 * Otherwise use the default, and don't use the calibrated i586 841 * frequency. 842 */ 843 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 844 if (delta < timer_freq / 100) { 845#ifndef CLK_USE_I8254_CALIBRATION 846 if (bootverbose) 847 printf( 848"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 849 freq = timer_freq; 850#endif 851 timer_freq = freq; 852 } else { 853 if (bootverbose) 854 printf( 855 "%d Hz differs from default of %d Hz by more than 1%%\n", 856 freq, timer_freq); 857#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 858 i586_ctr_freq = 0; 859#endif 860 } 861#endif 862 863 set_timer_freq(timer_freq, hz); 864 865#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 866#ifndef CLK_USE_I586_CALIBRATION 867 if (i586_ctr_freq != 0) { 868 if (bootverbose) 869 printf( 870"CLK_USE_I586_CALIBRATION not specified - using old calibration method\n"); 871 i586_ctr_freq = 0; 872 } 873#endif 874 if (i586_ctr_freq == 0 && 875 (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686)) { 876 /* 877 * Calibration of the i586 clock relative to the mc146818A 878 * clock failed. Do a less accurate calibration relative 879 * to the i8254 clock. 880 */ 881 wrmsr(0x10, 0LL); /* XXX */ 882 DELAY(1000000); 883 set_i586_ctr_freq((u_int)rdtsc(), timer_freq); 884#ifdef CLK_USE_I586_CALIBRATION 885 if (bootverbose) 886 printf("i586 clock: %u Hz\n", i586_ctr_freq); 887#endif 888 } 889#endif 890} 891 892#ifdef PC98 893static void 894rtc_serialcombit(int i) 895{ 896 outb(IO_RTC, ((i&0x01)<<5)|0x07); 897 DELAY(1); 898 outb(IO_RTC, ((i&0x01)<<5)|0x17); 899 DELAY(1); 900 outb(IO_RTC, ((i&0x01)<<5)|0x07); 901 DELAY(1); 902} 903 904static void 905rtc_serialcom(int i) 906{ 907 rtc_serialcombit(i&0x01); 908 rtc_serialcombit((i&0x02)>>1); 909 rtc_serialcombit((i&0x04)>>2); 910 rtc_serialcombit((i&0x08)>>3); 911 outb(IO_RTC, 0x07); 912 DELAY(1); 913 outb(IO_RTC, 0x0f); 914 DELAY(1); 915 outb(IO_RTC, 0x07); 916 DELAY(1); 917} 918 919static void 920rtc_outb(int val) 921{ 922 int s; 923 int sa = 0; 924 925 for (s=0;s<8;s++) { 926 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 927 outb(IO_RTC, sa); /* set DI & CLK 0 */ 928 DELAY(1); 929 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 930 DELAY(1); 931 } 932 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 933} 934 935static int 936rtc_inb(void) 937{ 938 int s; 939 int sa = 0; 940 941 for (s=0;s<8;s++) { 942 sa |= ((inb(0x33) & 0x01) << s); 943 outb(IO_RTC, 0x17); /* CLK 1 */ 944 DELAY(1); 945 outb(IO_RTC, 0x07); /* CLK 0 */ 946 DELAY(2); 947 } 948 return sa; 949} 950#endif /* PC-98 */ 951 952/* 953 * Initialize the time of day register, based on the time base which is, e.g. 954 * from a filesystem. 955 */ 956void 957inittodr(time_t base) 958{ 959 unsigned long sec, days; 960 int yd; 961 int year, month; 962 int y, m, s; 963#ifdef PC98 964 int second, min, hour; 965#endif 966 967 s = splclock(); 968 time.tv_sec = base; 969 time.tv_usec = 0; 970 splx(s); 971 972#ifdef PC98 973 rtc_serialcom(0x03); /* Time Read */ 974 rtc_serialcom(0x01); /* Register shift command. */ 975 DELAY(20); 976 977 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 978 min = bcd2bin(rtc_inb() & 0xff); /* min */ 979 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 980 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 981 982 month = (rtc_inb() >> 4) & 0x0f; /* month */ 983 for (m = 1; m < month; m++) 984 days += daysinmonth[m-1]; 985 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 986 /* 2000 year problem */ 987 if (year < 1995) 988 year += 100; 989 if (year < 1970) 990 goto wrong_time; 991 for (y = 1970; y < year; y++) 992 days += DAYSPERYEAR + LEAPYEAR(y); 993 if ((month > 2) && LEAPYEAR(year)) 994 days ++; 995 sec = ((( days * 24 + 996 hour) * 60 + 997 min) * 60 + 998 second); 999 /* sec now contains the number of seconds, since Jan 1 1970, 1000 in the local time zone */ 1001#else /* IBM-PC */ 1002 /* Look if we have a RTC present and the time is valid */ 1003 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 1004 goto wrong_time; 1005 1006 /* wait for time update to complete */ 1007 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 1008 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 1009 1010 days = 0; 1011#ifdef USE_RTC_CENTURY 1012 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 1013#else 1014 year = readrtc(RTC_YEAR) + 1900; 1015 if (year < 1970) 1016 year += 100; 1017#endif 1018 if (year < 1970) 1019 goto wrong_time; 1020 month = readrtc(RTC_MONTH); 1021 for (m = 1; m < month; m++) 1022 days += daysinmonth[m-1]; 1023 if ((month > 2) && LEAPYEAR(year)) 1024 days ++; 1025 days += readrtc(RTC_DAY) - 1; 1026 yd = days; 1027 for (y = 1970; y < year; y++) 1028 days += DAYSPERYEAR + LEAPYEAR(y); 1029 sec = ((( days * 24 + 1030 readrtc(RTC_HRS)) * 60 + 1031 readrtc(RTC_MIN)) * 60 + 1032 readrtc(RTC_SEC)); 1033 /* sec now contains the number of seconds, since Jan 1 1970, 1034 in the local time zone */ 1035#endif 1036 1037 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1038 1039 s = splclock(); 1040 time.tv_sec = sec; 1041 splx(s); 1042 return; 1043 1044wrong_time: 1045 printf("Invalid time in real time clock.\n"); 1046 printf("Check and reset the date immediately!\n"); 1047} 1048 1049/* 1050 * Write system time back to RTC 1051 */ 1052void 1053resettodr() 1054{ 1055 unsigned long tm; 1056 int y, m, s; 1057#ifdef PC98 1058 int wd; 1059#endif 1060 1061 if (disable_rtc_set) 1062 return; 1063 1064 s = splclock(); 1065 tm = time.tv_sec; 1066 splx(s); 1067 1068#ifdef PC98 1069 rtc_serialcom(0x01); /* Register shift command. */ 1070 1071 /* Calculate local time to put in RTC */ 1072 1073 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1074 1075 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1076 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1077 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1078 1079 /* We have now the days since 01-01-1970 in tm */ 1080 wd = (tm+4)%7; 1081 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1082 tm >= m; 1083 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1084 tm -= m; 1085 1086 /* Now we have the years in y and the day-of-the-year in tm */ 1087 for (m = 0; ; m++) { 1088 int ml; 1089 1090 ml = daysinmonth[m]; 1091 if (m == 1 && LEAPYEAR(y)) 1092 ml++; 1093 if (tm < ml) 1094 break; 1095 tm -= ml; 1096 } 1097 1098 m++; 1099 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1100 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1101 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1102 1103 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1104 rtc_serialcom(0x00); /* Register hold command. */ 1105#else 1106 /* Disable RTC updates and interrupts. */ 1107 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1108 1109 /* Calculate local time to put in RTC */ 1110 1111 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1112 1113 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1114 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1115 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1116 1117 /* We have now the days since 01-01-1970 in tm */ 1118 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1119 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1120 tm >= m; 1121 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1122 tm -= m; 1123 1124 /* Now we have the years in y and the day-of-the-year in tm */ 1125 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1126#ifdef USE_RTC_CENTURY 1127 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1128#endif 1129 for (m = 0; ; m++) { 1130 int ml; 1131 1132 ml = daysinmonth[m]; 1133 if (m == 1 && LEAPYEAR(y)) 1134 ml++; 1135 if (tm < ml) 1136 break; 1137 tm -= ml; 1138 } 1139 1140 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1141 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1142 1143 /* Reenable RTC updates and interrupts. */ 1144 writertc(RTC_STATUSB, rtc_statusb); 1145#endif 1146} 1147 1148 1149/* 1150 * Start both clocks running. 1151 */ 1152void 1153cpu_initclocks() 1154{ 1155#ifdef APIC_IO 1156 int x; 1157#endif /* APIC_IO */ 1158#ifndef PC98 1159 int diag; 1160 1161 if (statclock_disable) { 1162 /* 1163 * The stat interrupt mask is different without the 1164 * statistics clock. Also, don't set the interrupt 1165 * flag which would normally cause the RTC to generate 1166 * interrupts. 1167 */ 1168 stat_imask = HWI_MASK | SWI_MASK; 1169 rtc_statusb = RTCSB_24HR; 1170 } else { 1171 /* Setting stathz to nonzero early helps avoid races. */ 1172 stathz = RTC_NOPROFRATE; 1173 profhz = RTC_PROFRATE; 1174 } 1175#endif 1176 1177 /* Finish initializing 8253 timer 0. */ 1178#ifdef APIC_IO 1179 1180 /* 1st look for ExtInt on pin 0 */ 1181 if (apic_int_type(0, 0) == 3) { 1182 /* 1183 * Allow 8254 timer to INTerrupt 8259: 1184 * re-initialize master 8259: 1185 * reset; prog 4 bytes, single ICU, edge triggered 1186 */ 1187 outb(IO_ICU1, 0x13); 1188 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */ 1189 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1190 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1191 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1192 1193 /* program IO APIC for type 3 INT on INT0 */ 1194 if (ext_int_setup(0, 0) < 0) 1195 panic("8254 redirect via APIC pin0 impossible!"); 1196 1197 x = 0; 1198 /* XXX if (bootverbose) */ 1199 printf("APIC_IO: routing 8254 via 8259 on pin 0\n"); 1200 } 1201 1202 /* failing that, look for 8254 on pin 2 */ 1203 else if (isa_apic_pin(0) == 2) { 1204 x = 2; 1205 /* XXX if (bootverbose) */ 1206 printf("APIC_IO: routing 8254 via pin 2\n"); 1207 } 1208 1209 /* better write that 8254 INT discover code... */ 1210 else 1211 panic("neither pin 0 or pin 2 works for 8254"); 1212 1213 /* setup the vectors */ 1214 vec[x] = (u_int)vec8254; 1215 Xintr8254 = (u_int)ivectors[x]; 1216 mask8254 = (1 << x); 1217 1218 register_intr(/* irq */ x, /* XXX id */ 0, /* flags */ 0, 1219 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1220 /* unit */ 0); 1221 INTREN(mask8254); 1222 1223#else /* APIC_IO */ 1224 1225 register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, 1226 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1227 /* unit */ 0); 1228 INTREN(IRQ0); 1229 1230#endif /* APIC_IO */ 1231 1232#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 1233 /* 1234 * Finish setting up anti-jitter measures. 1235 */ 1236 if (i586_ctr_freq != 0) 1237 i586_ctr_bias = rdtsc(); 1238#endif 1239 1240#ifndef PC98 1241 /* Initialize RTC. */ 1242 writertc(RTC_STATUSA, rtc_statusa); 1243 writertc(RTC_STATUSB, RTCSB_24HR); 1244 1245 /* Don't bother enabling the statistics clock. */ 1246 if (statclock_disable) 1247 return; 1248 diag = rtcin(RTC_DIAG); 1249 if (diag != 0) 1250 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1251 1252#ifdef APIC_IO 1253 if (isa_apic_pin(8) != 8) 1254 panic("APIC RTC != 8"); 1255#endif /* APIC_IO */ 1256 1257 register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, 1258 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1259 /* unit */ 0); 1260 1261#ifdef APIC_IO 1262 INTREN(APIC_IRQ8); 1263#else 1264 INTREN(IRQ8); 1265#endif /* APIC_IO */ 1266 1267 writertc(RTC_STATUSB, rtc_statusb); 1268#endif /* !PC98 */ 1269} 1270 1271void 1272setstatclockrate(int newhz) 1273{ 1274#ifndef PC98 1275 if (newhz == RTC_PROFRATE) 1276 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1277 else 1278 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1279 writertc(RTC_STATUSA, rtc_statusa); 1280#endif 1281} 1282 1283static int 1284sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1285{ 1286 int error; 1287 u_int freq; 1288 1289 /* 1290 * Use `i8254' instead of `timer' in external names because `timer' 1291 * is is too generic. Should use it everywhere. 1292 */ 1293 freq = timer_freq; 1294 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1295 if (error == 0 && req->newptr != NULL) { 1296 if (timer0_state != 0) 1297 return (EBUSY); /* too much trouble to handle */ 1298 set_timer_freq(freq, hz); 1299#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 1300 set_i586_ctr_freq(i586_ctr_freq, timer_freq); 1301#endif 1302 } 1303 return (error); 1304} 1305 1306SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1307 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1308 1309#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 1310static void 1311set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq) 1312{ 1313 u_int comultiplier, multiplier; 1314 u_long ef; 1315 1316 if (i586_freq == 0) { 1317 i586_ctr_freq = i586_freq; 1318 return; 1319 } 1320 comultiplier = ((unsigned long long)i586_freq 1321 << I586_CTR_COMULTIPLIER_SHIFT) / i8254_freq; 1322 multiplier = (1000000LL << I586_CTR_MULTIPLIER_SHIFT) / i586_freq; 1323 ef = read_eflags(); 1324 disable_intr(); 1325 i586_ctr_freq = i586_freq; 1326 i586_ctr_comultiplier = comultiplier; 1327 i586_ctr_multiplier = multiplier; 1328 CLOCK_UNLOCK(); 1329 write_eflags(ef); 1330} 1331 1332static int 1333sysctl_machdep_i586_freq SYSCTL_HANDLER_ARGS 1334{ 1335 int error; 1336 u_int freq; 1337 1338 if (cpu_class != CPUCLASS_586 && cpu_class != CPUCLASS_686) 1339 return (EOPNOTSUPP); 1340 freq = i586_ctr_freq; 1341 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1342 if (error == 0 && req->newptr != NULL) 1343 set_i586_ctr_freq(freq, timer_freq); 1344 return (error); 1345} 1346 1347SYSCTL_PROC(_machdep, OID_AUTO, i586_freq, CTLTYPE_INT | CTLFLAG_RW, 1348 0, sizeof(u_int), sysctl_machdep_i586_freq, "I", ""); 1349#endif /* (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) */ 1350