pcrtc.c revision 30811
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $Id: clock.c,v 1.35 1997/09/01 10:44:06 kato Exp $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51/* 52 * modified for PC98 by Kakefuda 53 */ 54 55#include "opt_clock.h" 56#include "opt_cpu.h" 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/time.h> 61#include <sys/kernel.h> 62#include <sys/sysctl.h> 63 64#include <machine/clock.h> 65#ifdef CLK_CALIBRATION_LOOP 66#include <machine/cons.h> 67#endif 68#include <machine/cputypes.h> 69#include <machine/frame.h> 70#include <machine/ipl.h> 71#include <machine/limits.h> 72#ifdef APIC_IO 73#include <machine/segments.h> 74#endif 75#if defined(SMP) || defined(APIC_IO) 76#include <machine/smp.h> 77#endif /* SMP || APIC_IO */ 78 79#include <i386/isa/icu.h> 80#ifdef PC98 81#include <pc98/pc98/pc98.h> 82#include <pc98/pc98/pc98_machdep.h> 83#include <i386/isa/isa_device.h> 84#else 85#include <i386/isa/isa.h> 86#include <i386/isa/rtc.h> 87#endif 88#include <i386/isa/timerreg.h> 89 90#include <i386/isa/intr_machdep.h> 91#include <sys/interrupt.h> 92 93#ifdef SMP 94#define disable_intr() CLOCK_DISABLE_INTR() 95#define enable_intr() CLOCK_ENABLE_INTR() 96#endif /* SMP */ 97 98/* 99 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 100 * can use a simple formula for leap years. 101 */ 102#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 103#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 104 105#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 106 107/* 108 * Time in timer cycles that it takes for microtime() to disable interrupts 109 * and latch the count. microtime() currently uses "cli; outb ..." so it 110 * normally takes less than 2 timer cycles. Add a few for cache misses. 111 * Add a few more to allow for latency in bogus calls to microtime() with 112 * interrupts already disabled. 113 */ 114#define TIMER0_LATCH_COUNT 20 115 116/* 117 * Maximum frequency that we are willing to allow for timer0. Must be 118 * low enough to guarantee that the timer interrupt handler returns 119 * before the next timer interrupt. Must result in a lower TIMER_DIV 120 * value than TIMER0_LATCH_COUNT so that we don't have to worry about 121 * underflow in the calculation of timer0_overflow_threshold. 122 */ 123#define TIMER0_MAX_FREQ 20000 124 125int adjkerntz; /* local offset from GMT in seconds */ 126int disable_rtc_set; /* disable resettodr() if != 0 */ 127u_int idelayed; 128#if defined(I586_CPU) || defined(I686_CPU) 129#ifndef SMP 130u_int i586_ctr_bias; 131u_int i586_ctr_comultiplier; 132#endif 133u_int i586_ctr_freq; 134#ifndef SMP 135u_int i586_ctr_multiplier; 136#endif 137#endif 138int statclock_disable; 139u_int stat_imask = SWI_CLOCK_MASK; 140#ifdef TIMER_FREQ 141u_int timer_freq = TIMER_FREQ; 142#else 143#ifdef PC98 144#ifndef AUTO_CLOCK 145#ifndef PC98_8M 146u_int timer_freq = 2457600; 147#else /* !PC98_8M */ 148u_int timer_freq = 1996800; 149#endif /* PC98_8M */ 150#else /* AUTO_CLOCK */ 151u_int timer_freq = 2457600; 152#endif /* AUTO_CLOCK */ 153#else /* IBM-PC */ 154u_int timer_freq = 1193182; 155#endif /* PC98 */ 156#endif 157int timer0_max_count; 158u_int timer0_overflow_threshold; 159u_int timer0_prescaler_count; 160int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 161 162static int beeping = 0; 163static u_int clk_imask = HWI_MASK | SWI_MASK; 164static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 165static u_int hardclock_max_count; 166/* 167 * XXX new_function and timer_func should not handle clockframes, but 168 * timer_func currently needs to hold hardclock to handle the 169 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 170 * to switch between clkintr() and a slightly different timerintr(). 171 */ 172static void (*new_function) __P((struct clockframe *frame)); 173static u_int new_rate; 174#ifndef PC98 175static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 176static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 177#endif 178 179/* Values for timerX_state: */ 180#define RELEASED 0 181#define RELEASE_PENDING 1 182#define ACQUIRED 2 183#define ACQUIRE_PENDING 3 184 185static u_char timer0_state; 186#ifdef PC98 187static u_char timer1_state; 188#endif 189static u_char timer2_state; 190static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 191#ifdef PC98 192static void rtc_serialcombit __P((int)); 193static void rtc_serialcom __P((int)); 194static int rtc_inb __P((void)); 195static void rtc_outb __P((int)); 196#endif 197 198#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 199static void set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq); 200#endif 201static void set_timer_freq(u_int freq, int intr_freq); 202 203static void 204clkintr(struct clockframe frame) 205{ 206 timer_func(&frame); 207 switch (timer0_state) { 208 209 case RELEASED: 210 setdelayed(); 211 break; 212 213 case ACQUIRED: 214 if ((timer0_prescaler_count += timer0_max_count) 215 >= hardclock_max_count) { 216 hardclock(&frame); 217 setdelayed(); 218 timer0_prescaler_count -= hardclock_max_count; 219 } 220 break; 221 222 case ACQUIRE_PENDING: 223 setdelayed(); 224 timer0_max_count = TIMER_DIV(new_rate); 225 timer0_overflow_threshold = 226 timer0_max_count - TIMER0_LATCH_COUNT; 227 disable_intr(); 228 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 229 outb(TIMER_CNTR0, timer0_max_count & 0xff); 230 outb(TIMER_CNTR0, timer0_max_count >> 8); 231 enable_intr(); 232 timer0_prescaler_count = 0; 233 timer_func = new_function; 234 timer0_state = ACQUIRED; 235 break; 236 237 case RELEASE_PENDING: 238 if ((timer0_prescaler_count += timer0_max_count) 239 >= hardclock_max_count) { 240 hardclock(&frame); 241 setdelayed(); 242 timer0_max_count = hardclock_max_count; 243 timer0_overflow_threshold = 244 timer0_max_count - TIMER0_LATCH_COUNT; 245 disable_intr(); 246 outb(TIMER_MODE, 247 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 248 outb(TIMER_CNTR0, timer0_max_count & 0xff); 249 outb(TIMER_CNTR0, timer0_max_count >> 8); 250 enable_intr(); 251 /* 252 * See microtime.s for this magic. 253 */ 254#ifdef PC98 255#ifndef AUTO_CLOCK 256#ifndef PC98_8M 257 time.tv_usec += (6667 * 258 (timer0_prescaler_count - hardclock_max_count)) 259 >> 14; 260#else /* PC98_8M */ 261 time.tv_usec += (16411 * 262 (timer0_prescaler_count - hardclock_max_count)) 263 >> 15; 264#endif /* PC98_8M */ 265#else /* AUTO_CLOCK */ 266 if (pc98_machine_type & M_8M) { 267 /* PC98_8M */ 268 time.tv_usec += (16411 * 269 (timer0_prescaler_count - 270 hardclock_max_count)) >> 15; 271 } else { 272 time.tv_usec += (6667 * 273 (timer0_prescaler_count - 274 hardclock_max_count)) >> 14; 275 } 276#endif /* AUTO_CLOCK */ 277#else /* IBM-PC */ 278 time.tv_usec += (27465 * 279 (timer0_prescaler_count - hardclock_max_count)) 280 >> 15; 281#endif /* PC98 */ 282 if (time.tv_usec >= 1000000) 283 time.tv_usec -= 1000000; 284 timer0_prescaler_count = 0; 285 timer_func = hardclock; 286 timer0_state = RELEASED; 287 } 288 break; 289 } 290} 291 292/* 293 * The acquire and release functions must be called at ipl >= splclock(). 294 */ 295int 296acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 297{ 298 static int old_rate; 299 300 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 301 return (-1); 302 switch (timer0_state) { 303 304 case RELEASED: 305 timer0_state = ACQUIRE_PENDING; 306 break; 307 308 case RELEASE_PENDING: 309 if (rate != old_rate) 310 return (-1); 311 /* 312 * The timer has been released recently, but is being 313 * re-acquired before the release completed. In this 314 * case, we simply reclaim it as if it had not been 315 * released at all. 316 */ 317 timer0_state = ACQUIRED; 318 break; 319 320 default: 321 return (-1); /* busy */ 322 } 323 new_function = function; 324 old_rate = new_rate = rate; 325 return (0); 326} 327 328#ifdef PC98 329int 330acquire_timer1(int mode) 331{ 332 333 if (timer1_state != RELEASED) 334 return (-1); 335 timer1_state = ACQUIRED; 336 337 /* 338 * This access to the timer registers is as atomic as possible 339 * because it is a single instruction. We could do better if we 340 * knew the rate. Use of splclock() limits glitches to 10-100us, 341 * and this is probably good enough for timer2, so we aren't as 342 * careful with it as with timer0. 343 */ 344 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 345 346 return (0); 347} 348#endif 349 350int 351acquire_timer2(int mode) 352{ 353 354 if (timer2_state != RELEASED) 355 return (-1); 356 timer2_state = ACQUIRED; 357 358 /* 359 * This access to the timer registers is as atomic as possible 360 * because it is a single instruction. We could do better if we 361 * knew the rate. Use of splclock() limits glitches to 10-100us, 362 * and this is probably good enough for timer2, so we aren't as 363 * careful with it as with timer0. 364 */ 365 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 366 367 return (0); 368} 369 370int 371release_timer0() 372{ 373 switch (timer0_state) { 374 375 case ACQUIRED: 376 timer0_state = RELEASE_PENDING; 377 break; 378 379 case ACQUIRE_PENDING: 380 /* Nothing happened yet, release quickly. */ 381 timer0_state = RELEASED; 382 break; 383 384 default: 385 return (-1); 386 } 387 return (0); 388} 389 390#ifdef PC98 391int 392release_timer1() 393{ 394 395 if (timer1_state != ACQUIRED) 396 return (-1); 397 timer1_state = RELEASED; 398 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 399 return (0); 400} 401#endif 402 403int 404release_timer2() 405{ 406 407 if (timer2_state != ACQUIRED) 408 return (-1); 409 timer2_state = RELEASED; 410 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 411 return (0); 412} 413 414#ifndef PC98 415/* 416 * This routine receives statistical clock interrupts from the RTC. 417 * As explained above, these occur at 128 interrupts per second. 418 * When profiling, we receive interrupts at a rate of 1024 Hz. 419 * 420 * This does not actually add as much overhead as it sounds, because 421 * when the statistical clock is active, the hardclock driver no longer 422 * needs to keep (inaccurate) statistics on its own. This decouples 423 * statistics gathering from scheduling interrupts. 424 * 425 * The RTC chip requires that we read status register C (RTC_INTR) 426 * to acknowledge an interrupt, before it will generate the next one. 427 * Under high interrupt load, rtcintr() can be indefinitely delayed and 428 * the clock can tick immediately after the read from RTC_INTR. In this 429 * case, the mc146818A interrupt signal will not drop for long enough 430 * to register with the 8259 PIC. If an interrupt is missed, the stat 431 * clock will halt, considerably degrading system performance. This is 432 * why we use 'while' rather than a more straightforward 'if' below. 433 * Stat clock ticks can still be lost, causing minor loss of accuracy 434 * in the statistics, but the stat clock will no longer stop. 435 */ 436static void 437rtcintr(struct clockframe frame) 438{ 439 while (rtcin(RTC_INTR) & RTCIR_PERIOD) 440 statclock(&frame); 441} 442 443#include "opt_ddb.h" 444#ifdef DDB 445#include <ddb/ddb.h> 446 447DB_SHOW_COMMAND(rtc, rtc) 448{ 449 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 450 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 451 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 452 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 453} 454#endif /* DDB */ 455#endif /* for PC98 */ 456 457static int 458getit(void) 459{ 460 u_long ef; 461 int high, low; 462 463 ef = read_eflags(); 464 disable_intr(); 465 466 /* Select timer0 and latch counter value. */ 467 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 468 469 low = inb(TIMER_CNTR0); 470 high = inb(TIMER_CNTR0); 471 472 CLOCK_UNLOCK(); 473 write_eflags(ef); 474 return ((high << 8) | low); 475} 476 477/* 478 * Wait "n" microseconds. 479 * Relies on timer 1 counting down from (timer_freq / hz) 480 * Note: timer had better have been programmed before this is first used! 481 */ 482void 483DELAY(int n) 484{ 485 int delta, prev_tick, tick, ticks_left; 486 487#ifdef DELAYDEBUG 488 int getit_calls = 1; 489 int n1; 490 static int state = 0; 491 492 if (state == 0) { 493 state = 1; 494 for (n1 = 1; n1 <= 10000000; n1 *= 10) 495 DELAY(n1); 496 state = 2; 497 } 498 if (state == 1) 499 printf("DELAY(%d)...", n); 500#endif 501 /* 502 * Guard against the timer being uninitialized if we are called 503 * early for console i/o. 504 */ 505 if (timer0_max_count == 0) 506 set_timer_freq(timer_freq, hz); 507 508 /* 509 * Read the counter first, so that the rest of the setup overhead is 510 * counted. Guess the initial overhead is 20 usec (on most systems it 511 * takes about 1.5 usec for each of the i/o's in getit(). The loop 512 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 513 * multiplications and divisions to scale the count take a while). 514 */ 515 prev_tick = getit(); 516 n -= 0; /* XXX actually guess no initial overhead */ 517 /* 518 * Calculate (n * (timer_freq / 1e6)) without using floating point 519 * and without any avoidable overflows. 520 */ 521 if (n <= 0) 522 ticks_left = 0; 523 else if (n < 256) 524 /* 525 * Use fixed point to avoid a slow division by 1000000. 526 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 527 * 2^15 is the first power of 2 that gives exact results 528 * for n between 0 and 256. 529 */ 530 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 531 else 532 /* 533 * Don't bother using fixed point, although gcc-2.7.2 534 * generates particularly poor code for the long long 535 * division, since even the slow way will complete long 536 * before the delay is up (unless we're interrupted). 537 */ 538 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 539 / 1000000; 540 541 while (ticks_left > 0) { 542 tick = getit(); 543#ifdef DELAYDEBUG 544 ++getit_calls; 545#endif 546 delta = prev_tick - tick; 547 prev_tick = tick; 548 if (delta < 0) { 549 delta += timer0_max_count; 550 /* 551 * Guard against timer0_max_count being wrong. 552 * This shouldn't happen in normal operation, 553 * but it may happen if set_timer_freq() is 554 * traced. 555 */ 556 if (delta < 0) 557 delta = 0; 558 } 559 ticks_left -= delta; 560 } 561#ifdef DELAYDEBUG 562 if (state == 1) 563 printf(" %d calls to getit() at %d usec each\n", 564 getit_calls, (n + 5) / getit_calls); 565#endif 566} 567 568static void 569sysbeepstop(void *chan) 570{ 571#ifdef PC98 /* PC98 */ 572 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 573 release_timer1(); 574#else 575 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 576 release_timer2(); 577#endif 578 beeping = 0; 579} 580 581int 582sysbeep(int pitch, int period) 583{ 584 int x = splclock(); 585 586#ifdef PC98 587 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 588 if (!beeping) { 589 /* Something else owns it. */ 590 splx(x); 591 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 592 } 593 disable_intr(); 594 outb(0x3fdb, pitch); 595 outb(0x3fdb, (pitch>>8)); 596 enable_intr(); 597 if (!beeping) { 598 /* enable counter1 output to speaker */ 599 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 600 beeping = period; 601 timeout(sysbeepstop, (void *)NULL, period); 602 } 603#else 604 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 605 if (!beeping) { 606 /* Something else owns it. */ 607 splx(x); 608 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 609 } 610 disable_intr(); 611 outb(TIMER_CNTR2, pitch); 612 outb(TIMER_CNTR2, (pitch>>8)); 613 enable_intr(); 614 if (!beeping) { 615 /* enable counter2 output to speaker */ 616 outb(IO_PPI, inb(IO_PPI) | 3); 617 beeping = period; 618 timeout(sysbeepstop, (void *)NULL, period); 619 } 620#endif 621 splx(x); 622 return (0); 623} 624 625#ifndef PC98 626/* 627 * RTC support routines 628 */ 629 630int 631rtcin(reg) 632 int reg; 633{ 634 u_char val; 635 636 outb(IO_RTC, reg); 637 inb(0x84); 638 val = inb(IO_RTC + 1); 639 inb(0x84); 640 return (val); 641} 642 643static __inline void 644writertc(u_char reg, u_char val) 645{ 646 outb(IO_RTC, reg); 647 outb(IO_RTC + 1, val); 648} 649 650static __inline int 651readrtc(int port) 652{ 653 return(bcd2bin(rtcin(port))); 654} 655#endif 656 657#ifdef PC98 658unsigned int delaycount; 659#define FIRST_GUESS 0x2000 660static void findcpuspeed(void) 661{ 662 int i; 663 int remainder; 664 665 /* Put counter in count down mode */ 666 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 667 outb(TIMER_CNTR0, 0xff); 668 outb(TIMER_CNTR0, 0xff); 669 for (i = FIRST_GUESS; i; i--) 670 ; 671 remainder = getit(); 672 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 673} 674#endif 675 676#ifndef PC98 677static u_int 678calibrate_clocks(void) 679{ 680 u_int count, prev_count, tot_count; 681 int sec, start_sec, timeout; 682 683 if (bootverbose) 684 printf("Calibrating clock(s) ... "); 685 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 686 goto fail; 687 timeout = 100000000; 688 689 /* Read the mc146818A seconds counter. */ 690 for (;;) { 691 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 692 sec = rtcin(RTC_SEC); 693 break; 694 } 695 if (--timeout == 0) 696 goto fail; 697 } 698 699 /* Wait for the mC146818A seconds counter to change. */ 700 start_sec = sec; 701 for (;;) { 702 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 703 sec = rtcin(RTC_SEC); 704 if (sec != start_sec) 705 break; 706 } 707 if (--timeout == 0) 708 goto fail; 709 } 710 711 /* Start keeping track of the i8254 counter. */ 712 prev_count = getit(); 713 if (prev_count == 0 || prev_count > timer0_max_count) 714 goto fail; 715 tot_count = 0; 716 717#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 718 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) 719 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 720#endif 721 722 /* 723 * Wait for the mc146818A seconds counter to change. Read the i8254 724 * counter for each iteration since this is convenient and only 725 * costs a few usec of inaccuracy. The timing of the final reads 726 * of the counters almost matches the timing of the initial reads, 727 * so the main cause of inaccuracy is the varying latency from 728 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 729 * rtcin(RTC_SEC) that returns a changed seconds count. The 730 * maximum inaccuracy from this cause is < 10 usec on 486's. 731 */ 732 start_sec = sec; 733 for (;;) { 734 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 735 sec = rtcin(RTC_SEC); 736 count = getit(); 737 if (count == 0 || count > timer0_max_count) 738 goto fail; 739 if (count > prev_count) 740 tot_count += prev_count - (count - timer0_max_count); 741 else 742 tot_count += prev_count - count; 743 prev_count = count; 744 if (sec != start_sec) 745 break; 746 if (--timeout == 0) 747 goto fail; 748 } 749 750#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 751 /* 752 * Read the cpu cycle counter. The timing considerations are 753 * similar to those for the i8254 clock. 754 */ 755 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) { 756 set_i586_ctr_freq((u_int)rdtsc(), tot_count); 757 if (bootverbose) 758 printf("i586 clock: %u Hz, ", i586_ctr_freq); 759 } 760#endif 761 762 if (bootverbose) 763 printf("i8254 clock: %u Hz\n", tot_count); 764 return (tot_count); 765 766fail: 767 if (bootverbose) 768 printf("failed, using default i8254 clock of %u Hz\n", 769 timer_freq); 770 return (timer_freq); 771} 772#endif /* !PC98 */ 773 774static void 775set_timer_freq(u_int freq, int intr_freq) 776{ 777 u_long ef; 778 779 ef = read_eflags(); 780 disable_intr(); 781 timer_freq = freq; 782 timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 783 timer0_overflow_threshold = timer0_max_count - TIMER0_LATCH_COUNT; 784 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 785 outb(TIMER_CNTR0, timer0_max_count & 0xff); 786 outb(TIMER_CNTR0, timer0_max_count >> 8); 787 CLOCK_UNLOCK(); 788 write_eflags(ef); 789} 790 791/* 792 * Initialize 8253 timer 0 early so that it can be used in DELAY(). 793 * XXX initialization of other timers is unintentionally left blank. 794 */ 795void 796startrtclock() 797{ 798 u_int delta, freq; 799 800#ifdef PC98 801 findcpuspeed(); 802#ifndef AUTO_CLOCK 803 if (pc98_machine_type & M_8M) { 804#ifndef PC98_8M 805 printf("you must reconfig a kernel with \"PC98_8M\" option.\n"); 806#endif 807 } else { 808#ifdef PC98_8M 809 printf("You must reconfig a kernel without \"PC98_8M\" option.\n"); 810#endif 811 } 812#else /* AUTO_CLOCK */ 813 if (pc98_machine_type & M_8M) 814 timer_freq = 1996800L; /* 1.9968 MHz */ 815 else 816 timer_freq = 2457600L; /* 2.4576 MHz */ 817#endif /* AUTO_CLOCK */ 818#endif /* PC98 */ 819 820#ifndef PC98 821 writertc(RTC_STATUSA, rtc_statusa); 822 writertc(RTC_STATUSB, RTCSB_24HR); 823#endif 824 825#ifndef PC98 826 set_timer_freq(timer_freq, hz); 827 freq = calibrate_clocks(); 828#ifdef CLK_CALIBRATION_LOOP 829 if (bootverbose) { 830 printf( 831 "Press a key on the console to abort clock calibration\n"); 832 while (cncheckc() == -1) 833 calibrate_clocks(); 834 } 835#endif 836 837 /* 838 * Use the calibrated i8254 frequency if it seems reasonable. 839 * Otherwise use the default, and don't use the calibrated i586 840 * frequency. 841 */ 842 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 843 if (delta < timer_freq / 100) { 844#ifndef CLK_USE_I8254_CALIBRATION 845 if (bootverbose) 846 printf( 847"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 848 freq = timer_freq; 849#endif 850 timer_freq = freq; 851 } else { 852 if (bootverbose) 853 printf( 854 "%d Hz differs from default of %d Hz by more than 1%%\n", 855 freq, timer_freq); 856#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 857 i586_ctr_freq = 0; 858#endif 859 } 860#endif 861 862 set_timer_freq(timer_freq, hz); 863 864#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 865#ifndef CLK_USE_I586_CALIBRATION 866 if (i586_ctr_freq != 0) { 867 if (bootverbose) 868 printf( 869"CLK_USE_I586_CALIBRATION not specified - using old calibration method\n"); 870 i586_ctr_freq = 0; 871 } 872#endif 873 if (i586_ctr_freq == 0 && 874 (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686)) { 875 /* 876 * Calibration of the i586 clock relative to the mc146818A 877 * clock failed. Do a less accurate calibration relative 878 * to the i8254 clock. 879 */ 880 wrmsr(0x10, 0LL); /* XXX */ 881 DELAY(1000000); 882 set_i586_ctr_freq((u_int)rdtsc(), timer_freq); 883#ifdef CLK_USE_I586_CALIBRATION 884 if (bootverbose) 885 printf("i586 clock: %u Hz\n", i586_ctr_freq); 886#endif 887 } 888#endif 889} 890 891#ifdef PC98 892static void 893rtc_serialcombit(int i) 894{ 895 outb(IO_RTC, ((i&0x01)<<5)|0x07); 896 DELAY(1); 897 outb(IO_RTC, ((i&0x01)<<5)|0x17); 898 DELAY(1); 899 outb(IO_RTC, ((i&0x01)<<5)|0x07); 900 DELAY(1); 901} 902 903static void 904rtc_serialcom(int i) 905{ 906 rtc_serialcombit(i&0x01); 907 rtc_serialcombit((i&0x02)>>1); 908 rtc_serialcombit((i&0x04)>>2); 909 rtc_serialcombit((i&0x08)>>3); 910 outb(IO_RTC, 0x07); 911 DELAY(1); 912 outb(IO_RTC, 0x0f); 913 DELAY(1); 914 outb(IO_RTC, 0x07); 915 DELAY(1); 916} 917 918static void 919rtc_outb(int val) 920{ 921 int s; 922 int sa = 0; 923 924 for (s=0;s<8;s++) { 925 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 926 outb(IO_RTC, sa); /* set DI & CLK 0 */ 927 DELAY(1); 928 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 929 DELAY(1); 930 } 931 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 932} 933 934static int 935rtc_inb(void) 936{ 937 int s; 938 int sa = 0; 939 940 for (s=0;s<8;s++) { 941 sa |= ((inb(0x33) & 0x01) << s); 942 outb(IO_RTC, 0x17); /* CLK 1 */ 943 DELAY(1); 944 outb(IO_RTC, 0x07); /* CLK 0 */ 945 DELAY(2); 946 } 947 return sa; 948} 949#endif /* PC-98 */ 950 951/* 952 * Initialize the time of day register, based on the time base which is, e.g. 953 * from a filesystem. 954 */ 955void 956inittodr(time_t base) 957{ 958 unsigned long sec, days; 959 int yd; 960 int year, month; 961 int y, m, s; 962#ifdef PC98 963 int second, min, hour; 964#endif 965 966 s = splclock(); 967 time.tv_sec = base; 968 time.tv_usec = 0; 969 splx(s); 970 971#ifdef PC98 972 rtc_serialcom(0x03); /* Time Read */ 973 rtc_serialcom(0x01); /* Register shift command. */ 974 DELAY(20); 975 976 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 977 min = bcd2bin(rtc_inb() & 0xff); /* min */ 978 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 979 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 980 981 month = (rtc_inb() >> 4) & 0x0f; /* month */ 982 for (m = 1; m < month; m++) 983 days += daysinmonth[m-1]; 984 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 985 /* 2000 year problem */ 986 if (year < 1995) 987 year += 100; 988 if (year < 1970) 989 goto wrong_time; 990 for (y = 1970; y < year; y++) 991 days += DAYSPERYEAR + LEAPYEAR(y); 992 if ((month > 2) && LEAPYEAR(year)) 993 days ++; 994 sec = ((( days * 24 + 995 hour) * 60 + 996 min) * 60 + 997 second); 998 /* sec now contains the number of seconds, since Jan 1 1970, 999 in the local time zone */ 1000#else /* IBM-PC */ 1001 /* Look if we have a RTC present and the time is valid */ 1002 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 1003 goto wrong_time; 1004 1005 /* wait for time update to complete */ 1006 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 1007 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 1008 1009 days = 0; 1010#ifdef USE_RTC_CENTURY 1011 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 1012#else 1013 year = readrtc(RTC_YEAR) + 1900; 1014 if (year < 1970) 1015 year += 100; 1016#endif 1017 if (year < 1970) 1018 goto wrong_time; 1019 month = readrtc(RTC_MONTH); 1020 for (m = 1; m < month; m++) 1021 days += daysinmonth[m-1]; 1022 if ((month > 2) && LEAPYEAR(year)) 1023 days ++; 1024 days += readrtc(RTC_DAY) - 1; 1025 yd = days; 1026 for (y = 1970; y < year; y++) 1027 days += DAYSPERYEAR + LEAPYEAR(y); 1028 sec = ((( days * 24 + 1029 readrtc(RTC_HRS)) * 60 + 1030 readrtc(RTC_MIN)) * 60 + 1031 readrtc(RTC_SEC)); 1032 /* sec now contains the number of seconds, since Jan 1 1970, 1033 in the local time zone */ 1034#endif 1035 1036 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1037 1038 s = splclock(); 1039 time.tv_sec = sec; 1040 splx(s); 1041 return; 1042 1043wrong_time: 1044 printf("Invalid time in real time clock.\n"); 1045 printf("Check and reset the date immediately!\n"); 1046} 1047 1048/* 1049 * Write system time back to RTC 1050 */ 1051void 1052resettodr() 1053{ 1054 unsigned long tm; 1055 int y, m, s; 1056#ifdef PC98 1057 int wd; 1058#endif 1059 1060 if (disable_rtc_set) 1061 return; 1062 1063 s = splclock(); 1064 tm = time.tv_sec; 1065 splx(s); 1066 1067#ifdef PC98 1068 rtc_serialcom(0x01); /* Register shift command. */ 1069 1070 /* Calculate local time to put in RTC */ 1071 1072 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1073 1074 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1075 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1076 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1077 1078 /* We have now the days since 01-01-1970 in tm */ 1079 wd = (tm+4)%7; 1080 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1081 tm >= m; 1082 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1083 tm -= m; 1084 1085 /* Now we have the years in y and the day-of-the-year in tm */ 1086 for (m = 0; ; m++) { 1087 int ml; 1088 1089 ml = daysinmonth[m]; 1090 if (m == 1 && LEAPYEAR(y)) 1091 ml++; 1092 if (tm < ml) 1093 break; 1094 tm -= ml; 1095 } 1096 1097 m++; 1098 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1099 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1100 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1101 1102 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1103 rtc_serialcom(0x00); /* Register hold command. */ 1104#else 1105 /* Disable RTC updates and interrupts. */ 1106 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1107 1108 /* Calculate local time to put in RTC */ 1109 1110 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1111 1112 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1113 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1114 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1115 1116 /* We have now the days since 01-01-1970 in tm */ 1117 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1118 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1119 tm >= m; 1120 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1121 tm -= m; 1122 1123 /* Now we have the years in y and the day-of-the-year in tm */ 1124 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1125#ifdef USE_RTC_CENTURY 1126 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1127#endif 1128 for (m = 0; ; m++) { 1129 int ml; 1130 1131 ml = daysinmonth[m]; 1132 if (m == 1 && LEAPYEAR(y)) 1133 ml++; 1134 if (tm < ml) 1135 break; 1136 tm -= ml; 1137 } 1138 1139 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1140 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1141 1142 /* Reenable RTC updates and interrupts. */ 1143 writertc(RTC_STATUSB, rtc_statusb); 1144#endif 1145} 1146 1147 1148/* 1149 * Start both clocks running. 1150 */ 1151void 1152cpu_initclocks() 1153{ 1154#ifdef APIC_IO 1155 int x; 1156#endif /* APIC_IO */ 1157#ifndef PC98 1158 int diag; 1159 1160 if (statclock_disable) { 1161 /* 1162 * The stat interrupt mask is different without the 1163 * statistics clock. Also, don't set the interrupt 1164 * flag which would normally cause the RTC to generate 1165 * interrupts. 1166 */ 1167 stat_imask = HWI_MASK | SWI_MASK; 1168 rtc_statusb = RTCSB_24HR; 1169 } else { 1170 /* Setting stathz to nonzero early helps avoid races. */ 1171 stathz = RTC_NOPROFRATE; 1172 profhz = RTC_PROFRATE; 1173 } 1174#endif 1175 1176 /* Finish initializing 8253 timer 0. */ 1177#ifdef APIC_IO 1178 1179 /* 1st look for ExtInt on pin 0 */ 1180 if (apic_int_type(0, 0) == 3) { 1181 /* 1182 * Allow 8254 timer to INTerrupt 8259: 1183 * re-initialize master 8259: 1184 * reset; prog 4 bytes, single ICU, edge triggered 1185 */ 1186 outb(IO_ICU1, 0x13); 1187 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */ 1188 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1189 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1190 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1191 1192 /* program IO APIC for type 3 INT on INT0 */ 1193 if (ext_int_setup(0, 0) < 0) 1194 panic("8254 redirect via APIC pin0 impossible!"); 1195 1196 x = 0; 1197 /* XXX if (bootverbose) */ 1198 printf("APIC_IO: routing 8254 via 8259 on pin 0\n"); 1199 } 1200 1201 /* failing that, look for 8254 on pin 2 */ 1202 else if (isa_apic_pin(0) == 2) { 1203 x = 2; 1204 /* XXX if (bootverbose) */ 1205 printf("APIC_IO: routing 8254 via pin 2\n"); 1206 } 1207 1208 /* better write that 8254 INT discover code... */ 1209 else 1210 panic("neither pin 0 or pin 2 works for 8254"); 1211 1212 /* setup the vectors */ 1213 vec[x] = (u_int)vec8254; 1214 Xintr8254 = (u_int)ivectors[x]; 1215 mask8254 = (1 << x); 1216 1217 register_intr(/* irq */ x, /* XXX id */ 0, /* flags */ 0, 1218 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1219 /* unit */ 0); 1220 INTREN(mask8254); 1221 1222#else /* APIC_IO */ 1223 1224 register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, 1225 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1226 /* unit */ 0); 1227 INTREN(IRQ0); 1228 1229#endif /* APIC_IO */ 1230 1231#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 1232 /* 1233 * Finish setting up anti-jitter measures. 1234 */ 1235 if (i586_ctr_freq != 0) 1236 i586_ctr_bias = rdtsc(); 1237#endif 1238 1239#ifndef PC98 1240 /* Initialize RTC. */ 1241 writertc(RTC_STATUSA, rtc_statusa); 1242 writertc(RTC_STATUSB, RTCSB_24HR); 1243 1244 /* Don't bother enabling the statistics clock. */ 1245 if (statclock_disable) 1246 return; 1247 diag = rtcin(RTC_DIAG); 1248 if (diag != 0) 1249 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1250 1251#ifdef APIC_IO 1252 if (isa_apic_pin(8) != 8) 1253 panic("APIC RTC != 8"); 1254#endif /* APIC_IO */ 1255 1256 register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, 1257 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1258 /* unit */ 0); 1259 1260#ifdef APIC_IO 1261 INTREN(APIC_IRQ8); 1262#else 1263 INTREN(IRQ8); 1264#endif /* APIC_IO */ 1265 1266 writertc(RTC_STATUSB, rtc_statusb); 1267#endif /* !PC98 */ 1268} 1269 1270void 1271setstatclockrate(int newhz) 1272{ 1273#ifndef PC98 1274 if (newhz == RTC_PROFRATE) 1275 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1276 else 1277 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1278 writertc(RTC_STATUSA, rtc_statusa); 1279#endif 1280} 1281 1282static int 1283sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1284{ 1285 int error; 1286 u_int freq; 1287 1288 /* 1289 * Use `i8254' instead of `timer' in external names because `timer' 1290 * is is too generic. Should use it everywhere. 1291 */ 1292 freq = timer_freq; 1293 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1294 if (error == 0 && req->newptr != NULL) { 1295 if (timer0_state != 0) 1296 return (EBUSY); /* too much trouble to handle */ 1297 set_timer_freq(freq, hz); 1298#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 1299 set_i586_ctr_freq(i586_ctr_freq, timer_freq); 1300#endif 1301 } 1302 return (error); 1303} 1304 1305SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1306 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1307 1308#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 1309static void 1310set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq) 1311{ 1312 u_int comultiplier, multiplier; 1313 u_long ef; 1314 1315 if (i586_freq == 0) { 1316 i586_ctr_freq = i586_freq; 1317 return; 1318 } 1319 comultiplier = ((unsigned long long)i586_freq 1320 << I586_CTR_COMULTIPLIER_SHIFT) / i8254_freq; 1321 multiplier = (1000000LL << I586_CTR_MULTIPLIER_SHIFT) / i586_freq; 1322 ef = read_eflags(); 1323 disable_intr(); 1324 i586_ctr_freq = i586_freq; 1325 i586_ctr_comultiplier = comultiplier; 1326 i586_ctr_multiplier = multiplier; 1327 CLOCK_UNLOCK(); 1328 write_eflags(ef); 1329} 1330 1331static int 1332sysctl_machdep_i586_freq SYSCTL_HANDLER_ARGS 1333{ 1334 int error; 1335 u_int freq; 1336 1337 if (cpu_class != CPUCLASS_586 && cpu_class != CPUCLASS_686) 1338 return (EOPNOTSUPP); 1339 freq = i586_ctr_freq; 1340 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1341 if (error == 0 && req->newptr != NULL) 1342 set_i586_ctr_freq(freq, timer_freq); 1343 return (error); 1344} 1345 1346SYSCTL_PROC(_machdep, OID_AUTO, i586_freq, CTLTYPE_INT | CTLFLAG_RW, 1347 0, sizeof(u_int), sysctl_machdep_i586_freq, "I", ""); 1348#endif /* (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) */ 1349