pcrtc.c revision 26961
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $Id: clock.c,v 1.25 1997/06/02 15:45:40 kato Exp $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51/* 52 * modified for PC98 by Kakefuda 53 */ 54 55#include "opt_clock.h" 56#include "opt_cpu.h" 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/time.h> 61#include <sys/kernel.h> 62#include <sys/sysctl.h> 63 64#include <machine/clock.h> 65#ifdef CLK_CALIBRATION_LOOP 66#include <machine/cons.h> 67#endif 68#include <machine/cpu.h> 69#include <machine/frame.h> 70#include <machine/ipl.h> 71#ifdef APIC_IO 72#include <machine/smp.h> 73#endif /* APIC_IO */ 74 75#include <i386/isa/icu.h> 76#ifdef PC98 77#include <pc98/pc98/pc98.h> 78#include <pc98/pc98/pc98_machdep.h> 79#include <i386/isa/isa_device.h> 80#else 81#include <i386/isa/isa.h> 82#include <i386/isa/intr_machdep.h> 83#include <i386/isa/rtc.h> 84#endif 85#include <i386/isa/timerreg.h> 86 87/* 88 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 89 * can use a simple formula for leap years. 90 */ 91#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 92#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 93 94#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 95 96/* 97 * Time in timer cycles that it takes for microtime() to disable interrupts 98 * and latch the count. microtime() currently uses "cli; outb ..." so it 99 * normally takes less than 2 timer cycles. Add a few for cache misses. 100 * Add a few more to allow for latency in bogus calls to microtime() with 101 * interrupts already disabled. 102 */ 103#define TIMER0_LATCH_COUNT 20 104 105/* 106 * Maximum frequency that we are willing to allow for timer0. Must be 107 * low enough to guarantee that the timer interrupt handler returns 108 * before the next timer interrupt. Must result in a lower TIMER_DIV 109 * value than TIMER0_LATCH_COUNT so that we don't have to worry about 110 * underflow in the calculation of timer0_overflow_threshold. 111 */ 112#define TIMER0_MAX_FREQ 20000 113 114int adjkerntz; /* local offset from GMT in seconds */ 115int disable_rtc_set; /* disable resettodr() if != 0 */ 116u_int idelayed; 117#if defined(I586_CPU) || defined(I686_CPU) 118#ifndef SMP 119u_int i586_ctr_bias; 120u_int i586_ctr_comultiplier; 121#endif 122u_int i586_ctr_freq; 123#ifndef SMP 124u_int i586_ctr_multiplier; 125#endif 126#endif 127int statclock_disable; 128u_int stat_imask = SWI_CLOCK_MASK; 129#ifdef TIMER_FREQ 130u_int timer_freq = TIMER_FREQ; 131#else 132#ifdef PC98 133#ifndef AUTO_CLOCK 134#ifndef PC98_8M 135u_int timer_freq = 2457600; 136#else /* !PC98_8M */ 137u_int timer_freq = 1996800; 138#endif /* PC98_8M */ 139#else /* AUTO_CLOCK */ 140u_int timer_freq = 2457600; 141#endif /* AUTO_CLOCK */ 142#else /* IBM-PC */ 143u_int timer_freq = 1193182; 144#endif /* PC98 */ 145#endif 146int timer0_max_count; 147u_int timer0_overflow_threshold; 148u_int timer0_prescaler_count; 149int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 150 151static int beeping = 0; 152static u_int clk_imask = HWI_MASK | SWI_MASK; 153static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 154static u_int hardclock_max_count; 155/* 156 * XXX new_function and timer_func should not handle clockframes, but 157 * timer_func currently needs to hold hardclock to handle the 158 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 159 * to switch between clkintr() and a slightly different timerintr(). 160 */ 161static void (*new_function) __P((struct clockframe *frame)); 162static u_int new_rate; 163#ifndef PC98 164static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 165static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 166#endif 167 168/* Values for timerX_state: */ 169#define RELEASED 0 170#define RELEASE_PENDING 1 171#define ACQUIRED 2 172#define ACQUIRE_PENDING 3 173 174static u_char timer0_state; 175#ifdef PC98 176static u_char timer1_state; 177#endif 178static u_char timer2_state; 179static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 180#ifdef PC98 181static void rtc_serialcombit __P((int)); 182static void rtc_serialcom __P((int)); 183static int rtc_inb __P((void)); 184static void rtc_outb __P((int)); 185#endif 186 187#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 188static void set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq); 189#endif 190static void set_timer_freq(u_int freq, int intr_freq); 191 192static void 193clkintr(struct clockframe frame) 194{ 195 timer_func(&frame); 196 switch (timer0_state) { 197 198 case RELEASED: 199 setdelayed(); 200 break; 201 202 case ACQUIRED: 203 if ((timer0_prescaler_count += timer0_max_count) 204 >= hardclock_max_count) { 205 hardclock(&frame); 206 setdelayed(); 207 timer0_prescaler_count -= hardclock_max_count; 208 } 209 break; 210 211 case ACQUIRE_PENDING: 212 setdelayed(); 213 timer0_max_count = TIMER_DIV(new_rate); 214 timer0_overflow_threshold = 215 timer0_max_count - TIMER0_LATCH_COUNT; 216 disable_intr(); 217 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 218 outb(TIMER_CNTR0, timer0_max_count & 0xff); 219 outb(TIMER_CNTR0, timer0_max_count >> 8); 220 enable_intr(); 221 timer0_prescaler_count = 0; 222 timer_func = new_function; 223 timer0_state = ACQUIRED; 224 break; 225 226 case RELEASE_PENDING: 227 if ((timer0_prescaler_count += timer0_max_count) 228 >= hardclock_max_count) { 229 hardclock(&frame); 230 setdelayed(); 231 timer0_max_count = hardclock_max_count; 232 timer0_overflow_threshold = 233 timer0_max_count - TIMER0_LATCH_COUNT; 234 disable_intr(); 235 outb(TIMER_MODE, 236 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 237 outb(TIMER_CNTR0, timer0_max_count & 0xff); 238 outb(TIMER_CNTR0, timer0_max_count >> 8); 239 enable_intr(); 240 /* 241 * See microtime.s for this magic. 242 */ 243#ifdef PC98 244#ifndef AUTO_CLOCK 245#ifndef PC98_8M 246 time.tv_usec += (6667 * 247 (timer0_prescaler_count - hardclock_max_count)) 248 >> 14; 249#else /* PC98_8M */ 250 time.tv_usec += (16411 * 251 (timer0_prescaler_count - hardclock_max_count)) 252 >> 15; 253#endif /* PC98_8M */ 254#else /* AUTO_CLOCK */ 255 if (pc98_machine_type & M_8M) { 256 /* PC98_8M */ 257 time.tv_usec += (16411 * 258 (timer0_prescaler_count - 259 hardclock_max_count)) >> 15; 260 } else { 261 time.tv_usec += (6667 * 262 (timer0_prescaler_count - 263 hardclock_max_count)) >> 14; 264 } 265#endif /* AUTO_CLOCK */ 266#else /* IBM-PC */ 267 time.tv_usec += (27465 * 268 (timer0_prescaler_count - hardclock_max_count)) 269 >> 15; 270#endif /* PC98 */ 271 if (time.tv_usec >= 1000000) 272 time.tv_usec -= 1000000; 273 timer0_prescaler_count = 0; 274 timer_func = hardclock; 275 timer0_state = RELEASED; 276 } 277 break; 278 } 279} 280 281/* 282 * The acquire and release functions must be called at ipl >= splclock(). 283 */ 284int 285acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 286{ 287 static int old_rate; 288 289 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 290 return (-1); 291 switch (timer0_state) { 292 293 case RELEASED: 294 timer0_state = ACQUIRE_PENDING; 295 break; 296 297 case RELEASE_PENDING: 298 if (rate != old_rate) 299 return (-1); 300 /* 301 * The timer has been released recently, but is being 302 * re-acquired before the release completed. In this 303 * case, we simply reclaim it as if it had not been 304 * released at all. 305 */ 306 timer0_state = ACQUIRED; 307 break; 308 309 default: 310 return (-1); /* busy */ 311 } 312 new_function = function; 313 old_rate = new_rate = rate; 314 return (0); 315} 316 317#ifdef PC98 318int 319acquire_timer1(int mode) 320{ 321 322 if (timer1_state != RELEASED) 323 return (-1); 324 timer1_state = ACQUIRED; 325 326 /* 327 * This access to the timer registers is as atomic as possible 328 * because it is a single instruction. We could do better if we 329 * knew the rate. Use of splclock() limits glitches to 10-100us, 330 * and this is probably good enough for timer2, so we aren't as 331 * careful with it as with timer0. 332 */ 333 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 334 335 return (0); 336} 337#endif 338 339int 340acquire_timer2(int mode) 341{ 342 343 if (timer2_state != RELEASED) 344 return (-1); 345 timer2_state = ACQUIRED; 346 347 /* 348 * This access to the timer registers is as atomic as possible 349 * because it is a single instruction. We could do better if we 350 * knew the rate. Use of splclock() limits glitches to 10-100us, 351 * and this is probably good enough for timer2, so we aren't as 352 * careful with it as with timer0. 353 */ 354 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 355 356 return (0); 357} 358 359int 360release_timer0() 361{ 362 switch (timer0_state) { 363 364 case ACQUIRED: 365 timer0_state = RELEASE_PENDING; 366 break; 367 368 case ACQUIRE_PENDING: 369 /* Nothing happened yet, release quickly. */ 370 timer0_state = RELEASED; 371 break; 372 373 default: 374 return (-1); 375 } 376 return (0); 377} 378 379#ifdef PC98 380int 381release_timer1() 382{ 383 384 if (timer1_state != ACQUIRED) 385 return (-1); 386 timer1_state = RELEASED; 387 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 388 return (0); 389} 390#endif 391 392int 393release_timer2() 394{ 395 396 if (timer2_state != ACQUIRED) 397 return (-1); 398 timer2_state = RELEASED; 399 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 400 return (0); 401} 402 403#ifndef PC98 404/* 405 * This routine receives statistical clock interrupts from the RTC. 406 * As explained above, these occur at 128 interrupts per second. 407 * When profiling, we receive interrupts at a rate of 1024 Hz. 408 * 409 * This does not actually add as much overhead as it sounds, because 410 * when the statistical clock is active, the hardclock driver no longer 411 * needs to keep (inaccurate) statistics on its own. This decouples 412 * statistics gathering from scheduling interrupts. 413 * 414 * The RTC chip requires that we read status register C (RTC_INTR) 415 * to acknowledge an interrupt, before it will generate the next one. 416 * Under high interrupt load, rtcintr() can be indefinitely delayed and 417 * the clock can tick immediately after the read from RTC_INTR. In this 418 * case, the mc146818A interrupt signal will not drop for long enough 419 * to register with the 8259 PIC. If an interrupt is missed, the stat 420 * clock will halt, considerably degrading system performance. This is 421 * why we use 'while' rather than a more straightforward 'if' below. 422 * Stat clock ticks can still be lost, causing minor loss of accuracy 423 * in the statistics, but the stat clock will no longer stop. 424 */ 425static void 426rtcintr(struct clockframe frame) 427{ 428 while (rtcin(RTC_INTR) & RTCIR_PERIOD) 429 statclock(&frame); 430} 431 432#include "opt_ddb.h" 433#ifdef DDB 434#include <ddb/ddb.h> 435 436DB_SHOW_COMMAND(rtc, rtc) 437{ 438 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 439 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 440 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 441 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 442} 443#endif /* DDB */ 444#endif /* for PC98 */ 445 446static int 447getit(void) 448{ 449 u_long ef; 450 int high, low; 451 452 ef = read_eflags(); 453 disable_intr(); 454 455 /* Select timer0 and latch counter value. */ 456 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 457 458 low = inb(TIMER_CNTR0); 459 high = inb(TIMER_CNTR0); 460 461 write_eflags(ef); 462 return ((high << 8) | low); 463} 464 465/* 466 * Wait "n" microseconds. 467 * Relies on timer 1 counting down from (timer_freq / hz) 468 * Note: timer had better have been programmed before this is first used! 469 */ 470void 471DELAY(int n) 472{ 473 int delta, prev_tick, tick, ticks_left; 474 475#ifdef DELAYDEBUG 476 int getit_calls = 1; 477 int n1; 478 static int state = 0; 479 480 if (state == 0) { 481 state = 1; 482 for (n1 = 1; n1 <= 10000000; n1 *= 10) 483 DELAY(n1); 484 state = 2; 485 } 486 if (state == 1) 487 printf("DELAY(%d)...", n); 488#endif 489 /* 490 * Guard against the timer being uninitialized if we are called 491 * early for console i/o. 492 */ 493 if (timer0_max_count == 0) 494 set_timer_freq(timer_freq, hz); 495 496 /* 497 * Read the counter first, so that the rest of the setup overhead is 498 * counted. Guess the initial overhead is 20 usec (on most systems it 499 * takes about 1.5 usec for each of the i/o's in getit(). The loop 500 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 501 * multiplications and divisions to scale the count take a while). 502 */ 503 prev_tick = getit(); 504 n -= 0; /* XXX actually guess no initial overhead */ 505 /* 506 * Calculate (n * (timer_freq / 1e6)) without using floating point 507 * and without any avoidable overflows. 508 */ 509 if (n <= 0) 510 ticks_left = 0; 511 else if (n < 256) 512 /* 513 * Use fixed point to avoid a slow division by 1000000. 514 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 515 * 2^15 is the first power of 2 that gives exact results 516 * for n between 0 and 256. 517 */ 518 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 519 else 520 /* 521 * Don't bother using fixed point, although gcc-2.7.2 522 * generates particularly poor code for the long long 523 * division, since even the slow way will complete long 524 * before the delay is up (unless we're interrupted). 525 */ 526 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 527 / 1000000; 528 529 while (ticks_left > 0) { 530 tick = getit(); 531#ifdef DELAYDEBUG 532 ++getit_calls; 533#endif 534 delta = prev_tick - tick; 535 prev_tick = tick; 536 if (delta < 0) { 537 delta += timer0_max_count; 538 /* 539 * Guard against timer0_max_count being wrong. 540 * This shouldn't happen in normal operation, 541 * but it may happen if set_timer_freq() is 542 * traced. 543 */ 544 if (delta < 0) 545 delta = 0; 546 } 547 ticks_left -= delta; 548 } 549#ifdef DELAYDEBUG 550 if (state == 1) 551 printf(" %d calls to getit() at %d usec each\n", 552 getit_calls, (n + 5) / getit_calls); 553#endif 554} 555 556static void 557sysbeepstop(void *chan) 558{ 559#ifdef PC98 /* PC98 */ 560 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 561 release_timer1(); 562#else 563 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 564 release_timer2(); 565#endif 566 beeping = 0; 567} 568 569int 570sysbeep(int pitch, int period) 571{ 572 int x = splclock(); 573 574#ifdef PC98 575 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 576 if (!beeping) { 577 /* Something else owns it. */ 578 splx(x); 579 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 580 } 581 disable_intr(); 582 outb(0x3fdb, pitch); 583 outb(0x3fdb, (pitch>>8)); 584 enable_intr(); 585 if (!beeping) { 586 /* enable counter1 output to speaker */ 587 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 588 beeping = period; 589 timeout(sysbeepstop, (void *)NULL, period); 590 } 591#else 592 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 593 if (!beeping) { 594 /* Something else owns it. */ 595 splx(x); 596 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 597 } 598 disable_intr(); 599 outb(TIMER_CNTR2, pitch); 600 outb(TIMER_CNTR2, (pitch>>8)); 601 enable_intr(); 602 if (!beeping) { 603 /* enable counter2 output to speaker */ 604 outb(IO_PPI, inb(IO_PPI) | 3); 605 beeping = period; 606 timeout(sysbeepstop, (void *)NULL, period); 607 } 608#endif 609 splx(x); 610 return (0); 611} 612 613#ifndef PC98 614/* 615 * RTC support routines 616 */ 617 618int 619rtcin(reg) 620 int reg; 621{ 622 u_char val; 623 624 outb(IO_RTC, reg); 625 inb(0x84); 626 val = inb(IO_RTC + 1); 627 inb(0x84); 628 return (val); 629} 630 631static __inline void 632writertc(u_char reg, u_char val) 633{ 634 outb(IO_RTC, reg); 635 outb(IO_RTC + 1, val); 636} 637 638static __inline int 639readrtc(int port) 640{ 641 return(bcd2bin(rtcin(port))); 642} 643#endif 644 645#ifdef PC98 646unsigned int delaycount; 647#define FIRST_GUESS 0x2000 648static void findcpuspeed(void) 649{ 650 int i; 651 int remainder; 652 653 /* Put counter in count down mode */ 654 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 655 outb(TIMER_CNTR0, 0xff); 656 outb(TIMER_CNTR0, 0xff); 657 for (i = FIRST_GUESS; i; i--) 658 ; 659 remainder = getit(); 660 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 661} 662#endif 663 664#ifndef PC98 665static u_int 666calibrate_clocks(void) 667{ 668 u_int count, prev_count, tot_count; 669 int sec, start_sec, timeout; 670 671 if (bootverbose) 672 printf("Calibrating clock(s) ... "); 673 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 674 goto fail; 675 timeout = 100000000; 676 677 /* Read the mc146818A seconds counter. */ 678 for (;;) { 679 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 680 sec = rtcin(RTC_SEC); 681 break; 682 } 683 if (--timeout == 0) 684 goto fail; 685 } 686 687 /* Wait for the mC146818A seconds counter to change. */ 688 start_sec = sec; 689 for (;;) { 690 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 691 sec = rtcin(RTC_SEC); 692 if (sec != start_sec) 693 break; 694 } 695 if (--timeout == 0) 696 goto fail; 697 } 698 699 /* Start keeping track of the i8254 counter. */ 700 prev_count = getit(); 701 if (prev_count == 0 || prev_count > timer0_max_count) 702 goto fail; 703 tot_count = 0; 704 705#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 706 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) 707 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 708#endif 709 710 /* 711 * Wait for the mc146818A seconds counter to change. Read the i8254 712 * counter for each iteration since this is convenient and only 713 * costs a few usec of inaccuracy. The timing of the final reads 714 * of the counters almost matches the timing of the initial reads, 715 * so the main cause of inaccuracy is the varying latency from 716 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 717 * rtcin(RTC_SEC) that returns a changed seconds count. The 718 * maximum inaccuracy from this cause is < 10 usec on 486's. 719 */ 720 start_sec = sec; 721 for (;;) { 722 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 723 sec = rtcin(RTC_SEC); 724 count = getit(); 725 if (count == 0 || count > timer0_max_count) 726 goto fail; 727 if (count > prev_count) 728 tot_count += prev_count - (count - timer0_max_count); 729 else 730 tot_count += prev_count - count; 731 prev_count = count; 732 if (sec != start_sec) 733 break; 734 if (--timeout == 0) 735 goto fail; 736 } 737 738#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 739 /* 740 * Read the cpu cycle counter. The timing considerations are 741 * similar to those for the i8254 clock. 742 */ 743 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) { 744 set_i586_ctr_freq((u_int)rdtsc(), tot_count); 745 if (bootverbose) 746 printf("i586 clock: %u Hz, ", i586_ctr_freq); 747 } 748#endif 749 750 if (bootverbose) 751 printf("i8254 clock: %u Hz\n", tot_count); 752 return (tot_count); 753 754fail: 755 if (bootverbose) 756 printf("failed, using default i8254 clock of %u Hz\n", 757 timer_freq); 758 return (timer_freq); 759} 760#endif /* !PC98 */ 761 762static void 763set_timer_freq(u_int freq, int intr_freq) 764{ 765 u_long ef; 766 767 ef = read_eflags(); 768 disable_intr(); 769 timer_freq = freq; 770 timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 771 timer0_overflow_threshold = timer0_max_count - TIMER0_LATCH_COUNT; 772 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 773 outb(TIMER_CNTR0, timer0_max_count & 0xff); 774 outb(TIMER_CNTR0, timer0_max_count >> 8); 775 write_eflags(ef); 776} 777 778/* 779 * Initialize 8253 timer 0 early so that it can be used in DELAY(). 780 * XXX initialization of other timers is unintentionally left blank. 781 */ 782void 783startrtclock() 784{ 785 u_int delta, freq; 786 787#ifdef PC98 788 findcpuspeed(); 789#ifndef AUTO_CLOCK 790 if (pc98_machine_type & M_8M) { 791#ifndef PC98_8M 792 printf("you must reconfig a kernel with \"PC98_8M\" option.\n"); 793#endif 794 } else { 795#ifdef PC98_8M 796 printf("You must reconfig a kernel without \"PC98_8M\" option.\n"); 797#endif 798 } 799#else /* AUTO_CLOCK */ 800 if (pc98_machine_type & M_8M) 801 timer_freq = 1996800L; /* 1.9968 MHz */ 802 else 803 timer_freq = 2457600L; /* 2.4576 MHz */ 804#endif /* AUTO_CLOCK */ 805#endif /* PC98 */ 806 807#ifndef PC98 808 writertc(RTC_STATUSA, rtc_statusa); 809 writertc(RTC_STATUSB, RTCSB_24HR); 810#endif 811 812#ifndef PC98 813 set_timer_freq(timer_freq, hz); 814 freq = calibrate_clocks(); 815#ifdef CLK_CALIBRATION_LOOP 816 if (bootverbose) { 817 printf( 818 "Press a key on the console to abort clock calibration\n"); 819 while (cncheckc() == -1) 820 calibrate_clocks(); 821 } 822#endif 823 824 /* 825 * Use the calibrated i8254 frequency if it seems reasonable. 826 * Otherwise use the default, and don't use the calibrated i586 827 * frequency. 828 */ 829 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 830 if (delta < timer_freq / 100) { 831#ifndef CLK_USE_I8254_CALIBRATION 832 if (bootverbose) 833 printf( 834"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 835 freq = timer_freq; 836#endif 837 timer_freq = freq; 838 } else { 839 if (bootverbose) 840 printf( 841 "%d Hz differs from default of %d Hz by more than 1%%\n", 842 freq, timer_freq); 843#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 844 i586_ctr_freq = 0; 845#endif 846 } 847#endif 848 849 set_timer_freq(timer_freq, hz); 850 851#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 852#ifndef CLK_USE_I586_CALIBRATION 853 if (i586_ctr_freq != 0) { 854 if (bootverbose) 855 printf( 856"CLK_USE_I586_CALIBRATION not specified - using old calibration method\n"); 857 i586_ctr_freq = 0; 858 } 859#endif 860 if (i586_ctr_freq == 0 && 861 (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686)) { 862 /* 863 * Calibration of the i586 clock relative to the mc146818A 864 * clock failed. Do a less accurate calibration relative 865 * to the i8254 clock. 866 */ 867 wrmsr(0x10, 0LL); /* XXX */ 868 DELAY(1000000); 869 set_i586_ctr_freq((u_int)rdtsc(), timer_freq); 870#ifdef CLK_USE_I586_CALIBRATION 871 if (bootverbose) 872 printf("i586 clock: %u Hz\n", i586_ctr_freq); 873#endif 874 } 875#endif 876} 877 878#ifdef PC98 879static void 880rtc_serialcombit(int i) 881{ 882 outb(IO_RTC, ((i&0x01)<<5)|0x07); 883 DELAY(1); 884 outb(IO_RTC, ((i&0x01)<<5)|0x17); 885 DELAY(1); 886 outb(IO_RTC, ((i&0x01)<<5)|0x07); 887 DELAY(1); 888} 889 890static void 891rtc_serialcom(int i) 892{ 893 rtc_serialcombit(i&0x01); 894 rtc_serialcombit((i&0x02)>>1); 895 rtc_serialcombit((i&0x04)>>2); 896 rtc_serialcombit((i&0x08)>>3); 897 outb(IO_RTC, 0x07); 898 DELAY(1); 899 outb(IO_RTC, 0x0f); 900 DELAY(1); 901 outb(IO_RTC, 0x07); 902 DELAY(1); 903} 904 905static void 906rtc_outb(int val) 907{ 908 int s; 909 int sa = 0; 910 911 for (s=0;s<8;s++) { 912 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 913 outb(IO_RTC, sa); /* set DI & CLK 0 */ 914 DELAY(1); 915 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 916 DELAY(1); 917 } 918 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 919} 920 921static int 922rtc_inb(void) 923{ 924 int s; 925 int sa = 0; 926 927 for (s=0;s<8;s++) { 928 sa |= ((inb(0x33) & 0x01) << s); 929 outb(IO_RTC, 0x17); /* CLK 1 */ 930 DELAY(1); 931 outb(IO_RTC, 0x07); /* CLK 0 */ 932 DELAY(2); 933 } 934 return sa; 935} 936#endif /* PC-98 */ 937 938/* 939 * Initialize the time of day register, based on the time base which is, e.g. 940 * from a filesystem. 941 */ 942void 943inittodr(time_t base) 944{ 945 unsigned long sec, days; 946 int yd; 947 int year, month; 948 int y, m, s; 949#ifdef PC98 950 int second, min, hour; 951#endif 952 953 s = splclock(); 954 time.tv_sec = base; 955 time.tv_usec = 0; 956 splx(s); 957 958#ifdef PC98 959 rtc_serialcom(0x03); /* Time Read */ 960 rtc_serialcom(0x01); /* Register shift command. */ 961 DELAY(20); 962 963 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 964 min = bcd2bin(rtc_inb() & 0xff); /* min */ 965 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 966 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 967 968 month = (rtc_inb() >> 4) & 0x0f; /* month */ 969 for (m = 1; m < month; m++) 970 days += daysinmonth[m-1]; 971 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 972 /* 2000 year problem */ 973 if (year < 1995) 974 year += 100; 975 if (year < 1970) 976 goto wrong_time; 977 for (y = 1970; y < year; y++) 978 days += DAYSPERYEAR + LEAPYEAR(y); 979 if ((month > 2) && LEAPYEAR(year)) 980 days ++; 981 sec = ((( days * 24 + 982 hour) * 60 + 983 min) * 60 + 984 second); 985 /* sec now contains the number of seconds, since Jan 1 1970, 986 in the local time zone */ 987#else /* IBM-PC */ 988 /* Look if we have a RTC present and the time is valid */ 989 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 990 goto wrong_time; 991 992 /* wait for time update to complete */ 993 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 994 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 995 996 days = 0; 997#ifdef USE_RTC_CENTURY 998 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 999#else 1000 year = readrtc(RTC_YEAR) + 1900; 1001 if (year < 1970) 1002 year += 100; 1003#endif 1004 if (year < 1970) 1005 goto wrong_time; 1006 month = readrtc(RTC_MONTH); 1007 for (m = 1; m < month; m++) 1008 days += daysinmonth[m-1]; 1009 if ((month > 2) && LEAPYEAR(year)) 1010 days ++; 1011 days += readrtc(RTC_DAY) - 1; 1012 yd = days; 1013 for (y = 1970; y < year; y++) 1014 days += DAYSPERYEAR + LEAPYEAR(y); 1015 sec = ((( days * 24 + 1016 readrtc(RTC_HRS)) * 60 + 1017 readrtc(RTC_MIN)) * 60 + 1018 readrtc(RTC_SEC)); 1019 /* sec now contains the number of seconds, since Jan 1 1970, 1020 in the local time zone */ 1021#endif 1022 1023 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1024 1025 s = splclock(); 1026 time.tv_sec = sec; 1027 splx(s); 1028 return; 1029 1030wrong_time: 1031 printf("Invalid time in real time clock.\n"); 1032 printf("Check and reset the date immediately!\n"); 1033} 1034 1035/* 1036 * Write system time back to RTC 1037 */ 1038void 1039resettodr() 1040{ 1041 unsigned long tm; 1042 int y, m, s; 1043#ifdef PC98 1044 int wd; 1045#endif 1046 1047 if (disable_rtc_set) 1048 return; 1049 1050 s = splclock(); 1051 tm = time.tv_sec; 1052 splx(s); 1053 1054#ifdef PC98 1055 rtc_serialcom(0x01); /* Register shift command. */ 1056 1057 /* Calculate local time to put in RTC */ 1058 1059 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1060 1061 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1062 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1063 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1064 1065 /* We have now the days since 01-01-1970 in tm */ 1066 wd = (tm+4)%7; 1067 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1068 tm >= m; 1069 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1070 tm -= m; 1071 1072 /* Now we have the years in y and the day-of-the-year in tm */ 1073 for (m = 0; ; m++) { 1074 int ml; 1075 1076 ml = daysinmonth[m]; 1077 if (m == 1 && LEAPYEAR(y)) 1078 ml++; 1079 if (tm < ml) 1080 break; 1081 tm -= ml; 1082 } 1083 1084 m++; 1085 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1086 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1087 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1088 1089 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1090 rtc_serialcom(0x00); /* Register hold command. */ 1091#else 1092 /* Disable RTC updates and interrupts. */ 1093 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1094 1095 /* Calculate local time to put in RTC */ 1096 1097 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1098 1099 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1100 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1101 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1102 1103 /* We have now the days since 01-01-1970 in tm */ 1104 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1105 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1106 tm >= m; 1107 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1108 tm -= m; 1109 1110 /* Now we have the years in y and the day-of-the-year in tm */ 1111 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1112#ifdef USE_RTC_CENTURY 1113 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1114#endif 1115 for (m = 0; ; m++) { 1116 int ml; 1117 1118 ml = daysinmonth[m]; 1119 if (m == 1 && LEAPYEAR(y)) 1120 ml++; 1121 if (tm < ml) 1122 break; 1123 tm -= ml; 1124 } 1125 1126 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1127 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1128 1129 /* Reenable RTC updates and interrupts. */ 1130 writertc(RTC_STATUSB, rtc_statusb); 1131#endif 1132} 1133 1134#ifdef APIC_IO 1135 1136/* XXX FIXME: from icu.s: */ 1137extern u_int vec[]; 1138extern void vec8254 __P((void)); 1139extern void vecRTC __P((void)); 1140extern u_int ivectors[]; 1141extern u_int Xintr8254; 1142extern u_int XintrRTC; 1143extern u_int mask8254; 1144extern u_int maskRTC; 1145 1146#endif /* APIC_IO */ 1147 1148/* 1149 * Start both clocks running. 1150 */ 1151void 1152cpu_initclocks() 1153{ 1154#ifdef APIC_IO 1155 int x; 1156#endif /* APIC_IO */ 1157#ifndef PC98 1158 int diag; 1159 1160 if (statclock_disable) { 1161 /* 1162 * The stat interrupt mask is different without the 1163 * statistics clock. Also, don't set the interrupt 1164 * flag which would normally cause the RTC to generate 1165 * interrupts. 1166 */ 1167 stat_imask = HWI_MASK | SWI_MASK; 1168 rtc_statusb = RTCSB_24HR; 1169 } else { 1170 /* Setting stathz to nonzero early helps avoid races. */ 1171 stathz = RTC_NOPROFRATE; 1172 profhz = RTC_PROFRATE; 1173 } 1174#endif 1175 1176 /* Finish initializing 8253 timer 0. */ 1177#ifdef APIC_IO 1178#ifndef IO_ICU1 1179#ifdef PC98 1180#define IO_ICU1 0x20 1181#else 1182#define IO_ICU1 0x20 1183#endif 1184#endif /* IO_ICU1 */ 1185 1186 /* 8254 is traditionally on ISA IRQ0 */ 1187 if ((x = isa_apic_pin(0)) < 0) { 1188 /* bummer, attempt to redirect thru the 8259 */ 1189 if (bootverbose) 1190 printf("APIC missing 8254 connection\n"); 1191 1192 /* allow 8254 timer to INTerrupt 8259 */ 1193 x = inb(IO_ICU1 + 1); /* current mask in 8259 */ 1194 x &= ~1; /* clear 8254 timer mask */ 1195 outb(IO_ICU1 + 1, x); /* write new mask */ 1196 1197 /* program IO APIC for type 3 INT on INT0 */ 1198 if (ext_int_setup(0, 0) < 0) 1199 panic("8254 redirect impossible!"); 1200 x = 0; /* 8259 is on 0 */ 1201 } 1202 1203 vec[x] = (u_int)vec8254; 1204 Xintr8254 = (u_int)ivectors[x]; /* XXX might need Xfastintr# */ 1205 mask8254 = (1 << x); 1206 register_intr(/* irq */ x, /* XXX id */ 0, /* flags */ 0, 1207 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1208 /* unit */ 0); 1209 INTREN(mask8254); 1210#else 1211 register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, 1212 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1213 /* unit */ 0); 1214 INTREN(IRQ0); 1215#endif /* APIC_IO */ 1216 1217#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 1218 /* 1219 * Finish setting up anti-jitter measures. 1220 */ 1221 if (i586_ctr_freq != 0) 1222 i586_ctr_bias = rdtsc(); 1223#endif 1224 1225#ifndef PC98 1226 /* Initialize RTC. */ 1227 writertc(RTC_STATUSA, rtc_statusa); 1228 writertc(RTC_STATUSB, RTCSB_24HR); 1229 1230 /* Don't bother enabling the statistics clock. */ 1231 if (statclock_disable) 1232 return; 1233 diag = rtcin(RTC_DIAG); 1234 if (diag != 0) 1235 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1236#ifdef APIC_IO 1237 /* RTC is traditionally on ISA IRQ8 */ 1238 if ((x = isa_apic_pin(8)) < 0) 1239 panic("APIC missing RTC connection"); 1240 1241 vec[x] = (u_int)vecRTC; 1242 XintrRTC = (u_int)ivectors[x]; /* XXX might need Xfastintr# */ 1243 maskRTC = (1 << x); 1244 register_intr(/* irq */ x, /* XXX id */ 1, /* flags */ 0, 1245 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1246 /* unit */ 0); 1247 INTREN(maskRTC); 1248#else 1249 register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, 1250 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1251 /* unit */ 0); 1252 INTREN(IRQ8); 1253#endif /* APIC_IO */ 1254 writertc(RTC_STATUSB, rtc_statusb); 1255#endif 1256 1257#ifdef APIC_IO 1258 printf("Enabled INTs: "); 1259 for (x = 0; x < 24; ++x) 1260 if ((imen & (1 << x)) == 0) 1261 printf("%d, ", x); 1262 printf("imen: 0x%08x\n", imen); 1263#endif /* APIC_IO */ 1264} 1265 1266void 1267setstatclockrate(int newhz) 1268{ 1269#ifndef PC98 1270 if (newhz == RTC_PROFRATE) 1271 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1272 else 1273 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1274 writertc(RTC_STATUSA, rtc_statusa); 1275#endif 1276} 1277 1278static int 1279sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1280{ 1281 int error; 1282 u_int freq; 1283 1284 /* 1285 * Use `i8254' instead of `timer' in external names because `timer' 1286 * is is too generic. Should use it everywhere. 1287 */ 1288 freq = timer_freq; 1289 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1290 if (error == 0 && req->newptr != NULL) { 1291 if (timer0_state != 0) 1292 return (EBUSY); /* too much trouble to handle */ 1293 set_timer_freq(freq, hz); 1294#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 1295 set_i586_ctr_freq(i586_ctr_freq, timer_freq); 1296#endif 1297 } 1298 return (error); 1299} 1300 1301SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1302 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1303 1304#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 1305static void 1306set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq) 1307{ 1308 u_int comultiplier, multiplier; 1309 u_long ef; 1310 1311 if (i586_freq == 0) { 1312 i586_ctr_freq = i586_freq; 1313 return; 1314 } 1315 comultiplier = ((unsigned long long)i586_freq 1316 << I586_CTR_COMULTIPLIER_SHIFT) / i8254_freq; 1317 multiplier = (1000000LL << I586_CTR_MULTIPLIER_SHIFT) / i586_freq; 1318 ef = read_eflags(); 1319 disable_intr(); 1320 i586_ctr_freq = i586_freq; 1321 i586_ctr_comultiplier = comultiplier; 1322 i586_ctr_multiplier = multiplier; 1323 write_eflags(ef); 1324} 1325 1326static int 1327sysctl_machdep_i586_freq SYSCTL_HANDLER_ARGS 1328{ 1329 int error; 1330 u_int freq; 1331 1332 if (cpu_class != CPUCLASS_586 && cpu_class != CPUCLASS_686) 1333 return (EOPNOTSUPP); 1334 freq = i586_ctr_freq; 1335 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1336 if (error == 0 && req->newptr != NULL) 1337 set_i586_ctr_freq(freq, timer_freq); 1338 return (error); 1339} 1340 1341SYSCTL_PROC(_machdep, OID_AUTO, i586_freq, CTLTYPE_INT | CTLFLAG_RW, 1342 0, sizeof(u_int), sysctl_machdep_i586_freq, "I", ""); 1343#endif /* (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) */ 1344