pcrtc.c revision 26384
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $Id: clock.c,v 1.24 1997/05/31 12:43:17 kato Exp $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51/* 52 * modified for PC98 by Kakefuda 53 */ 54 55#include "opt_clock.h" 56#include "opt_cpu.h" 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/time.h> 61#include <sys/kernel.h> 62#include <sys/sysctl.h> 63 64#include <machine/clock.h> 65#ifdef CLK_CALIBRATION_LOOP 66#include <machine/cons.h> 67#endif 68#include <machine/cpu.h> 69#include <machine/frame.h> 70#include <machine/ipl.h> 71 72#include <i386/isa/icu.h> 73#ifdef PC98 74#include <pc98/pc98/pc98.h> 75#include <pc98/pc98/pc98_machdep.h> 76#include <i386/isa/isa_device.h> 77#else 78#include <i386/isa/isa.h> 79#include <i386/isa/intr_machdep.h> 80#include <i386/isa/rtc.h> 81#endif 82#include <i386/isa/timerreg.h> 83 84/* 85 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 86 * can use a simple formula for leap years. 87 */ 88#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 89#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 90 91#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 92 93/* 94 * Time in timer cycles that it takes for microtime() to disable interrupts 95 * and latch the count. microtime() currently uses "cli; outb ..." so it 96 * normally takes less than 2 timer cycles. Add a few for cache misses. 97 * Add a few more to allow for latency in bogus calls to microtime() with 98 * interrupts already disabled. 99 */ 100#define TIMER0_LATCH_COUNT 20 101 102/* 103 * Maximum frequency that we are willing to allow for timer0. Must be 104 * low enough to guarantee that the timer interrupt handler returns 105 * before the next timer interrupt. Must result in a lower TIMER_DIV 106 * value than TIMER0_LATCH_COUNT so that we don't have to worry about 107 * underflow in the calculation of timer0_overflow_threshold. 108 */ 109#define TIMER0_MAX_FREQ 20000 110 111int adjkerntz; /* local offset from GMT in seconds */ 112int disable_rtc_set; /* disable resettodr() if != 0 */ 113u_int idelayed; 114#if defined(I586_CPU) || defined(I686_CPU) 115#ifndef SMP 116u_int i586_ctr_bias; 117u_int i586_ctr_comultiplier; 118#endif 119u_int i586_ctr_freq; 120#ifndef SMP 121u_int i586_ctr_multiplier; 122#endif 123#endif 124int statclock_disable; 125u_int stat_imask = SWI_CLOCK_MASK; 126#ifdef TIMER_FREQ 127u_int timer_freq = TIMER_FREQ; 128#else 129#ifdef PC98 130#ifndef AUTO_CLOCK 131#ifndef PC98_8M 132u_int timer_freq = 2457600; 133#else /* !PC98_8M */ 134u_int timer_freq = 1996800; 135#endif /* PC98_8M */ 136#else /* AUTO_CLOCK */ 137u_int timer_freq = 2457600; 138#endif /* AUTO_CLOCK */ 139#else /* IBM-PC */ 140u_int timer_freq = 1193182; 141#endif /* PC98 */ 142#endif 143int timer0_max_count; 144u_int timer0_overflow_threshold; 145u_int timer0_prescaler_count; 146int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 147 148static int beeping = 0; 149static u_int clk_imask = HWI_MASK | SWI_MASK; 150static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 151static u_int hardclock_max_count; 152/* 153 * XXX new_function and timer_func should not handle clockframes, but 154 * timer_func currently needs to hold hardclock to handle the 155 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 156 * to switch between clkintr() and a slightly different timerintr(). 157 */ 158static void (*new_function) __P((struct clockframe *frame)); 159static u_int new_rate; 160#ifndef PC98 161static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 162static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 163#endif 164 165/* Values for timerX_state: */ 166#define RELEASED 0 167#define RELEASE_PENDING 1 168#define ACQUIRED 2 169#define ACQUIRE_PENDING 3 170 171static u_char timer0_state; 172#ifdef PC98 173static u_char timer1_state; 174#endif 175static u_char timer2_state; 176static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 177#ifdef PC98 178static void rtc_serialcombit __P((int)); 179static void rtc_serialcom __P((int)); 180static int rtc_inb __P((void)); 181static void rtc_outb __P((int)); 182#endif 183 184#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 185static void set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq); 186#endif 187static void set_timer_freq(u_int freq, int intr_freq); 188 189static void 190clkintr(struct clockframe frame) 191{ 192 timer_func(&frame); 193 switch (timer0_state) { 194 195 case RELEASED: 196 setdelayed(); 197 break; 198 199 case ACQUIRED: 200 if ((timer0_prescaler_count += timer0_max_count) 201 >= hardclock_max_count) { 202 hardclock(&frame); 203 setdelayed(); 204 timer0_prescaler_count -= hardclock_max_count; 205 } 206 break; 207 208 case ACQUIRE_PENDING: 209 setdelayed(); 210 timer0_max_count = TIMER_DIV(new_rate); 211 timer0_overflow_threshold = 212 timer0_max_count - TIMER0_LATCH_COUNT; 213 disable_intr(); 214 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 215 outb(TIMER_CNTR0, timer0_max_count & 0xff); 216 outb(TIMER_CNTR0, timer0_max_count >> 8); 217 enable_intr(); 218 timer0_prescaler_count = 0; 219 timer_func = new_function; 220 timer0_state = ACQUIRED; 221 break; 222 223 case RELEASE_PENDING: 224 if ((timer0_prescaler_count += timer0_max_count) 225 >= hardclock_max_count) { 226 hardclock(&frame); 227 setdelayed(); 228 timer0_max_count = hardclock_max_count; 229 timer0_overflow_threshold = 230 timer0_max_count - TIMER0_LATCH_COUNT; 231 disable_intr(); 232 outb(TIMER_MODE, 233 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 234 outb(TIMER_CNTR0, timer0_max_count & 0xff); 235 outb(TIMER_CNTR0, timer0_max_count >> 8); 236 enable_intr(); 237 /* 238 * See microtime.s for this magic. 239 */ 240#ifdef PC98 241#ifndef AUTO_CLOCK 242#ifndef PC98_8M 243 time.tv_usec += (6667 * 244 (timer0_prescaler_count - hardclock_max_count)) 245 >> 14; 246#else /* PC98_8M */ 247 time.tv_usec += (16411 * 248 (timer0_prescaler_count - hardclock_max_count)) 249 >> 15; 250#endif /* PC98_8M */ 251#else /* AUTO_CLOCK */ 252 if (pc98_machine_type & M_8M) { 253 /* PC98_8M */ 254 time.tv_usec += (16411 * 255 (timer0_prescaler_count - 256 hardclock_max_count)) >> 15; 257 } else { 258 time.tv_usec += (6667 * 259 (timer0_prescaler_count - 260 hardclock_max_count)) >> 14; 261 } 262#endif /* AUTO_CLOCK */ 263#else /* IBM-PC */ 264 time.tv_usec += (27465 * 265 (timer0_prescaler_count - hardclock_max_count)) 266 >> 15; 267#endif /* PC98 */ 268 if (time.tv_usec >= 1000000) 269 time.tv_usec -= 1000000; 270 timer0_prescaler_count = 0; 271 timer_func = hardclock; 272 timer0_state = RELEASED; 273 } 274 break; 275 } 276} 277 278/* 279 * The acquire and release functions must be called at ipl >= splclock(). 280 */ 281int 282acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 283{ 284 static int old_rate; 285 286 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 287 return (-1); 288 switch (timer0_state) { 289 290 case RELEASED: 291 timer0_state = ACQUIRE_PENDING; 292 break; 293 294 case RELEASE_PENDING: 295 if (rate != old_rate) 296 return (-1); 297 /* 298 * The timer has been released recently, but is being 299 * re-acquired before the release completed. In this 300 * case, we simply reclaim it as if it had not been 301 * released at all. 302 */ 303 timer0_state = ACQUIRED; 304 break; 305 306 default: 307 return (-1); /* busy */ 308 } 309 new_function = function; 310 old_rate = new_rate = rate; 311 return (0); 312} 313 314#ifdef PC98 315int 316acquire_timer1(int mode) 317{ 318 319 if (timer1_state != RELEASED) 320 return (-1); 321 timer1_state = ACQUIRED; 322 323 /* 324 * This access to the timer registers is as atomic as possible 325 * because it is a single instruction. We could do better if we 326 * knew the rate. Use of splclock() limits glitches to 10-100us, 327 * and this is probably good enough for timer2, so we aren't as 328 * careful with it as with timer0. 329 */ 330 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 331 332 return (0); 333} 334#endif 335 336int 337acquire_timer2(int mode) 338{ 339 340 if (timer2_state != RELEASED) 341 return (-1); 342 timer2_state = ACQUIRED; 343 344 /* 345 * This access to the timer registers is as atomic as possible 346 * because it is a single instruction. We could do better if we 347 * knew the rate. Use of splclock() limits glitches to 10-100us, 348 * and this is probably good enough for timer2, so we aren't as 349 * careful with it as with timer0. 350 */ 351 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 352 353 return (0); 354} 355 356int 357release_timer0() 358{ 359 switch (timer0_state) { 360 361 case ACQUIRED: 362 timer0_state = RELEASE_PENDING; 363 break; 364 365 case ACQUIRE_PENDING: 366 /* Nothing happened yet, release quickly. */ 367 timer0_state = RELEASED; 368 break; 369 370 default: 371 return (-1); 372 } 373 return (0); 374} 375 376#ifdef PC98 377int 378release_timer1() 379{ 380 381 if (timer1_state != ACQUIRED) 382 return (-1); 383 timer1_state = RELEASED; 384 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 385 return (0); 386} 387#endif 388 389int 390release_timer2() 391{ 392 393 if (timer2_state != ACQUIRED) 394 return (-1); 395 timer2_state = RELEASED; 396 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 397 return (0); 398} 399 400#ifndef PC98 401/* 402 * This routine receives statistical clock interrupts from the RTC. 403 * As explained above, these occur at 128 interrupts per second. 404 * When profiling, we receive interrupts at a rate of 1024 Hz. 405 * 406 * This does not actually add as much overhead as it sounds, because 407 * when the statistical clock is active, the hardclock driver no longer 408 * needs to keep (inaccurate) statistics on its own. This decouples 409 * statistics gathering from scheduling interrupts. 410 * 411 * The RTC chip requires that we read status register C (RTC_INTR) 412 * to acknowledge an interrupt, before it will generate the next one. 413 * Under high interrupt load, rtcintr() can be indefinitely delayed and 414 * the clock can tick immediately after the read from RTC_INTR. In this 415 * case, the mc146818A interrupt signal will not drop for long enough 416 * to register with the 8259 PIC. If an interrupt is missed, the stat 417 * clock will halt, considerably degrading system performance. This is 418 * why we use 'while' rather than a more straightforward 'if' below. 419 * Stat clock ticks can still be lost, causing minor loss of accuracy 420 * in the statistics, but the stat clock will no longer stop. 421 */ 422static void 423rtcintr(struct clockframe frame) 424{ 425 while (rtcin(RTC_INTR) & RTCIR_PERIOD) 426 statclock(&frame); 427} 428 429#include "opt_ddb.h" 430#ifdef DDB 431#include <ddb/ddb.h> 432 433DB_SHOW_COMMAND(rtc, rtc) 434{ 435 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 436 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 437 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 438 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 439} 440#endif /* DDB */ 441#endif /* for PC98 */ 442 443static int 444getit(void) 445{ 446 u_long ef; 447 int high, low; 448 449 ef = read_eflags(); 450 disable_intr(); 451 452 /* Select timer0 and latch counter value. */ 453 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 454 455 low = inb(TIMER_CNTR0); 456 high = inb(TIMER_CNTR0); 457 458 write_eflags(ef); 459 return ((high << 8) | low); 460} 461 462/* 463 * Wait "n" microseconds. 464 * Relies on timer 1 counting down from (timer_freq / hz) 465 * Note: timer had better have been programmed before this is first used! 466 */ 467void 468DELAY(int n) 469{ 470 int delta, prev_tick, tick, ticks_left; 471 472#ifdef DELAYDEBUG 473 int getit_calls = 1; 474 int n1; 475 static int state = 0; 476 477 if (state == 0) { 478 state = 1; 479 for (n1 = 1; n1 <= 10000000; n1 *= 10) 480 DELAY(n1); 481 state = 2; 482 } 483 if (state == 1) 484 printf("DELAY(%d)...", n); 485#endif 486 /* 487 * Guard against the timer being uninitialized if we are called 488 * early for console i/o. 489 */ 490 if (timer0_max_count == 0) 491 set_timer_freq(timer_freq, hz); 492 493 /* 494 * Read the counter first, so that the rest of the setup overhead is 495 * counted. Guess the initial overhead is 20 usec (on most systems it 496 * takes about 1.5 usec for each of the i/o's in getit(). The loop 497 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 498 * multiplications and divisions to scale the count take a while). 499 */ 500 prev_tick = getit(); 501 n -= 0; /* XXX actually guess no initial overhead */ 502 /* 503 * Calculate (n * (timer_freq / 1e6)) without using floating point 504 * and without any avoidable overflows. 505 */ 506 if (n <= 0) 507 ticks_left = 0; 508 else if (n < 256) 509 /* 510 * Use fixed point to avoid a slow division by 1000000. 511 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 512 * 2^15 is the first power of 2 that gives exact results 513 * for n between 0 and 256. 514 */ 515 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 516 else 517 /* 518 * Don't bother using fixed point, although gcc-2.7.2 519 * generates particularly poor code for the long long 520 * division, since even the slow way will complete long 521 * before the delay is up (unless we're interrupted). 522 */ 523 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 524 / 1000000; 525 526 while (ticks_left > 0) { 527 tick = getit(); 528#ifdef DELAYDEBUG 529 ++getit_calls; 530#endif 531 delta = prev_tick - tick; 532 prev_tick = tick; 533 if (delta < 0) { 534 delta += timer0_max_count; 535 /* 536 * Guard against timer0_max_count being wrong. 537 * This shouldn't happen in normal operation, 538 * but it may happen if set_timer_freq() is 539 * traced. 540 */ 541 if (delta < 0) 542 delta = 0; 543 } 544 ticks_left -= delta; 545 } 546#ifdef DELAYDEBUG 547 if (state == 1) 548 printf(" %d calls to getit() at %d usec each\n", 549 getit_calls, (n + 5) / getit_calls); 550#endif 551} 552 553static void 554sysbeepstop(void *chan) 555{ 556#ifdef PC98 /* PC98 */ 557 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 558 release_timer1(); 559#else 560 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 561 release_timer2(); 562#endif 563 beeping = 0; 564} 565 566int 567sysbeep(int pitch, int period) 568{ 569 int x = splclock(); 570 571#ifdef PC98 572 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 573 if (!beeping) { 574 /* Something else owns it. */ 575 splx(x); 576 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 577 } 578 disable_intr(); 579 outb(0x3fdb, pitch); 580 outb(0x3fdb, (pitch>>8)); 581 enable_intr(); 582 if (!beeping) { 583 /* enable counter1 output to speaker */ 584 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 585 beeping = period; 586 timeout(sysbeepstop, (void *)NULL, period); 587 } 588#else 589 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 590 if (!beeping) { 591 /* Something else owns it. */ 592 splx(x); 593 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 594 } 595 disable_intr(); 596 outb(TIMER_CNTR2, pitch); 597 outb(TIMER_CNTR2, (pitch>>8)); 598 enable_intr(); 599 if (!beeping) { 600 /* enable counter2 output to speaker */ 601 outb(IO_PPI, inb(IO_PPI) | 3); 602 beeping = period; 603 timeout(sysbeepstop, (void *)NULL, period); 604 } 605#endif 606 splx(x); 607 return (0); 608} 609 610#ifndef PC98 611/* 612 * RTC support routines 613 */ 614 615int 616rtcin(reg) 617 int reg; 618{ 619 u_char val; 620 621 outb(IO_RTC, reg); 622 inb(0x84); 623 val = inb(IO_RTC + 1); 624 inb(0x84); 625 return (val); 626} 627 628static __inline void 629writertc(u_char reg, u_char val) 630{ 631 outb(IO_RTC, reg); 632 outb(IO_RTC + 1, val); 633} 634 635static __inline int 636readrtc(int port) 637{ 638 return(bcd2bin(rtcin(port))); 639} 640#endif 641 642#ifdef PC98 643unsigned int delaycount; 644#define FIRST_GUESS 0x2000 645static void findcpuspeed(void) 646{ 647 int i; 648 int remainder; 649 650 /* Put counter in count down mode */ 651 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 652 outb(TIMER_CNTR0, 0xff); 653 outb(TIMER_CNTR0, 0xff); 654 for (i = FIRST_GUESS; i; i--) 655 ; 656 remainder = getit(); 657 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 658} 659#endif 660 661#ifndef PC98 662static u_int 663calibrate_clocks(void) 664{ 665 u_int count, prev_count, tot_count; 666 int sec, start_sec, timeout; 667 668 if (bootverbose) 669 printf("Calibrating clock(s) ... "); 670 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 671 goto fail; 672 timeout = 100000000; 673 674 /* Read the mc146818A seconds counter. */ 675 for (;;) { 676 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 677 sec = rtcin(RTC_SEC); 678 break; 679 } 680 if (--timeout == 0) 681 goto fail; 682 } 683 684 /* Wait for the mC146818A seconds counter to change. */ 685 start_sec = sec; 686 for (;;) { 687 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 688 sec = rtcin(RTC_SEC); 689 if (sec != start_sec) 690 break; 691 } 692 if (--timeout == 0) 693 goto fail; 694 } 695 696 /* Start keeping track of the i8254 counter. */ 697 prev_count = getit(); 698 if (prev_count == 0 || prev_count > timer0_max_count) 699 goto fail; 700 tot_count = 0; 701 702#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 703 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) 704 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 705#endif 706 707 /* 708 * Wait for the mc146818A seconds counter to change. Read the i8254 709 * counter for each iteration since this is convenient and only 710 * costs a few usec of inaccuracy. The timing of the final reads 711 * of the counters almost matches the timing of the initial reads, 712 * so the main cause of inaccuracy is the varying latency from 713 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 714 * rtcin(RTC_SEC) that returns a changed seconds count. The 715 * maximum inaccuracy from this cause is < 10 usec on 486's. 716 */ 717 start_sec = sec; 718 for (;;) { 719 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 720 sec = rtcin(RTC_SEC); 721 count = getit(); 722 if (count == 0 || count > timer0_max_count) 723 goto fail; 724 if (count > prev_count) 725 tot_count += prev_count - (count - timer0_max_count); 726 else 727 tot_count += prev_count - count; 728 prev_count = count; 729 if (sec != start_sec) 730 break; 731 if (--timeout == 0) 732 goto fail; 733 } 734 735#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 736 /* 737 * Read the cpu cycle counter. The timing considerations are 738 * similar to those for the i8254 clock. 739 */ 740 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) { 741 set_i586_ctr_freq((u_int)rdtsc(), tot_count); 742 if (bootverbose) 743 printf("i586 clock: %u Hz, ", i586_ctr_freq); 744 } 745#endif 746 747 if (bootverbose) 748 printf("i8254 clock: %u Hz\n", tot_count); 749 return (tot_count); 750 751fail: 752 if (bootverbose) 753 printf("failed, using default i8254 clock of %u Hz\n", 754 timer_freq); 755 return (timer_freq); 756} 757#endif /* !PC98 */ 758 759static void 760set_timer_freq(u_int freq, int intr_freq) 761{ 762 u_long ef; 763 764 ef = read_eflags(); 765 disable_intr(); 766 timer_freq = freq; 767 timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 768 timer0_overflow_threshold = timer0_max_count - TIMER0_LATCH_COUNT; 769 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 770 outb(TIMER_CNTR0, timer0_max_count & 0xff); 771 outb(TIMER_CNTR0, timer0_max_count >> 8); 772 write_eflags(ef); 773} 774 775/* 776 * Initialize 8253 timer 0 early so that it can be used in DELAY(). 777 * XXX initialization of other timers is unintentionally left blank. 778 */ 779void 780startrtclock() 781{ 782 u_int delta, freq; 783 784#ifdef PC98 785 findcpuspeed(); 786#ifndef AUTO_CLOCK 787 if (pc98_machine_type & M_8M) { 788#ifndef PC98_8M 789 printf("you must reconfig a kernel with \"PC98_8M\" option.\n"); 790#endif 791 } else { 792#ifdef PC98_8M 793 printf("You must reconfig a kernel without \"PC98_8M\" option.\n"); 794#endif 795 } 796#else /* AUTO_CLOCK */ 797 if (pc98_machine_type & M_8M) 798 timer_freq = 1996800L; /* 1.9968 MHz */ 799 else 800 timer_freq = 2457600L; /* 2.4576 MHz */ 801#endif /* AUTO_CLOCK */ 802#endif /* PC98 */ 803 804#ifndef PC98 805 writertc(RTC_STATUSA, rtc_statusa); 806 writertc(RTC_STATUSB, RTCSB_24HR); 807#endif 808 809#ifndef PC98 810 set_timer_freq(timer_freq, hz); 811 freq = calibrate_clocks(); 812#ifdef CLK_CALIBRATION_LOOP 813 if (bootverbose) { 814 printf( 815 "Press a key on the console to abort clock calibration\n"); 816 while (cncheckc() == -1) 817 calibrate_clocks(); 818 } 819#endif 820 821 /* 822 * Use the calibrated i8254 frequency if it seems reasonable. 823 * Otherwise use the default, and don't use the calibrated i586 824 * frequency. 825 */ 826 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 827 if (delta < timer_freq / 100) { 828#ifndef CLK_USE_I8254_CALIBRATION 829 if (bootverbose) 830 printf( 831"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 832 freq = timer_freq; 833#endif 834 timer_freq = freq; 835 } else { 836 if (bootverbose) 837 printf( 838 "%d Hz differs from default of %d Hz by more than 1%%\n", 839 freq, timer_freq); 840#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 841 i586_ctr_freq = 0; 842#endif 843 } 844#endif 845 846 set_timer_freq(timer_freq, hz); 847 848#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 849#ifndef CLK_USE_I586_CALIBRATION 850 if (i586_ctr_freq != 0) { 851 if (bootverbose) 852 printf( 853"CLK_USE_I586_CALIBRATION not specified - using old calibration method\n"); 854 i586_ctr_freq = 0; 855 } 856#endif 857 if (i586_ctr_freq == 0 && 858 (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686)) { 859 /* 860 * Calibration of the i586 clock relative to the mc146818A 861 * clock failed. Do a less accurate calibration relative 862 * to the i8254 clock. 863 */ 864 wrmsr(0x10, 0LL); /* XXX */ 865 DELAY(1000000); 866 set_i586_ctr_freq((u_int)rdtsc(), timer_freq); 867#ifdef CLK_USE_I586_CALIBRATION 868 if (bootverbose) 869 printf("i586 clock: %u Hz\n", i586_ctr_freq); 870#endif 871 } 872#endif 873} 874 875#ifdef PC98 876static void 877rtc_serialcombit(int i) 878{ 879 outb(IO_RTC, ((i&0x01)<<5)|0x07); 880 DELAY(1); 881 outb(IO_RTC, ((i&0x01)<<5)|0x17); 882 DELAY(1); 883 outb(IO_RTC, ((i&0x01)<<5)|0x07); 884 DELAY(1); 885} 886 887static void 888rtc_serialcom(int i) 889{ 890 rtc_serialcombit(i&0x01); 891 rtc_serialcombit((i&0x02)>>1); 892 rtc_serialcombit((i&0x04)>>2); 893 rtc_serialcombit((i&0x08)>>3); 894 outb(IO_RTC, 0x07); 895 DELAY(1); 896 outb(IO_RTC, 0x0f); 897 DELAY(1); 898 outb(IO_RTC, 0x07); 899 DELAY(1); 900} 901 902static void 903rtc_outb(int val) 904{ 905 int s; 906 int sa = 0; 907 908 for (s=0;s<8;s++) { 909 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 910 outb(IO_RTC, sa); /* set DI & CLK 0 */ 911 DELAY(1); 912 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 913 DELAY(1); 914 } 915 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 916} 917 918static int 919rtc_inb(void) 920{ 921 int s; 922 int sa = 0; 923 924 for (s=0;s<8;s++) { 925 sa |= ((inb(0x33) & 0x01) << s); 926 outb(IO_RTC, 0x17); /* CLK 1 */ 927 DELAY(1); 928 outb(IO_RTC, 0x07); /* CLK 0 */ 929 DELAY(2); 930 } 931 return sa; 932} 933#endif /* PC-98 */ 934 935/* 936 * Initialize the time of day register, based on the time base which is, e.g. 937 * from a filesystem. 938 */ 939void 940inittodr(time_t base) 941{ 942 unsigned long sec, days; 943 int yd; 944 int year, month; 945 int y, m, s; 946#ifdef PC98 947 int second, min, hour; 948#endif 949 950 s = splclock(); 951 time.tv_sec = base; 952 time.tv_usec = 0; 953 splx(s); 954 955#ifdef PC98 956 rtc_serialcom(0x03); /* Time Read */ 957 rtc_serialcom(0x01); /* Register shift command. */ 958 DELAY(20); 959 960 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 961 min = bcd2bin(rtc_inb() & 0xff); /* min */ 962 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 963 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 964 965 month = (rtc_inb() >> 4) & 0x0f; /* month */ 966 for (m = 1; m < month; m++) 967 days += daysinmonth[m-1]; 968 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 969 /* 2000 year problem */ 970 if (year < 1995) 971 year += 100; 972 if (year < 1970) 973 goto wrong_time; 974 for (y = 1970; y < year; y++) 975 days += DAYSPERYEAR + LEAPYEAR(y); 976 if ((month > 2) && LEAPYEAR(year)) 977 days ++; 978 sec = ((( days * 24 + 979 hour) * 60 + 980 min) * 60 + 981 second); 982 /* sec now contains the number of seconds, since Jan 1 1970, 983 in the local time zone */ 984#else /* IBM-PC */ 985 /* Look if we have a RTC present and the time is valid */ 986 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 987 goto wrong_time; 988 989 /* wait for time update to complete */ 990 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 991 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 992 993 days = 0; 994#ifdef USE_RTC_CENTURY 995 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 996#else 997 year = readrtc(RTC_YEAR) + 1900; 998 if (year < 1970) 999 year += 100; 1000#endif 1001 if (year < 1970) 1002 goto wrong_time; 1003 month = readrtc(RTC_MONTH); 1004 for (m = 1; m < month; m++) 1005 days += daysinmonth[m-1]; 1006 if ((month > 2) && LEAPYEAR(year)) 1007 days ++; 1008 days += readrtc(RTC_DAY) - 1; 1009 yd = days; 1010 for (y = 1970; y < year; y++) 1011 days += DAYSPERYEAR + LEAPYEAR(y); 1012 sec = ((( days * 24 + 1013 readrtc(RTC_HRS)) * 60 + 1014 readrtc(RTC_MIN)) * 60 + 1015 readrtc(RTC_SEC)); 1016 /* sec now contains the number of seconds, since Jan 1 1970, 1017 in the local time zone */ 1018#endif 1019 1020 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1021 1022 s = splclock(); 1023 time.tv_sec = sec; 1024 splx(s); 1025 return; 1026 1027wrong_time: 1028 printf("Invalid time in real time clock.\n"); 1029 printf("Check and reset the date immediately!\n"); 1030} 1031 1032/* 1033 * Write system time back to RTC 1034 */ 1035void 1036resettodr() 1037{ 1038 unsigned long tm; 1039 int y, m, s; 1040#ifdef PC98 1041 int wd; 1042#endif 1043 1044 if (disable_rtc_set) 1045 return; 1046 1047 s = splclock(); 1048 tm = time.tv_sec; 1049 splx(s); 1050 1051#ifdef PC98 1052 rtc_serialcom(0x01); /* Register shift command. */ 1053 1054 /* Calculate local time to put in RTC */ 1055 1056 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1057 1058 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1059 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1060 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1061 1062 /* We have now the days since 01-01-1970 in tm */ 1063 wd = (tm+4)%7; 1064 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1065 tm >= m; 1066 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1067 tm -= m; 1068 1069 /* Now we have the years in y and the day-of-the-year in tm */ 1070 for (m = 0; ; m++) { 1071 int ml; 1072 1073 ml = daysinmonth[m]; 1074 if (m == 1 && LEAPYEAR(y)) 1075 ml++; 1076 if (tm < ml) 1077 break; 1078 tm -= ml; 1079 } 1080 1081 m++; 1082 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1083 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1084 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1085 1086 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1087 rtc_serialcom(0x00); /* Register hold command. */ 1088#else 1089 /* Disable RTC updates and interrupts. */ 1090 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1091 1092 /* Calculate local time to put in RTC */ 1093 1094 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1095 1096 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1097 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1098 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1099 1100 /* We have now the days since 01-01-1970 in tm */ 1101 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1102 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1103 tm >= m; 1104 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1105 tm -= m; 1106 1107 /* Now we have the years in y and the day-of-the-year in tm */ 1108 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1109#ifdef USE_RTC_CENTURY 1110 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1111#endif 1112 for (m = 0; ; m++) { 1113 int ml; 1114 1115 ml = daysinmonth[m]; 1116 if (m == 1 && LEAPYEAR(y)) 1117 ml++; 1118 if (tm < ml) 1119 break; 1120 tm -= ml; 1121 } 1122 1123 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1124 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1125 1126 /* Reenable RTC updates and interrupts. */ 1127 writertc(RTC_STATUSB, rtc_statusb); 1128#endif 1129} 1130 1131#if defined(APIC_IO) 1132 1133/* from icu.s: */ 1134extern u_int vec[]; 1135extern void vec8254 __P((void)); 1136extern void vecRTC __P((void)); 1137extern u_int ivectors[]; 1138extern u_int Xintr8254; 1139extern u_int XintrRTC; 1140extern u_int mask8254; 1141extern u_int maskRTC; 1142 1143#endif /* APIC_IO */ 1144 1145/* 1146 * Start both clocks running. 1147 */ 1148void 1149cpu_initclocks() 1150{ 1151#if defined(APIC_IO) 1152 int x; 1153#endif /* APIC_IO */ 1154#ifndef PC98 1155 int diag; 1156 1157 if (statclock_disable) { 1158 /* 1159 * The stat interrupt mask is different without the 1160 * statistics clock. Also, don't set the interrupt 1161 * flag which would normally cause the RTC to generate 1162 * interrupts. 1163 */ 1164 stat_imask = HWI_MASK | SWI_MASK; 1165 rtc_statusb = RTCSB_24HR; 1166 } else { 1167 /* Setting stathz to nonzero early helps avoid races. */ 1168 stathz = RTC_NOPROFRATE; 1169 profhz = RTC_PROFRATE; 1170 } 1171#endif 1172 1173 /* Finish initializing 8253 timer 0. */ 1174#if defined(APIC_IO) 1175 /* 8254 is traditionally on ISA IRQ0 */ 1176 if ((x = get_isa_apic_irq(0)) < 0) { 1177 /* 1178 * bummer, this mb doesn't have the 8254 on ISA irq0, 1179 * perhaps it's on the EISA bus... 1180 */ 1181 if ((x = get_eisa_apic_irq(0)) < 0) { 1182 /* double bummer, attempt to redirect thru the 8259 */ 1183 if (bootverbose) 1184 printf("APIC missing 8254 connection\n"); 1185 1186 /* allow 8254 timer to INTerrupt 8259 */ 1187#if !defined(IO_ICU1) 1188#ifdef PC98 1189#define IO_ICU1 0x00 1190#else 1191#define IO_ICU1 0x20 1192#endif 1193#endif 1194 x = inb(IO_ICU1 + 1); /* current mask in 8259 */ 1195 x &= ~1; /* clear 8254 timer mask */ 1196 outb(IO_ICU1 + 1, x); /* write new mask */ 1197 1198 /* program IO APIC for type 3 INT on INT0 */ 1199 if (ext_int_setup(0, 0) < 0) 1200 panic("8254 redirect impossible!"); 1201 x = 0; /* 8259 is on 0 */ 1202 } 1203 } 1204 1205 vec[x] = (u_int)vec8254; 1206 Xintr8254 = (u_int)ivectors[x]; /* XXX might need Xfastintr# */ 1207 mask8254 = (1 << x); 1208 register_intr(/* irq */ x, /* XXX id */ 0, /* flags */ 0, 1209 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1210 /* unit */ 0); 1211 INTREN(mask8254); 1212#else 1213 register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, 1214 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1215 /* unit */ 0); 1216 INTREN(IRQ0); 1217#endif /* APIC_IO */ 1218#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 1219 /* 1220 * Finish setting up anti-jitter measures. 1221 */ 1222 if (i586_ctr_freq != 0) 1223 i586_ctr_bias = rdtsc(); 1224#endif 1225 1226#ifndef PC98 1227 /* Initialize RTC. */ 1228 writertc(RTC_STATUSA, rtc_statusa); 1229 writertc(RTC_STATUSB, RTCSB_24HR); 1230 1231 /* Don't bother enabling the statistics clock. */ 1232 if (statclock_disable) 1233 return; 1234 diag = rtcin(RTC_DIAG); 1235 if (diag != 0) 1236 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1237#if defined(APIC_IO) 1238 /* RTC is traditionally on ISA IRQ8 */ 1239 if ((x = get_isa_apic_irq(8)) < 0) { 1240 if ((x = get_eisa_apic_irq(8)) < 0) { 1241 panic("APIC missing RTC connection"); 1242 } 1243 } 1244 1245 vec[x] = (u_int)vecRTC; 1246 XintrRTC = (u_int)ivectors[x]; /* XXX might need Xfastintr# */ 1247 maskRTC = (1 << x); 1248 register_intr(/* irq */ x, /* XXX id */ 1, /* flags */ 0, 1249 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1250 /* unit */ 0); 1251 INTREN(maskRTC); 1252#else 1253 register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, 1254 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1255 /* unit */ 0); 1256 INTREN(IRQ8); 1257#endif /* APIC_IO */ 1258 writertc(RTC_STATUSB, rtc_statusb); 1259#endif 1260 1261#if defined(APIC_IO) 1262 printf("Enabled INTs: "); 1263 for (x = 0; x < 24; ++x) 1264 if ((imen & (1 << x)) == 0) 1265 printf("%d, ", x); 1266 printf("imen: 0x%08x\n", imen); 1267#endif /* APIC_IO */ 1268} 1269 1270void 1271setstatclockrate(int newhz) 1272{ 1273#ifndef PC98 1274 if (newhz == RTC_PROFRATE) 1275 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1276 else 1277 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1278 writertc(RTC_STATUSA, rtc_statusa); 1279#endif 1280} 1281 1282static int 1283sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1284{ 1285 int error; 1286 u_int freq; 1287 1288 /* 1289 * Use `i8254' instead of `timer' in external names because `timer' 1290 * is is too generic. Should use it everywhere. 1291 */ 1292 freq = timer_freq; 1293 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1294 if (error == 0 && req->newptr != NULL) { 1295 if (timer0_state != 0) 1296 return (EBUSY); /* too much trouble to handle */ 1297 set_timer_freq(freq, hz); 1298#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 1299 set_i586_ctr_freq(i586_ctr_freq, timer_freq); 1300#endif 1301 } 1302 return (error); 1303} 1304 1305SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1306 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1307 1308#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 1309static void 1310set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq) 1311{ 1312 u_int comultiplier, multiplier; 1313 u_long ef; 1314 1315 if (i586_freq == 0) { 1316 i586_ctr_freq = i586_freq; 1317 return; 1318 } 1319 comultiplier = ((unsigned long long)i586_freq 1320 << I586_CTR_COMULTIPLIER_SHIFT) / i8254_freq; 1321 multiplier = (1000000LL << I586_CTR_MULTIPLIER_SHIFT) / i586_freq; 1322 ef = read_eflags(); 1323 disable_intr(); 1324 i586_ctr_freq = i586_freq; 1325 i586_ctr_comultiplier = comultiplier; 1326 i586_ctr_multiplier = multiplier; 1327 write_eflags(ef); 1328} 1329 1330static int 1331sysctl_machdep_i586_freq SYSCTL_HANDLER_ARGS 1332{ 1333 int error; 1334 u_int freq; 1335 1336 if (cpu_class != CPUCLASS_586 && cpu_class != CPUCLASS_686) 1337 return (EOPNOTSUPP); 1338 freq = i586_ctr_freq; 1339 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1340 if (error == 0 && req->newptr != NULL) 1341 set_i586_ctr_freq(freq, timer_freq); 1342 return (error); 1343} 1344 1345SYSCTL_PROC(_machdep, OID_AUTO, i586_freq, CTLTYPE_INT | CTLFLAG_RW, 1346 0, sizeof(u_int), sysctl_machdep_i586_freq, "I", ""); 1347#endif /* (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) */ 1348