pcrtc.c revision 26278
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $Id: clock.c,v 1.22 1997/05/28 09:04:26 kato Exp $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51/* 52 * modified for PC98 by Kakefuda 53 */ 54 55#include "opt_clock.h" 56#include "opt_cpu.h" 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/time.h> 61#include <sys/kernel.h> 62#include <sys/sysctl.h> 63 64#include <machine/clock.h> 65#ifdef CLK_CALIBRATION_LOOP 66#include <machine/cons.h> 67#endif 68#include <machine/cpu.h> 69#include <machine/frame.h> 70 71#include <i386/isa/icu.h> 72#ifdef PC98 73#include <pc98/pc98/pc98.h> 74#include <pc98/pc98/pc98_machdep.h> 75#include <i386/isa/isa_device.h> 76#else 77#include <i386/isa/isa.h> 78#include <i386/isa/isa_device.h> 79#include <i386/isa/rtc.h> 80#endif 81#include <i386/isa/timerreg.h> 82 83/* 84 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 85 * can use a simple formula for leap years. 86 */ 87#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 88#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 89 90#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 91 92/* 93 * Time in timer cycles that it takes for microtime() to disable interrupts 94 * and latch the count. microtime() currently uses "cli; outb ..." so it 95 * normally takes less than 2 timer cycles. Add a few for cache misses. 96 * Add a few more to allow for latency in bogus calls to microtime() with 97 * interrupts already disabled. 98 */ 99#define TIMER0_LATCH_COUNT 20 100 101/* 102 * Maximum frequency that we are willing to allow for timer0. Must be 103 * low enough to guarantee that the timer interrupt handler returns 104 * before the next timer interrupt. Must result in a lower TIMER_DIV 105 * value than TIMER0_LATCH_COUNT so that we don't have to worry about 106 * underflow in the calculation of timer0_overflow_threshold. 107 */ 108#define TIMER0_MAX_FREQ 20000 109 110int adjkerntz; /* local offset from GMT in seconds */ 111int disable_rtc_set; /* disable resettodr() if != 0 */ 112u_int idelayed; 113#if defined(I586_CPU) || defined(I686_CPU) 114#ifndef SMP 115u_int i586_ctr_bias; 116u_int i586_ctr_comultiplier; 117#endif 118u_int i586_ctr_freq; 119#ifndef SMP 120u_int i586_ctr_multiplier; 121#endif 122#endif 123int statclock_disable; 124u_int stat_imask = SWI_CLOCK_MASK; 125#ifdef TIMER_FREQ 126u_int timer_freq = TIMER_FREQ; 127#else 128#ifdef PC98 129#ifndef AUTO_CLOCK 130#ifndef PC98_8M 131u_int timer_freq = 2457600; 132#else /* !PC98_8M */ 133u_int timer_freq = 1996800; 134#endif /* PC98_8M */ 135#else /* AUTO_CLOCK */ 136u_int timer_freq = 2457600; 137#endif /* AUTO_CLOCK */ 138#else /* IBM-PC */ 139u_int timer_freq = 1193182; 140#endif /* PC98 */ 141#endif 142int timer0_max_count; 143u_int timer0_overflow_threshold; 144u_int timer0_prescaler_count; 145int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 146 147static int beeping = 0; 148static u_int clk_imask = HWI_MASK | SWI_MASK; 149static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 150static u_int hardclock_max_count; 151/* 152 * XXX new_function and timer_func should not handle clockframes, but 153 * timer_func currently needs to hold hardclock to handle the 154 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 155 * to switch between clkintr() and a slightly different timerintr(). 156 */ 157static void (*new_function) __P((struct clockframe *frame)); 158static u_int new_rate; 159#ifndef PC98 160static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 161static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 162#endif 163 164/* Values for timerX_state: */ 165#define RELEASED 0 166#define RELEASE_PENDING 1 167#define ACQUIRED 2 168#define ACQUIRE_PENDING 3 169 170static u_char timer0_state; 171#ifdef PC98 172static u_char timer1_state; 173#endif 174static u_char timer2_state; 175static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 176#ifdef PC98 177static void rtc_serialcombit __P((int)); 178static void rtc_serialcom __P((int)); 179static int rtc_inb __P((void)); 180static void rtc_outb __P((int)); 181#endif 182 183#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 184static void set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq); 185#endif 186static void set_timer_freq(u_int freq, int intr_freq); 187 188static void 189clkintr(struct clockframe frame) 190{ 191 timer_func(&frame); 192 switch (timer0_state) { 193 194 case RELEASED: 195 setdelayed(); 196 break; 197 198 case ACQUIRED: 199 if ((timer0_prescaler_count += timer0_max_count) 200 >= hardclock_max_count) { 201 hardclock(&frame); 202 setdelayed(); 203 timer0_prescaler_count -= hardclock_max_count; 204 } 205 break; 206 207 case ACQUIRE_PENDING: 208 setdelayed(); 209 timer0_max_count = TIMER_DIV(new_rate); 210 timer0_overflow_threshold = 211 timer0_max_count - TIMER0_LATCH_COUNT; 212 disable_intr(); 213 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 214 outb(TIMER_CNTR0, timer0_max_count & 0xff); 215 outb(TIMER_CNTR0, timer0_max_count >> 8); 216 enable_intr(); 217 timer0_prescaler_count = 0; 218 timer_func = new_function; 219 timer0_state = ACQUIRED; 220 break; 221 222 case RELEASE_PENDING: 223 if ((timer0_prescaler_count += timer0_max_count) 224 >= hardclock_max_count) { 225 hardclock(&frame); 226 setdelayed(); 227 timer0_max_count = hardclock_max_count; 228 timer0_overflow_threshold = 229 timer0_max_count - TIMER0_LATCH_COUNT; 230 disable_intr(); 231 outb(TIMER_MODE, 232 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 233 outb(TIMER_CNTR0, timer0_max_count & 0xff); 234 outb(TIMER_CNTR0, timer0_max_count >> 8); 235 enable_intr(); 236 /* 237 * See microtime.s for this magic. 238 */ 239#ifdef PC98 240#ifndef AUTO_CLOCK 241#ifndef PC98_8M 242 time.tv_usec += (6667 * 243 (timer0_prescaler_count - hardclock_max_count)) 244 >> 14; 245#else /* PC98_8M */ 246 time.tv_usec += (16411 * 247 (timer0_prescaler_count - hardclock_max_count)) 248 >> 15; 249#endif /* PC98_8M */ 250#else /* AUTO_CLOCK */ 251 if (pc98_machine_type & M_8M) { 252 /* PC98_8M */ 253 time.tv_usec += (16411 * 254 (timer0_prescaler_count - 255 hardclock_max_count)) >> 15; 256 } else { 257 time.tv_usec += (6667 * 258 (timer0_prescaler_count - 259 hardclock_max_count)) >> 14; 260 } 261#endif /* AUTO_CLOCK */ 262#else /* IBM-PC */ 263 time.tv_usec += (27465 * 264 (timer0_prescaler_count - hardclock_max_count)) 265 >> 15; 266#endif /* PC98 */ 267 if (time.tv_usec >= 1000000) 268 time.tv_usec -= 1000000; 269 timer0_prescaler_count = 0; 270 timer_func = hardclock; 271 timer0_state = RELEASED; 272 } 273 break; 274 } 275} 276 277/* 278 * The acquire and release functions must be called at ipl >= splclock(). 279 */ 280int 281acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 282{ 283 static int old_rate; 284 285 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 286 return (-1); 287 switch (timer0_state) { 288 289 case RELEASED: 290 timer0_state = ACQUIRE_PENDING; 291 break; 292 293 case RELEASE_PENDING: 294 if (rate != old_rate) 295 return (-1); 296 /* 297 * The timer has been released recently, but is being 298 * re-acquired before the release completed. In this 299 * case, we simply reclaim it as if it had not been 300 * released at all. 301 */ 302 timer0_state = ACQUIRED; 303 break; 304 305 default: 306 return (-1); /* busy */ 307 } 308 new_function = function; 309 old_rate = new_rate = rate; 310 return (0); 311} 312 313#ifdef PC98 314int 315acquire_timer1(int mode) 316{ 317 318 if (timer1_state != RELEASED) 319 return (-1); 320 timer1_state = ACQUIRED; 321 322 /* 323 * This access to the timer registers is as atomic as possible 324 * because it is a single instruction. We could do better if we 325 * knew the rate. Use of splclock() limits glitches to 10-100us, 326 * and this is probably good enough for timer2, so we aren't as 327 * careful with it as with timer0. 328 */ 329 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 330 331 return (0); 332} 333#endif 334 335int 336acquire_timer2(int mode) 337{ 338 339 if (timer2_state != RELEASED) 340 return (-1); 341 timer2_state = ACQUIRED; 342 343 /* 344 * This access to the timer registers is as atomic as possible 345 * because it is a single instruction. We could do better if we 346 * knew the rate. Use of splclock() limits glitches to 10-100us, 347 * and this is probably good enough for timer2, so we aren't as 348 * careful with it as with timer0. 349 */ 350 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 351 352 return (0); 353} 354 355int 356release_timer0() 357{ 358 switch (timer0_state) { 359 360 case ACQUIRED: 361 timer0_state = RELEASE_PENDING; 362 break; 363 364 case ACQUIRE_PENDING: 365 /* Nothing happened yet, release quickly. */ 366 timer0_state = RELEASED; 367 break; 368 369 default: 370 return (-1); 371 } 372 return (0); 373} 374 375#ifdef PC98 376int 377release_timer1() 378{ 379 380 if (timer1_state != ACQUIRED) 381 return (-1); 382 timer1_state = RELEASED; 383 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 384 return (0); 385} 386#endif 387 388int 389release_timer2() 390{ 391 392 if (timer2_state != ACQUIRED) 393 return (-1); 394 timer2_state = RELEASED; 395 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 396 return (0); 397} 398 399#ifndef PC98 400/* 401 * This routine receives statistical clock interrupts from the RTC. 402 * As explained above, these occur at 128 interrupts per second. 403 * When profiling, we receive interrupts at a rate of 1024 Hz. 404 * 405 * This does not actually add as much overhead as it sounds, because 406 * when the statistical clock is active, the hardclock driver no longer 407 * needs to keep (inaccurate) statistics on its own. This decouples 408 * statistics gathering from scheduling interrupts. 409 * 410 * The RTC chip requires that we read status register C (RTC_INTR) 411 * to acknowledge an interrupt, before it will generate the next one. 412 * Under high interrupt load, rtcintr() can be indefinitely delayed and 413 * the clock can tick immediately after the read from RTC_INTR. In this 414 * case, the mc146818A interrupt signal will not drop for long enough 415 * to register with the 8259 PIC. If an interrupt is missed, the stat 416 * clock will halt, considerably degrading system performance. This is 417 * why we use 'while' rather than a more straightforward 'if' below. 418 * Stat clock ticks can still be lost, causing minor loss of accuracy 419 * in the statistics, but the stat clock will no longer stop. 420 */ 421static void 422rtcintr(struct clockframe frame) 423{ 424 while (rtcin(RTC_INTR) & RTCIR_PERIOD) 425 statclock(&frame); 426} 427 428#include "opt_ddb.h" 429#ifdef DDB 430#include <ddb/ddb.h> 431 432DB_SHOW_COMMAND(rtc, rtc) 433{ 434 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 435 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 436 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 437 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 438} 439#endif /* DDB */ 440#endif /* for PC98 */ 441 442static int 443getit(void) 444{ 445 u_long ef; 446 int high, low; 447 448 ef = read_eflags(); 449 disable_intr(); 450 451 /* Select timer0 and latch counter value. */ 452 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 453 454 low = inb(TIMER_CNTR0); 455 high = inb(TIMER_CNTR0); 456 457 write_eflags(ef); 458 return ((high << 8) | low); 459} 460 461/* 462 * Wait "n" microseconds. 463 * Relies on timer 1 counting down from (timer_freq / hz) 464 * Note: timer had better have been programmed before this is first used! 465 */ 466void 467DELAY(int n) 468{ 469 int delta, prev_tick, tick, ticks_left; 470 471#ifdef DELAYDEBUG 472 int getit_calls = 1; 473 int n1; 474 static int state = 0; 475 476 if (state == 0) { 477 state = 1; 478 for (n1 = 1; n1 <= 10000000; n1 *= 10) 479 DELAY(n1); 480 state = 2; 481 } 482 if (state == 1) 483 printf("DELAY(%d)...", n); 484#endif 485 /* 486 * Guard against the timer being uninitialized if we are called 487 * early for console i/o. 488 */ 489 if (timer0_max_count == 0) 490 set_timer_freq(timer_freq, hz); 491 492 /* 493 * Read the counter first, so that the rest of the setup overhead is 494 * counted. Guess the initial overhead is 20 usec (on most systems it 495 * takes about 1.5 usec for each of the i/o's in getit(). The loop 496 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 497 * multiplications and divisions to scale the count take a while). 498 */ 499 prev_tick = getit(); 500 n -= 0; /* XXX actually guess no initial overhead */ 501 /* 502 * Calculate (n * (timer_freq / 1e6)) without using floating point 503 * and without any avoidable overflows. 504 */ 505 if (n <= 0) 506 ticks_left = 0; 507 else if (n < 256) 508 /* 509 * Use fixed point to avoid a slow division by 1000000. 510 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 511 * 2^15 is the first power of 2 that gives exact results 512 * for n between 0 and 256. 513 */ 514 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 515 else 516 /* 517 * Don't bother using fixed point, although gcc-2.7.2 518 * generates particularly poor code for the long long 519 * division, since even the slow way will complete long 520 * before the delay is up (unless we're interrupted). 521 */ 522 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 523 / 1000000; 524 525 while (ticks_left > 0) { 526 tick = getit(); 527#ifdef DELAYDEBUG 528 ++getit_calls; 529#endif 530 delta = prev_tick - tick; 531 prev_tick = tick; 532 if (delta < 0) { 533 delta += timer0_max_count; 534 /* 535 * Guard against timer0_max_count being wrong. 536 * This shouldn't happen in normal operation, 537 * but it may happen if set_timer_freq() is 538 * traced. 539 */ 540 if (delta < 0) 541 delta = 0; 542 } 543 ticks_left -= delta; 544 } 545#ifdef DELAYDEBUG 546 if (state == 1) 547 printf(" %d calls to getit() at %d usec each\n", 548 getit_calls, (n + 5) / getit_calls); 549#endif 550} 551 552static void 553sysbeepstop(void *chan) 554{ 555#ifdef PC98 /* PC98 */ 556 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 557 release_timer1(); 558#else 559 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 560 release_timer2(); 561#endif 562 beeping = 0; 563} 564 565int 566sysbeep(int pitch, int period) 567{ 568 int x = splclock(); 569 570#ifdef PC98 571 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 572 if (!beeping) { 573 /* Something else owns it. */ 574 splx(x); 575 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 576 } 577 disable_intr(); 578 outb(0x3fdb, pitch); 579 outb(0x3fdb, (pitch>>8)); 580 enable_intr(); 581 if (!beeping) { 582 /* enable counter1 output to speaker */ 583 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 584 beeping = period; 585 timeout(sysbeepstop, (void *)NULL, period); 586 } 587#else 588 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 589 if (!beeping) { 590 /* Something else owns it. */ 591 splx(x); 592 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 593 } 594 disable_intr(); 595 outb(TIMER_CNTR2, pitch); 596 outb(TIMER_CNTR2, (pitch>>8)); 597 enable_intr(); 598 if (!beeping) { 599 /* enable counter2 output to speaker */ 600 outb(IO_PPI, inb(IO_PPI) | 3); 601 beeping = period; 602 timeout(sysbeepstop, (void *)NULL, period); 603 } 604#endif 605 splx(x); 606 return (0); 607} 608 609#ifndef PC98 610/* 611 * RTC support routines 612 */ 613 614int 615rtcin(reg) 616 int reg; 617{ 618 u_char val; 619 620 outb(IO_RTC, reg); 621 inb(0x84); 622 val = inb(IO_RTC + 1); 623 inb(0x84); 624 return (val); 625} 626 627static __inline void 628writertc(u_char reg, u_char val) 629{ 630 outb(IO_RTC, reg); 631 outb(IO_RTC + 1, val); 632} 633 634static __inline int 635readrtc(int port) 636{ 637 return(bcd2bin(rtcin(port))); 638} 639#endif 640 641#ifdef PC98 642unsigned int delaycount; 643#define FIRST_GUESS 0x2000 644static void findcpuspeed(void) 645{ 646 int i; 647 int remainder; 648 649 /* Put counter in count down mode */ 650 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 651 outb(TIMER_CNTR0, 0xff); 652 outb(TIMER_CNTR0, 0xff); 653 for (i = FIRST_GUESS; i; i--) 654 ; 655 remainder = getit(); 656 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 657} 658#endif 659 660#ifndef PC98 661static u_int 662calibrate_clocks(void) 663{ 664 u_int count, prev_count, tot_count; 665 int sec, start_sec, timeout; 666 667 if (bootverbose) 668 printf("Calibrating clock(s) ... "); 669 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 670 goto fail; 671 timeout = 100000000; 672 673 /* Read the mc146818A seconds counter. */ 674 for (;;) { 675 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 676 sec = rtcin(RTC_SEC); 677 break; 678 } 679 if (--timeout == 0) 680 goto fail; 681 } 682 683 /* Wait for the mC146818A seconds counter to change. */ 684 start_sec = sec; 685 for (;;) { 686 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 687 sec = rtcin(RTC_SEC); 688 if (sec != start_sec) 689 break; 690 } 691 if (--timeout == 0) 692 goto fail; 693 } 694 695 /* Start keeping track of the i8254 counter. */ 696 prev_count = getit(); 697 if (prev_count == 0 || prev_count > timer0_max_count) 698 goto fail; 699 tot_count = 0; 700 701#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 702 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) 703 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 704#endif 705 706 /* 707 * Wait for the mc146818A seconds counter to change. Read the i8254 708 * counter for each iteration since this is convenient and only 709 * costs a few usec of inaccuracy. The timing of the final reads 710 * of the counters almost matches the timing of the initial reads, 711 * so the main cause of inaccuracy is the varying latency from 712 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 713 * rtcin(RTC_SEC) that returns a changed seconds count. The 714 * maximum inaccuracy from this cause is < 10 usec on 486's. 715 */ 716 start_sec = sec; 717 for (;;) { 718 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 719 sec = rtcin(RTC_SEC); 720 count = getit(); 721 if (count == 0 || count > timer0_max_count) 722 goto fail; 723 if (count > prev_count) 724 tot_count += prev_count - (count - timer0_max_count); 725 else 726 tot_count += prev_count - count; 727 prev_count = count; 728 if (sec != start_sec) 729 break; 730 if (--timeout == 0) 731 goto fail; 732 } 733 734#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 735 /* 736 * Read the cpu cycle counter. The timing considerations are 737 * similar to those for the i8254 clock. 738 */ 739 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) { 740 set_i586_ctr_freq((u_int)rdtsc(), tot_count); 741 if (bootverbose) 742 printf("i586 clock: %u Hz, ", i586_ctr_freq); 743 } 744#endif 745 746 if (bootverbose) 747 printf("i8254 clock: %u Hz\n", tot_count); 748 return (tot_count); 749 750fail: 751 if (bootverbose) 752 printf("failed, using default i8254 clock of %u Hz\n", 753 timer_freq); 754 return (timer_freq); 755} 756#endif /* !PC98 */ 757 758static void 759set_timer_freq(u_int freq, int intr_freq) 760{ 761 u_long ef; 762 763 ef = read_eflags(); 764 disable_intr(); 765 timer_freq = freq; 766 timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 767 timer0_overflow_threshold = timer0_max_count - TIMER0_LATCH_COUNT; 768 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 769 outb(TIMER_CNTR0, timer0_max_count & 0xff); 770 outb(TIMER_CNTR0, timer0_max_count >> 8); 771 write_eflags(ef); 772} 773 774/* 775 * Initialize 8253 timer 0 early so that it can be used in DELAY(). 776 * XXX initialization of other timers is unintentionally left blank. 777 */ 778void 779startrtclock() 780{ 781 u_int delta, freq; 782 783#ifdef PC98 784 findcpuspeed(); 785#ifndef AUTO_CLOCK 786 if (pc98_machine_type & M_8M) { 787#ifndef PC98_8M 788 printf("you must reconfig a kernel with \"PC98_8M\" option.\n"); 789#endif 790 } else { 791#ifdef PC98_8M 792 printf("You must reconfig a kernel without \"PC98_8M\" option.\n"); 793#endif 794 } 795#else /* AUTO_CLOCK */ 796 if (pc98_machine_type & M_8M) 797 timer_freq = 1996800L; /* 1.9968 MHz */ 798 else 799 timer_freq = 2457600L; /* 2.4576 MHz */ 800#endif /* AUTO_CLOCK */ 801#endif /* PC98 */ 802 803#ifndef PC98 804 writertc(RTC_STATUSA, rtc_statusa); 805 writertc(RTC_STATUSB, RTCSB_24HR); 806#endif 807 808#ifndef PC98 809 set_timer_freq(timer_freq, hz); 810 freq = calibrate_clocks(); 811#ifdef CLK_CALIBRATION_LOOP 812 if (bootverbose) { 813 printf( 814 "Press a key on the console to abort clock calibration\n"); 815 while (cncheckc() == -1) 816 calibrate_clocks(); 817 } 818#endif 819 820 /* 821 * Use the calibrated i8254 frequency if it seems reasonable. 822 * Otherwise use the default, and don't use the calibrated i586 823 * frequency. 824 */ 825 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 826 if (delta < timer_freq / 100) { 827#ifndef CLK_USE_I8254_CALIBRATION 828 if (bootverbose) 829 printf( 830"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 831 freq = timer_freq; 832#endif 833 timer_freq = freq; 834 } else { 835 if (bootverbose) 836 printf( 837 "%d Hz differs from default of %d Hz by more than 1%%\n", 838 freq, timer_freq); 839#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 840 i586_ctr_freq = 0; 841#endif 842 } 843#endif 844 845 set_timer_freq(timer_freq, hz); 846 847#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 848#ifndef CLK_USE_I586_CALIBRATION 849 if (i586_ctr_freq != 0) { 850 if (bootverbose) 851 printf( 852"CLK_USE_I586_CALIBRATION not specified - using old calibration method\n"); 853 i586_ctr_freq = 0; 854 } 855#endif 856 if (i586_ctr_freq == 0 && 857 (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686)) { 858 /* 859 * Calibration of the i586 clock relative to the mc146818A 860 * clock failed. Do a less accurate calibration relative 861 * to the i8254 clock. 862 */ 863 wrmsr(0x10, 0LL); /* XXX */ 864 DELAY(1000000); 865 set_i586_ctr_freq((u_int)rdtsc(), timer_freq); 866#ifdef CLK_USE_I586_CALIBRATION 867 if (bootverbose) 868 printf("i586 clock: %u Hz\n", i586_ctr_freq); 869#endif 870 } 871#endif 872} 873 874#ifdef PC98 875static void 876rtc_serialcombit(int i) 877{ 878 outb(IO_RTC, ((i&0x01)<<5)|0x07); 879 DELAY(1); 880 outb(IO_RTC, ((i&0x01)<<5)|0x17); 881 DELAY(1); 882 outb(IO_RTC, ((i&0x01)<<5)|0x07); 883 DELAY(1); 884} 885 886static void 887rtc_serialcom(int i) 888{ 889 rtc_serialcombit(i&0x01); 890 rtc_serialcombit((i&0x02)>>1); 891 rtc_serialcombit((i&0x04)>>2); 892 rtc_serialcombit((i&0x08)>>3); 893 outb(IO_RTC, 0x07); 894 DELAY(1); 895 outb(IO_RTC, 0x0f); 896 DELAY(1); 897 outb(IO_RTC, 0x07); 898 DELAY(1); 899} 900 901static void 902rtc_outb(int val) 903{ 904 int s; 905 int sa = 0; 906 907 for (s=0;s<8;s++) { 908 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 909 outb(IO_RTC, sa); /* set DI & CLK 0 */ 910 DELAY(1); 911 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 912 DELAY(1); 913 } 914 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 915} 916 917static int 918rtc_inb(void) 919{ 920 int s; 921 int sa = 0; 922 923 for (s=0;s<8;s++) { 924 sa |= ((inb(0x33) & 0x01) << s); 925 outb(IO_RTC, 0x17); /* CLK 1 */ 926 DELAY(1); 927 outb(IO_RTC, 0x07); /* CLK 0 */ 928 DELAY(2); 929 } 930 return sa; 931} 932#endif /* PC-98 */ 933 934/* 935 * Initialize the time of day register, based on the time base which is, e.g. 936 * from a filesystem. 937 */ 938void 939inittodr(time_t base) 940{ 941 unsigned long sec, days; 942 int yd; 943 int year, month; 944 int y, m, s; 945#ifdef PC98 946 int second, min, hour; 947#endif 948 949 s = splclock(); 950 time.tv_sec = base; 951 time.tv_usec = 0; 952 splx(s); 953 954#ifdef PC98 955 rtc_serialcom(0x03); /* Time Read */ 956 rtc_serialcom(0x01); /* Register shift command. */ 957 DELAY(20); 958 959 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 960 min = bcd2bin(rtc_inb() & 0xff); /* min */ 961 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 962 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 963 964 month = (rtc_inb() >> 4) & 0x0f; /* month */ 965 for (m = 1; m < month; m++) 966 days += daysinmonth[m-1]; 967 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 968 /* 2000 year problem */ 969 if (year < 1995) 970 year += 100; 971 if (year < 1970) 972 goto wrong_time; 973 for (y = 1970; y < year; y++) 974 days += DAYSPERYEAR + LEAPYEAR(y); 975 if ((month > 2) && LEAPYEAR(year)) 976 days ++; 977 sec = ((( days * 24 + 978 hour) * 60 + 979 min) * 60 + 980 second); 981 /* sec now contains the number of seconds, since Jan 1 1970, 982 in the local time zone */ 983#else /* IBM-PC */ 984 /* Look if we have a RTC present and the time is valid */ 985 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 986 goto wrong_time; 987 988 /* wait for time update to complete */ 989 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 990 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 991 992 days = 0; 993#ifdef USE_RTC_CENTURY 994 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 995#else 996 year = readrtc(RTC_YEAR) + 1900; 997 if (year < 1970) 998 year += 100; 999#endif 1000 if (year < 1970) 1001 goto wrong_time; 1002 month = readrtc(RTC_MONTH); 1003 for (m = 1; m < month; m++) 1004 days += daysinmonth[m-1]; 1005 if ((month > 2) && LEAPYEAR(year)) 1006 days ++; 1007 days += readrtc(RTC_DAY) - 1; 1008 yd = days; 1009 for (y = 1970; y < year; y++) 1010 days += DAYSPERYEAR + LEAPYEAR(y); 1011 sec = ((( days * 24 + 1012 readrtc(RTC_HRS)) * 60 + 1013 readrtc(RTC_MIN)) * 60 + 1014 readrtc(RTC_SEC)); 1015 /* sec now contains the number of seconds, since Jan 1 1970, 1016 in the local time zone */ 1017#endif 1018 1019 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1020 1021 s = splclock(); 1022 time.tv_sec = sec; 1023 splx(s); 1024 return; 1025 1026wrong_time: 1027 printf("Invalid time in real time clock.\n"); 1028 printf("Check and reset the date immediately!\n"); 1029} 1030 1031/* 1032 * Write system time back to RTC 1033 */ 1034void 1035resettodr() 1036{ 1037 unsigned long tm; 1038 int y, m, s; 1039#ifdef PC98 1040 int wd; 1041#endif 1042 1043 if (disable_rtc_set) 1044 return; 1045 1046 s = splclock(); 1047 tm = time.tv_sec; 1048 splx(s); 1049 1050#ifdef PC98 1051 rtc_serialcom(0x01); /* Register shift command. */ 1052 1053 /* Calculate local time to put in RTC */ 1054 1055 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1056 1057 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1058 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1059 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1060 1061 /* We have now the days since 01-01-1970 in tm */ 1062 wd = (tm+4)%7; 1063 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1064 tm >= m; 1065 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1066 tm -= m; 1067 1068 /* Now we have the years in y and the day-of-the-year in tm */ 1069 for (m = 0; ; m++) { 1070 int ml; 1071 1072 ml = daysinmonth[m]; 1073 if (m == 1 && LEAPYEAR(y)) 1074 ml++; 1075 if (tm < ml) 1076 break; 1077 tm -= ml; 1078 } 1079 1080 m++; 1081 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1082 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1083 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1084 1085 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1086 rtc_serialcom(0x00); /* Register hold command. */ 1087#else 1088 /* Disable RTC updates and interrupts. */ 1089 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1090 1091 /* Calculate local time to put in RTC */ 1092 1093 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1094 1095 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1096 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1097 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1098 1099 /* We have now the days since 01-01-1970 in tm */ 1100 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1101 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1102 tm >= m; 1103 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1104 tm -= m; 1105 1106 /* Now we have the years in y and the day-of-the-year in tm */ 1107 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1108#ifdef USE_RTC_CENTURY 1109 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1110#endif 1111 for (m = 0; ; m++) { 1112 int ml; 1113 1114 ml = daysinmonth[m]; 1115 if (m == 1 && LEAPYEAR(y)) 1116 ml++; 1117 if (tm < ml) 1118 break; 1119 tm -= ml; 1120 } 1121 1122 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1123 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1124 1125 /* Reenable RTC updates and interrupts. */ 1126 writertc(RTC_STATUSB, rtc_statusb); 1127#endif 1128} 1129 1130#if defined(APIC_IO) 1131 1132/* from icu.s: */ 1133extern u_int vec[]; 1134extern void vec8254 __P((void)); 1135extern void vecRTC __P((void)); 1136extern u_int ivectors[]; 1137extern u_int Xintr8254; 1138extern u_int XintrRTC; 1139extern u_int mask8254; 1140extern u_int maskRTC; 1141 1142#endif /* APIC_IO */ 1143 1144/* 1145 * Start both clocks running. 1146 */ 1147void 1148cpu_initclocks() 1149{ 1150#if defined(APIC_IO) 1151 int x; 1152#endif /* APIC_IO */ 1153#ifndef PC98 1154 int diag; 1155 1156 if (statclock_disable) { 1157 /* 1158 * The stat interrupt mask is different without the 1159 * statistics clock. Also, don't set the interrupt 1160 * flag which would normally cause the RTC to generate 1161 * interrupts. 1162 */ 1163 stat_imask = HWI_MASK | SWI_MASK; 1164 rtc_statusb = RTCSB_24HR; 1165 } else { 1166 /* Setting stathz to nonzero early helps avoid races. */ 1167 stathz = RTC_NOPROFRATE; 1168 profhz = RTC_PROFRATE; 1169 } 1170#endif 1171 1172 /* Finish initializing 8253 timer 0. */ 1173#if defined(APIC_IO) 1174 /* 8254 is traditionally on ISA IRQ0 */ 1175 if ((x = get_isa_apic_irq(0)) < 0) { 1176 /* 1177 * bummer, this mb doesn't have the 8254 on ISA irq0, 1178 * perhaps it's on the EISA bus... 1179 */ 1180 if ((x = get_eisa_apic_irq(0)) < 0) { 1181 /* double bummer, attempt to redirect thru the 8259 */ 1182 if (bootverbose) 1183 printf("APIC missing 8254 connection\n"); 1184 1185 /* allow 8254 timer to INTerrupt 8259 */ 1186#if !defined(IO_ICU1) 1187#ifdef PC98 1188#define IO_ICU1 0x00 1189#else 1190#define IO_ICU1 0x20 1191#endif 1192#endif 1193 x = inb(IO_ICU1 + 1); /* current mask in 8259 */ 1194 x &= ~1; /* clear 8254 timer mask */ 1195 outb(IO_ICU1 + 1, x); /* write new mask */ 1196 1197 /* program IO APIC for type 3 INT on INT0 */ 1198 if (ext_int_setup(0, 0) < 0) 1199 panic("8254 redirect impossible!"); 1200 x = 0; /* 8259 is on 0 */ 1201 } 1202 } 1203 1204 vec[x] = (u_int)vec8254; 1205 Xintr8254 = (u_int)ivectors[x]; /* XXX might need Xfastintr# */ 1206 mask8254 = (1 << x); 1207 register_intr(/* irq */ x, /* XXX id */ 0, /* flags */ 0, 1208 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1209 /* unit */ 0); 1210 INTREN(mask8254); 1211#else 1212 register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, 1213 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1214 /* unit */ 0); 1215 INTREN(IRQ0); 1216#endif /* APIC_IO */ 1217#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 1218 /* 1219 * Finish setting up anti-jitter measures. 1220 */ 1221 if (i586_ctr_freq != 0) 1222 i586_ctr_bias = rdtsc(); 1223#endif 1224 1225#ifndef PC98 1226 /* Initialize RTC. */ 1227 writertc(RTC_STATUSA, rtc_statusa); 1228 writertc(RTC_STATUSB, RTCSB_24HR); 1229 1230 /* Don't bother enabling the statistics clock. */ 1231 if (statclock_disable) 1232 return; 1233 diag = rtcin(RTC_DIAG); 1234 if (diag != 0) 1235 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1236#if defined(APIC_IO) 1237 /* RTC is traditionally on ISA IRQ8 */ 1238 if ((x = get_isa_apic_irq(8)) < 0) { 1239 if ((x = get_eisa_apic_irq(8)) < 0) { 1240 panic("APIC missing RTC connection"); 1241 } 1242 } 1243 1244 vec[x] = (u_int)vecRTC; 1245 XintrRTC = (u_int)ivectors[x]; /* XXX might need Xfastintr# */ 1246 maskRTC = (1 << x); 1247 register_intr(/* irq */ x, /* XXX id */ 1, /* flags */ 0, 1248 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1249 /* unit */ 0); 1250 INTREN(maskRTC); 1251#else 1252 register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, 1253 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1254 /* unit */ 0); 1255 INTREN(IRQ8); 1256#endif /* APIC_IO */ 1257 writertc(RTC_STATUSB, rtc_statusb); 1258#endif 1259 1260#if defined(APIC_IO) 1261 printf("Enabled INTs: "); 1262 for (x = 0; x < 24; ++x) 1263 if ((imen & (1 << x)) == 0) 1264 printf("%d, ", x); 1265 printf("imen: 0x%08x\n", imen); 1266#endif /* APIC_IO */ 1267} 1268 1269void 1270setstatclockrate(int newhz) 1271{ 1272#ifndef PC98 1273 if (newhz == RTC_PROFRATE) 1274 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1275 else 1276 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1277 writertc(RTC_STATUSA, rtc_statusa); 1278#endif 1279} 1280 1281static int 1282sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1283{ 1284 int error; 1285 u_int freq; 1286 1287 /* 1288 * Use `i8254' instead of `timer' in external names because `timer' 1289 * is is too generic. Should use it everywhere. 1290 */ 1291 freq = timer_freq; 1292 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1293 if (error == 0 && req->newptr != NULL) { 1294 if (timer0_state != 0) 1295 return (EBUSY); /* too much trouble to handle */ 1296 set_timer_freq(freq, hz); 1297#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 1298 set_i586_ctr_freq(i586_ctr_freq, timer_freq); 1299#endif 1300 } 1301 return (error); 1302} 1303 1304SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1305 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1306 1307#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) 1308static void 1309set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq) 1310{ 1311 u_int comultiplier, multiplier; 1312 u_long ef; 1313 1314 if (i586_freq == 0) { 1315 i586_ctr_freq = i586_freq; 1316 return; 1317 } 1318 comultiplier = ((unsigned long long)i586_freq 1319 << I586_CTR_COMULTIPLIER_SHIFT) / i8254_freq; 1320 multiplier = (1000000LL << I586_CTR_MULTIPLIER_SHIFT) / i586_freq; 1321 ef = read_eflags(); 1322 disable_intr(); 1323 i586_ctr_freq = i586_freq; 1324 i586_ctr_comultiplier = comultiplier; 1325 i586_ctr_multiplier = multiplier; 1326 write_eflags(ef); 1327} 1328 1329static int 1330sysctl_machdep_i586_freq SYSCTL_HANDLER_ARGS 1331{ 1332 int error; 1333 u_int freq; 1334 1335 if (cpu_class != CPUCLASS_586 && cpu_class != CPUCLASS_686) 1336 return (EOPNOTSUPP); 1337 freq = i586_ctr_freq; 1338 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1339 if (error == 0 && req->newptr != NULL) 1340 set_i586_ctr_freq(freq, timer_freq); 1341 return (error); 1342} 1343 1344SYSCTL_PROC(_machdep, OID_AUTO, i586_freq, CTLTYPE_INT | CTLFLAG_RW, 1345 0, sizeof(u_int), sysctl_machdep_i586_freq, "I", ""); 1346#endif /* (defined(I586_CPU) || defined(I686_CPU)) && !defined(SMP) */ 1347