pcrtc.c revision 21843
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $FreeBSD: head/sys/pc98/cbus/pcrtc.c 21843 1997-01-18 10:25:04Z kato $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51/* 52 * modified for PC98 by Kakefuda 53 */ 54 55#include "opt_clock.h" 56#include "opt_cpu.h" 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/time.h> 61#include <sys/kernel.h> 62#include <sys/sysctl.h> 63 64#include <machine/clock.h> 65#ifdef CLK_CALIBRATION_LOOP 66#include <machine/cons.h> 67#endif 68#include <machine/cpu.h> 69#include <machine/frame.h> 70 71#include <i386/isa/icu.h> 72#ifdef PC98 73#include <pc98/pc98/pc98.h> 74#include <i386/isa/isa_device.h> 75#else 76#include <i386/isa/isa.h> 77#include <i386/isa/isa_device.h> 78#include <i386/isa/rtc.h> 79#endif 80#include <i386/isa/timerreg.h> 81 82/* 83 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 84 * can use a simple formula for leap years. 85 */ 86#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 87#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 88 89#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 90 91/* 92 * Time in timer cycles that it takes for microtime() to disable interrupts 93 * and latch the count. microtime() currently uses "cli; outb ..." so it 94 * normally takes less than 2 timer cycles. Add a few for cache misses. 95 * Add a few more to allow for latency in bogus calls to microtime() with 96 * interrupts already disabled. 97 */ 98#define TIMER0_LATCH_COUNT 20 99 100/* 101 * Maximum frequency that we are willing to allow for timer0. Must be 102 * low enough to guarantee that the timer interrupt handler returns 103 * before the next timer interrupt. Must result in a lower TIMER_DIV 104 * value than TIMER0_LATCH_COUNT so that we don't have to worry about 105 * underflow in the calculation of timer0_overflow_threshold. 106 */ 107#define TIMER0_MAX_FREQ 20000 108 109int adjkerntz; /* local offset from GMT in seconds */ 110int disable_rtc_set; /* disable resettodr() if != 0 */ 111u_int idelayed; 112#if defined(I586_CPU) || defined(I686_CPU) 113u_int i586_ctr_bias; 114u_int i586_ctr_comultiplier; 115u_int i586_ctr_freq; 116u_int i586_ctr_multiplier; 117#endif 118int statclock_disable; 119u_int stat_imask = SWI_CLOCK_MASK; 120#ifdef TIMER_FREQ 121u_int timer_freq = TIMER_FREQ; 122#else 123#ifdef PC98 124#ifndef AUTO_CLOCK 125#ifndef PC98_8M 126u_int timer_freq = 2457600; 127#else /* !PC98_8M */ 128u_int timer_freq = 1996800; 129#endif /* PC98_8M */ 130#else /* AUTO_CLOCK */ 131u_int timer_freq = 2457600; 132#endif /* AUTO_CLOCK */ 133#else /* IBM-PC */ 134u_int timer_freq = 1193182; 135#endif /* PC98 */ 136#endif 137int timer0_max_count; 138u_int timer0_overflow_threshold; 139u_int timer0_prescaler_count; 140int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 141 142static int beeping = 0; 143static u_int clk_imask = HWI_MASK | SWI_MASK; 144static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 145static u_int hardclock_max_count; 146/* 147 * XXX new_function and timer_func should not handle clockframes, but 148 * timer_func currently needs to hold hardclock to handle the 149 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 150 * to switch between clkintr() and a slightly different timerintr(). 151 */ 152static void (*new_function) __P((struct clockframe *frame)); 153static u_int new_rate; 154#ifndef PC98 155static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 156static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 157#endif 158 159/* Values for timerX_state: */ 160#define RELEASED 0 161#define RELEASE_PENDING 1 162#define ACQUIRED 2 163#define ACQUIRE_PENDING 3 164 165static u_char timer0_state; 166#ifdef PC98 167static u_char timer1_state; 168#endif 169static u_char timer2_state; 170static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 171#ifdef PC98 172static void rtc_serialcombit __P((int)); 173static void rtc_serialcom __P((int)); 174static int rtc_inb __P((void)); 175static void rtc_outb __P((int)); 176#endif 177 178#if defined(I586_CPU) || defined(I686_CPU) 179static void set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq); 180#endif 181static void set_timer_freq(u_int freq, int intr_freq); 182 183static void 184clkintr(struct clockframe frame) 185{ 186 timer_func(&frame); 187 switch (timer0_state) { 188 189 case RELEASED: 190 setdelayed(); 191 break; 192 193 case ACQUIRED: 194 if ((timer0_prescaler_count += timer0_max_count) 195 >= hardclock_max_count) { 196 hardclock(&frame); 197 setdelayed(); 198 timer0_prescaler_count -= hardclock_max_count; 199 } 200 break; 201 202 case ACQUIRE_PENDING: 203 setdelayed(); 204 timer0_max_count = TIMER_DIV(new_rate); 205 timer0_overflow_threshold = 206 timer0_max_count - TIMER0_LATCH_COUNT; 207 disable_intr(); 208 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 209 outb(TIMER_CNTR0, timer0_max_count & 0xff); 210 outb(TIMER_CNTR0, timer0_max_count >> 8); 211 enable_intr(); 212 timer0_prescaler_count = 0; 213 timer_func = new_function; 214 timer0_state = ACQUIRED; 215 break; 216 217 case RELEASE_PENDING: 218 if ((timer0_prescaler_count += timer0_max_count) 219 >= hardclock_max_count) { 220 hardclock(&frame); 221 setdelayed(); 222 timer0_max_count = hardclock_max_count; 223 timer0_overflow_threshold = 224 timer0_max_count - TIMER0_LATCH_COUNT; 225 disable_intr(); 226 outb(TIMER_MODE, 227 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 228 outb(TIMER_CNTR0, timer0_max_count & 0xff); 229 outb(TIMER_CNTR0, timer0_max_count >> 8); 230 enable_intr(); 231 /* 232 * See microtime.s for this magic. 233 */ 234#ifdef PC98 235#ifndef AUTO_CLOCK 236#ifndef PC98_8M 237 time.tv_usec += (6667 * 238 (timer0_prescaler_count - hardclock_max_count)) 239 >> 14; 240#else /* PC98_8M */ 241 time.tv_usec += (16411 * 242 (timer0_prescaler_count - hardclock_max_count)) 243 >> 15; 244#endif /* PC98_8M */ 245#else /* AUTO_CLOCK */ 246 if (pc98_machine_type & M_8M) { 247 /* PC98_8M */ 248 time.tv_usec += (16411 * 249 (timer0_prescaler_count - 250 hardclock_max_count)) >> 15; 251 } else { 252 time.tv_usec += (6667 * 253 (timer0_prescaler_count - 254 hardclock_max_count)) >> 14; 255 } 256#endif /* AUTO_CLOCK */ 257#else /* IBM-PC */ 258 time.tv_usec += (27465 * 259 (timer0_prescaler_count - hardclock_max_count)) 260 >> 15; 261#endif /* PC98 */ 262 if (time.tv_usec >= 1000000) 263 time.tv_usec -= 1000000; 264 timer0_prescaler_count = 0; 265 timer_func = hardclock; 266 timer0_state = RELEASED; 267 } 268 break; 269 } 270} 271 272/* 273 * The acquire and release functions must be called at ipl >= splclock(). 274 */ 275int 276acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 277{ 278 static int old_rate; 279 280 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 281 return (-1); 282 switch (timer0_state) { 283 284 case RELEASED: 285 timer0_state = ACQUIRE_PENDING; 286 break; 287 288 case RELEASE_PENDING: 289 if (rate != old_rate) 290 return (-1); 291 /* 292 * The timer has been released recently, but is being 293 * re-acquired before the release completed. In this 294 * case, we simply reclaim it as if it had not been 295 * released at all. 296 */ 297 timer0_state = ACQUIRED; 298 break; 299 300 default: 301 return (-1); /* busy */ 302 } 303 new_function = function; 304 old_rate = new_rate = rate; 305 return (0); 306} 307 308#ifdef PC98 309int 310acquire_timer1(int mode) 311{ 312 313 if (timer1_state != RELEASED) 314 return (-1); 315 timer1_state = ACQUIRED; 316 317 /* 318 * This access to the timer registers is as atomic as possible 319 * because it is a single instruction. We could do better if we 320 * knew the rate. Use of splclock() limits glitches to 10-100us, 321 * and this is probably good enough for timer2, so we aren't as 322 * careful with it as with timer0. 323 */ 324 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 325 326 return (0); 327} 328#endif 329 330int 331acquire_timer2(int mode) 332{ 333 334 if (timer2_state != RELEASED) 335 return (-1); 336 timer2_state = ACQUIRED; 337 338 /* 339 * This access to the timer registers is as atomic as possible 340 * because it is a single instruction. We could do better if we 341 * knew the rate. Use of splclock() limits glitches to 10-100us, 342 * and this is probably good enough for timer2, so we aren't as 343 * careful with it as with timer0. 344 */ 345 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 346 347 return (0); 348} 349 350int 351release_timer0() 352{ 353 switch (timer0_state) { 354 355 case ACQUIRED: 356 timer0_state = RELEASE_PENDING; 357 break; 358 359 case ACQUIRE_PENDING: 360 /* Nothing happened yet, release quickly. */ 361 timer0_state = RELEASED; 362 break; 363 364 default: 365 return (-1); 366 } 367 return (0); 368} 369 370#ifdef PC98 371int 372release_timer1() 373{ 374 375 if (timer1_state != ACQUIRED) 376 return (-1); 377 timer1_state = RELEASED; 378 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 379 return (0); 380} 381#endif 382 383int 384release_timer2() 385{ 386 387 if (timer2_state != ACQUIRED) 388 return (-1); 389 timer2_state = RELEASED; 390 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 391 return (0); 392} 393 394#ifndef PC98 395/* 396 * This routine receives statistical clock interrupts from the RTC. 397 * As explained above, these occur at 128 interrupts per second. 398 * When profiling, we receive interrupts at a rate of 1024 Hz. 399 * 400 * This does not actually add as much overhead as it sounds, because 401 * when the statistical clock is active, the hardclock driver no longer 402 * needs to keep (inaccurate) statistics on its own. This decouples 403 * statistics gathering from scheduling interrupts. 404 * 405 * The RTC chip requires that we read status register C (RTC_INTR) 406 * to acknowledge an interrupt, before it will generate the next one. 407 */ 408static void 409rtcintr(struct clockframe frame) 410{ 411 u_char stat; 412 stat = rtcin(RTC_INTR); 413 if(stat & RTCIR_PERIOD) { 414 statclock(&frame); 415 } 416} 417 418#include "opt_ddb.h" 419#ifdef DDB 420#include <ddb/ddb.h> 421 422DB_SHOW_COMMAND(rtc, rtc) 423{ 424 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 425 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 426 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 427 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 428} 429#endif /* DDB */ 430#endif /* for PC98 */ 431 432static int 433getit(void) 434{ 435 u_long ef; 436 int high, low; 437 438 ef = read_eflags(); 439 disable_intr(); 440 441 /* Select timer0 and latch counter value. */ 442 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 443 444 low = inb(TIMER_CNTR0); 445 high = inb(TIMER_CNTR0); 446 447 write_eflags(ef); 448 return ((high << 8) | low); 449} 450 451/* 452 * Wait "n" microseconds. 453 * Relies on timer 1 counting down from (timer_freq / hz) 454 * Note: timer had better have been programmed before this is first used! 455 */ 456void 457DELAY(int n) 458{ 459 int delta, prev_tick, tick, ticks_left, sec, usec; 460 461#ifdef DELAYDEBUG 462 int getit_calls = 1; 463 int n1; 464 static int state = 0; 465 466 if (state == 0) { 467 state = 1; 468 for (n1 = 1; n1 <= 10000000; n1 *= 10) 469 DELAY(n1); 470 state = 2; 471 } 472 if (state == 1) 473 printf("DELAY(%d)...", n); 474#endif 475 /* 476 * Guard against the timer being uninitialized if we are called 477 * early for console i/o. 478 */ 479 if (timer0_max_count == 0) 480 set_timer_freq(timer_freq, hz); 481 482 /* 483 * Read the counter first, so that the rest of the setup overhead is 484 * counted. Guess the initial overhead is 20 usec (on most systems it 485 * takes about 1.5 usec for each of the i/o's in getit(). The loop 486 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 487 * multiplications and divisions to scale the count take a while). 488 */ 489 prev_tick = getit(); 490 n -= 20; 491 /* 492 * Calculate (n * (timer_freq / 1e6)) without using floating point 493 * and without any avoidable overflows. 494 */ 495 sec = n / 1000000; 496 usec = n - sec * 1000000; 497 ticks_left = sec * timer_freq 498 + usec * (timer_freq / 1000000) 499 + usec * ((timer_freq % 1000000) / 1000) / 1000 500 + usec * (timer_freq % 1000) / 1000000; 501 if (n < 0) 502 ticks_left = 0; /* XXX timer_freq is unsigned */ 503 504 while (ticks_left > 0) { 505 tick = getit(); 506#ifdef DELAYDEBUG 507 ++getit_calls; 508#endif 509 delta = prev_tick - tick; 510 prev_tick = tick; 511 if (delta < 0) { 512 delta += timer0_max_count; 513 /* 514 * Guard against timer0_max_count being wrong. 515 * This shouldn't happen in normal operation, 516 * but it may happen if set_timer_freq() is 517 * traced. 518 */ 519 if (delta < 0) 520 delta = 0; 521 } 522 ticks_left -= delta; 523 } 524#ifdef DELAYDEBUG 525 if (state == 1) 526 printf(" %d calls to getit() at %d usec each\n", 527 getit_calls, (n + 5) / getit_calls); 528#endif 529} 530 531static void 532sysbeepstop(void *chan) 533{ 534#ifdef PC98 /* PC98 */ 535 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 536 release_timer1(); 537#else 538 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 539 release_timer2(); 540#endif 541 beeping = 0; 542} 543 544int 545sysbeep(int pitch, int period) 546{ 547 int x = splclock(); 548 549#ifdef PC98 550 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 551 if (!beeping) { 552 /* Something else owns it. */ 553 splx(x); 554 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 555 } 556 disable_intr(); 557 outb(0x3fdb, pitch); 558 outb(0x3fdb, (pitch>>8)); 559 enable_intr(); 560 if (!beeping) { 561 /* enable counter1 output to speaker */ 562 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 563 beeping = period; 564 timeout(sysbeepstop, (void *)NULL, period); 565 } 566#else 567 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 568 if (!beeping) { 569 /* Something else owns it. */ 570 splx(x); 571 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 572 } 573 disable_intr(); 574 outb(TIMER_CNTR2, pitch); 575 outb(TIMER_CNTR2, (pitch>>8)); 576 enable_intr(); 577 if (!beeping) { 578 /* enable counter2 output to speaker */ 579 outb(IO_PPI, inb(IO_PPI) | 3); 580 beeping = period; 581 timeout(sysbeepstop, (void *)NULL, period); 582 } 583#endif 584 splx(x); 585 return (0); 586} 587 588#ifndef PC98 589/* 590 * RTC support routines 591 */ 592 593int 594rtcin(reg) 595 int reg; 596{ 597 u_char val; 598 599 outb(IO_RTC, reg); 600 inb(0x84); 601 val = inb(IO_RTC + 1); 602 inb(0x84); 603 return (val); 604} 605 606static __inline void 607writertc(u_char reg, u_char val) 608{ 609 outb(IO_RTC, reg); 610 outb(IO_RTC + 1, val); 611} 612 613static __inline int 614readrtc(int port) 615{ 616 return(bcd2bin(rtcin(port))); 617} 618#endif 619 620#ifdef PC98 621unsigned int delaycount; 622#define FIRST_GUESS 0x2000 623static void findcpuspeed(void) 624{ 625 int i; 626 int remainder; 627 628 /* Put counter in count down mode */ 629 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 630 outb(TIMER_CNTR0, 0xff); 631 outb(TIMER_CNTR0, 0xff); 632 for (i = FIRST_GUESS; i; i--) 633 ; 634 remainder = getit(); 635 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 636} 637#endif 638 639#ifndef PC98 640static u_int 641calibrate_clocks(void) 642{ 643 u_int count, prev_count, tot_count; 644 int sec, start_sec, timeout; 645 646 printf("Calibrating clock(s) relative to mc146818A clock ... "); 647 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 648 goto fail; 649 timeout = 100000000; 650 651 /* Read the mc146818A seconds counter. */ 652 for (;;) { 653 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 654 sec = rtcin(RTC_SEC); 655 break; 656 } 657 if (--timeout == 0) 658 goto fail; 659 } 660 661 /* Wait for the mC146818A seconds counter to change. */ 662 start_sec = sec; 663 for (;;) { 664 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 665 sec = rtcin(RTC_SEC); 666 if (sec != start_sec) 667 break; 668 } 669 if (--timeout == 0) 670 goto fail; 671 } 672 673 /* Start keeping track of the i8254 counter. */ 674 prev_count = getit(); 675 if (prev_count == 0 || prev_count > timer0_max_count) 676 goto fail; 677 tot_count = 0; 678 679#if defined(I586_CPU) || defined(I686_CPU) 680 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) 681 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 682#endif 683 684 /* 685 * Wait for the mc146818A seconds counter to change. Read the i8254 686 * counter for each iteration since this is convenient and only 687 * costs a few usec of inaccuracy. The timing of the final reads 688 * of the counters almost matches the timing of the initial reads, 689 * so the main cause of inaccuracy is the varying latency from 690 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 691 * rtcin(RTC_SEC) that returns a changed seconds count. The 692 * maximum inaccuracy from this cause is < 10 usec on 486's. 693 */ 694 start_sec = sec; 695 for (;;) { 696 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 697 sec = rtcin(RTC_SEC); 698 count = getit(); 699 if (count == 0 || count > timer0_max_count) 700 goto fail; 701 if (count > prev_count) 702 tot_count += prev_count - (count - timer0_max_count); 703 else 704 tot_count += prev_count - count; 705 prev_count = count; 706 if (sec != start_sec) 707 break; 708 if (--timeout == 0) 709 goto fail; 710 } 711 712#if defined(I586_CPU) || defined(I686_CPU) 713 /* 714 * Read the cpu cycle counter. The timing considerations are 715 * similar to those for the i8254 clock. 716 */ 717 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) { 718 set_i586_ctr_freq((u_int)rdtsc(), tot_count); 719 printf("i586 clock: %u Hz, ", i586_ctr_freq); 720 } 721#endif 722 723 printf("i8254 clock: %u Hz\n", tot_count); 724 return (tot_count); 725 726fail: 727 printf("failed, using default i8254 clock of %u Hz\n", timer_freq); 728 return (timer_freq); 729} 730#endif /* !PC98 */ 731 732static void 733set_timer_freq(u_int freq, int intr_freq) 734{ 735 u_long ef; 736 737 ef = read_eflags(); 738 disable_intr(); 739 timer_freq = freq; 740 timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 741 timer0_overflow_threshold = timer0_max_count - TIMER0_LATCH_COUNT; 742 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 743 outb(TIMER_CNTR0, timer0_max_count & 0xff); 744 outb(TIMER_CNTR0, timer0_max_count >> 8); 745 write_eflags(ef); 746} 747 748/* 749 * Initialize 8253 timer 0 early so that it can be used in DELAY(). 750 * XXX initialization of other timers is unintentionally left blank. 751 */ 752void 753startrtclock() 754{ 755 u_int delta, freq; 756 757#ifdef PC98 758 findcpuspeed(); 759#ifndef AUTO_CLOCK 760 if (pc98_machine_type & M_8M) { 761#ifndef PC98_8M 762 printf("you must reconfig a kernel with \"PC98_8M\" option.\n"); 763#endif 764 } else { 765#ifdef PC98_8M 766 printf("You must reconfig a kernel without \"PC98_8M\" option.\n"); 767#endif 768 } 769#else /* AUTO_CLOCK */ 770 if (pc98_machine_type & M_8M) 771 timer_freq = 1996800L; /* 1.9968 MHz */ 772 else 773 timer_freq = 2457600L; /* 2.4576 MHz */ 774#endif /* AUTO_CLOCK */ 775#endif /* PC98 */ 776 777#ifndef PC98 778 writertc(RTC_STATUSA, rtc_statusa); 779 writertc(RTC_STATUSB, RTCSB_24HR); 780#endif 781 782#ifndef PC98 783 set_timer_freq(timer_freq, hz); 784 freq = calibrate_clocks(); 785#ifdef CLK_CALIBRATION_LOOP 786 if (bootverbose) { 787 printf( 788 "Press a key on the console to abort clock calibration\n"); 789 while (cncheckc() == -1) 790 calibrate_clocks(); 791 } 792#endif 793 794 /* 795 * Use the calibrated i8254 frequency if it seems reasonable. 796 * Otherwise use the default, and don't use the calibrated i586 797 * frequency. 798 */ 799 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 800 if (delta < timer_freq / 100) { 801#ifndef CLK_USE_I8254_CALIBRATION 802 if (bootverbose) 803 printf( 804"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 805 freq = timer_freq; 806#endif 807 timer_freq = freq; 808 } else { 809 printf("%d Hz differs from default of %d Hz by more than 1%%\n", 810 freq, timer_freq); 811#if defined(I586_CPU) || defined(I686_CPU) 812 i586_ctr_freq = 0; 813#endif 814 } 815#endif 816 817 set_timer_freq(timer_freq, hz); 818 819#if defined(I586_CPU) || defined(I686_CPU) 820#ifndef CLK_USE_I586_CALIBRATION 821 if (i586_ctr_freq != 0) { 822 if (bootverbose) 823 printf( 824"CLK_USE_I586_CALIBRATION not specified - using old calibration method\n"); 825 i586_ctr_freq = 0; 826 } 827#endif 828 if (i586_ctr_freq == 0 && 829 (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686)) { 830 /* 831 * Calibration of the i586 clock relative to the mc146818A 832 * clock failed. Do a less accurate calibration relative 833 * to the i8254 clock. 834 */ 835 wrmsr(0x10, 0LL); /* XXX */ 836 DELAY(1000000); 837 set_i586_ctr_freq((u_int)rdtsc(), timer_freq); 838#ifdef CLK_USE_I586_CALIBRATION 839 printf("i586 clock: %u Hz\n", i586_ctr_freq); 840#endif 841 } 842#endif 843} 844 845#ifdef PC98 846static void 847rtc_serialcombit(int i) 848{ 849 outb(IO_RTC, ((i&0x01)<<5)|0x07); 850 DELAY(1); 851 outb(IO_RTC, ((i&0x01)<<5)|0x17); 852 DELAY(1); 853 outb(IO_RTC, ((i&0x01)<<5)|0x07); 854 DELAY(1); 855} 856 857static void 858rtc_serialcom(int i) 859{ 860 rtc_serialcombit(i&0x01); 861 rtc_serialcombit((i&0x02)>>1); 862 rtc_serialcombit((i&0x04)>>2); 863 rtc_serialcombit((i&0x08)>>3); 864 outb(IO_RTC, 0x07); 865 DELAY(1); 866 outb(IO_RTC, 0x0f); 867 DELAY(1); 868 outb(IO_RTC, 0x07); 869 DELAY(1); 870} 871 872static void 873rtc_outb(int val) 874{ 875 int s; 876 int sa = 0; 877 878 for (s=0;s<8;s++) { 879 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 880 outb(IO_RTC, sa); /* set DI & CLK 0 */ 881 DELAY(1); 882 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 883 DELAY(1); 884 } 885 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 886} 887 888static int 889rtc_inb(void) 890{ 891 int s; 892 int sa = 0; 893 894 for (s=0;s<8;s++) { 895 sa |= ((inb(0x33) & 0x01) << s); 896 outb(IO_RTC, 0x17); /* CLK 1 */ 897 DELAY(1); 898 outb(IO_RTC, 0x07); /* CLK 0 */ 899 DELAY(2); 900 } 901 return sa; 902} 903#endif /* PC-98 */ 904 905/* 906 * Initialize the time of day register, based on the time base which is, e.g. 907 * from a filesystem. 908 */ 909void 910inittodr(time_t base) 911{ 912 unsigned long sec, days; 913 int yd; 914 int year, month; 915 int y, m, s; 916#ifdef PC98 917 int second, min, hour; 918#endif 919 920 s = splclock(); 921 time.tv_sec = base; 922 time.tv_usec = 0; 923 splx(s); 924 925#ifdef PC98 926 rtc_serialcom(0x03); /* Time Read */ 927 rtc_serialcom(0x01); /* Register shift command. */ 928 DELAY(20); 929 930 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 931 min = bcd2bin(rtc_inb() & 0xff); /* min */ 932 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 933 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 934 935 month = (rtc_inb() >> 4) & 0x0f; /* month */ 936 for (m = 1; m < month; m++) 937 days += daysinmonth[m-1]; 938 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 939 /* 2000 year problem */ 940 if (year < 1995) 941 year += 100; 942 if (year < 1970) 943 goto wrong_time; 944 for (y = 1970; y < year; y++) 945 days += DAYSPERYEAR + LEAPYEAR(y); 946 if ((month > 2) && LEAPYEAR(year)) 947 days ++; 948 sec = ((( days * 24 + 949 hour) * 60 + 950 min) * 60 + 951 second); 952 /* sec now contains the number of seconds, since Jan 1 1970, 953 in the local time zone */ 954#else /* IBM-PC */ 955 /* Look if we have a RTC present and the time is valid */ 956 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 957 goto wrong_time; 958 959 /* wait for time update to complete */ 960 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 961 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 962 963 days = 0; 964#ifdef USE_RTC_CENTURY 965 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 966#else 967 year = readrtc(RTC_YEAR) + 1900; 968 if (year < 1970) 969 year += 100; 970#endif 971 if (year < 1970) 972 goto wrong_time; 973 month = readrtc(RTC_MONTH); 974 for (m = 1; m < month; m++) 975 days += daysinmonth[m-1]; 976 if ((month > 2) && LEAPYEAR(year)) 977 days ++; 978 days += readrtc(RTC_DAY) - 1; 979 yd = days; 980 for (y = 1970; y < year; y++) 981 days += DAYSPERYEAR + LEAPYEAR(y); 982 sec = ((( days * 24 + 983 readrtc(RTC_HRS)) * 60 + 984 readrtc(RTC_MIN)) * 60 + 985 readrtc(RTC_SEC)); 986 /* sec now contains the number of seconds, since Jan 1 1970, 987 in the local time zone */ 988#endif 989 990 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 991 992 s = splclock(); 993 time.tv_sec = sec; 994 splx(s); 995 return; 996 997wrong_time: 998 printf("Invalid time in real time clock.\n"); 999 printf("Check and reset the date immediately!\n"); 1000} 1001 1002/* 1003 * Write system time back to RTC 1004 */ 1005void 1006resettodr() 1007{ 1008 unsigned long tm; 1009 int y, m, s; 1010#ifdef PC98 1011 int wd; 1012#endif 1013 1014 if (disable_rtc_set) 1015 return; 1016 1017 s = splclock(); 1018 tm = time.tv_sec; 1019 splx(s); 1020 1021#ifdef PC98 1022 rtc_serialcom(0x01); /* Register shift command. */ 1023 1024 /* Calculate local time to put in RTC */ 1025 1026 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1027 1028 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1029 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1030 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1031 1032 /* We have now the days since 01-01-1970 in tm */ 1033 wd = (tm+4)%7; 1034 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1035 tm >= m; 1036 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1037 tm -= m; 1038 1039 /* Now we have the years in y and the day-of-the-year in tm */ 1040 for (m = 0; ; m++) { 1041 int ml; 1042 1043 ml = daysinmonth[m]; 1044 if (m == 1 && LEAPYEAR(y)) 1045 ml++; 1046 if (tm < ml) 1047 break; 1048 tm -= ml; 1049 } 1050 1051 m++; 1052 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1053 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1054 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1055 1056 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1057 rtc_serialcom(0x00); /* Register hold command. */ 1058#else 1059 /* Disable RTC updates and interrupts. */ 1060 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1061 1062 /* Calculate local time to put in RTC */ 1063 1064 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1065 1066 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1067 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1068 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1069 1070 /* We have now the days since 01-01-1970 in tm */ 1071 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1072 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1073 tm >= m; 1074 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1075 tm -= m; 1076 1077 /* Now we have the years in y and the day-of-the-year in tm */ 1078 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1079#ifdef USE_RTC_CENTURY 1080 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1081#endif 1082 for (m = 0; ; m++) { 1083 int ml; 1084 1085 ml = daysinmonth[m]; 1086 if (m == 1 && LEAPYEAR(y)) 1087 ml++; 1088 if (tm < ml) 1089 break; 1090 tm -= ml; 1091 } 1092 1093 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1094 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1095 1096 /* Reenable RTC updates and interrupts. */ 1097 writertc(RTC_STATUSB, rtc_statusb); 1098#endif 1099} 1100 1101/* 1102 * Start both clocks running. 1103 */ 1104void 1105cpu_initclocks() 1106{ 1107#ifndef PC98 1108 int diag; 1109 1110 if (statclock_disable) { 1111 /* 1112 * The stat interrupt mask is different without the 1113 * statistics clock. Also, don't set the interrupt 1114 * flag which would normally cause the RTC to generate 1115 * interrupts. 1116 */ 1117 stat_imask = HWI_MASK | SWI_MASK; 1118 rtc_statusb = RTCSB_24HR; 1119 } else { 1120 /* Setting stathz to nonzero early helps avoid races. */ 1121 stathz = RTC_NOPROFRATE; 1122 profhz = RTC_PROFRATE; 1123 } 1124#endif 1125 1126 /* Finish initializing 8253 timer 0. */ 1127 register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, 1128 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1129 /* unit */ 0); 1130 INTREN(IRQ0); 1131#if defined(I586_CPU) || defined(I686_CPU) 1132 /* 1133 * Finish setting up anti-jitter measures. 1134 */ 1135 if (i586_ctr_freq != 0) 1136 i586_ctr_bias = rdtsc(); 1137#endif 1138 1139#ifndef PC98 1140 /* Initialize RTC. */ 1141 writertc(RTC_STATUSA, rtc_statusa); 1142 writertc(RTC_STATUSB, RTCSB_24HR); 1143 1144 /* Don't bother enabling the statistics clock. */ 1145 if (statclock_disable) 1146 return; 1147 diag = rtcin(RTC_DIAG); 1148 if (diag != 0) 1149 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1150 register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, 1151 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1152 /* unit */ 0); 1153 INTREN(IRQ8); 1154 writertc(RTC_STATUSB, rtc_statusb); 1155#endif 1156} 1157 1158void 1159setstatclockrate(int newhz) 1160{ 1161#ifndef PC98 1162 if (newhz == RTC_PROFRATE) 1163 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1164 else 1165 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1166 writertc(RTC_STATUSA, rtc_statusa); 1167#endif 1168} 1169 1170static int 1171sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1172{ 1173 int error; 1174 u_int freq; 1175 1176 /* 1177 * Use `i8254' instead of `timer' in external names because `timer' 1178 * is is too generic. Should use it everywhere. 1179 */ 1180 freq = timer_freq; 1181 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1182 if (error == 0 && req->newptr != NULL) { 1183 if (timer0_state != 0) 1184 return (EBUSY); /* too much trouble to handle */ 1185 set_timer_freq(freq, hz); 1186#if defined(I586_CPU) || defined(I686_CPU) 1187 set_i586_ctr_freq(i586_ctr_freq, timer_freq); 1188#endif 1189 } 1190 return (error); 1191} 1192 1193SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1194 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1195 1196#if defined(I586_CPU) || defined(I686_CPU) 1197static void 1198set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq) 1199{ 1200 u_int comultiplier, multiplier; 1201 u_long ef; 1202 1203 if (i586_freq == 0) { 1204 i586_ctr_freq = i586_freq; 1205 return; 1206 } 1207 comultiplier = ((unsigned long long)i586_freq 1208 << I586_CTR_COMULTIPLIER_SHIFT) / i8254_freq; 1209 multiplier = (1000000LL << I586_CTR_MULTIPLIER_SHIFT) / i586_freq; 1210 ef = read_eflags(); 1211 disable_intr(); 1212 i586_ctr_freq = i586_freq; 1213 i586_ctr_comultiplier = comultiplier; 1214 i586_ctr_multiplier = multiplier; 1215 write_eflags(ef); 1216} 1217 1218static int 1219sysctl_machdep_i586_freq SYSCTL_HANDLER_ARGS 1220{ 1221 int error; 1222 u_int freq; 1223 1224 if (cpu_class != CPUCLASS_586 && cpu_class != CPUCLASS_686) 1225 return (EOPNOTSUPP); 1226 freq = i586_ctr_freq; 1227 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1228 if (error == 0 && req->newptr != NULL) 1229 set_i586_ctr_freq(freq, timer_freq); 1230 return (error); 1231} 1232 1233SYSCTL_PROC(_machdep, OID_AUTO, i586_freq, CTLTYPE_INT | CTLFLAG_RW, 1234 0, sizeof(u_int), sysctl_machdep_i586_freq, "I", ""); 1235#endif /* defined(I586_CPU) || defined(I686_CPU) */ 1236