pcrtc.c revision 19269
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $Id: clock.c,v 1.9 1996/10/29 08:36:19 asami Exp $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51/* 52 * modified for PC98 by Kakefuda 53 */ 54 55#include "opt_clock.h" 56#include "opt_cpu.h" 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/time.h> 61#include <sys/kernel.h> 62#include <sys/sysctl.h> 63 64#include <machine/clock.h> 65#ifdef CLK_CALIBRATION_LOOP 66#include <machine/cons.h> 67#endif 68#include <machine/cpu.h> 69#include <machine/frame.h> 70 71#include <i386/isa/icu.h> 72#ifdef PC98 73#include <pc98/pc98/pc98.h> 74#include <i386/isa/isa_device.h> 75#else 76#include <i386/isa/isa.h> 77#include <i386/isa/isa_device.h> 78#include <i386/isa/rtc.h> 79#endif 80#include <i386/isa/timerreg.h> 81 82/* 83 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 84 * can use a simple formula for leap years. 85 */ 86#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 87#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 88 89#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 90 91/* 92 * Time in timer cycles that it takes for microtime() to disable interrupts 93 * and latch the count. microtime() currently uses "cli; outb ..." so it 94 * normally takes less than 2 timer cycles. Add a few for cache misses. 95 * Add a few more to allow for latency in bogus calls to microtime() with 96 * interrupts already disabled. 97 */ 98#define TIMER0_LATCH_COUNT 20 99 100/* 101 * Maximum frequency that we are willing to allow for timer0. Must be 102 * low enough to guarantee that the timer interrupt handler returns 103 * before the next timer interrupt. Must result in a lower TIMER_DIV 104 * value than TIMER0_LATCH_COUNT so that we don't have to worry about 105 * underflow in the calculation of timer0_overflow_threshold. 106 */ 107#define TIMER0_MAX_FREQ 20000 108 109int adjkerntz; /* local offset from GMT in seconds */ 110int disable_rtc_set; /* disable resettodr() if != 0 */ 111u_int idelayed; 112#if defined(I586_CPU) || defined(I686_CPU) 113u_int i586_ctr_bias; 114u_int i586_ctr_comultiplier; 115u_int i586_ctr_freq; 116u_int i586_ctr_multiplier; 117#endif 118int statclock_disable; 119u_int stat_imask = SWI_CLOCK_MASK; 120#ifdef TIMER_FREQ 121u_int timer_freq = TIMER_FREQ; 122#else 123#ifdef PC98 124#ifndef AUTO_CLOCK 125#ifndef PC98_8M 126u_int timer_freq = 2457600; 127#else /* !PC98_8M */ 128u_int timer_freq = 1996800; 129#endif /* PC98_8M */ 130#else /* AUTO_CLOCK */ 131u_int timer_freq = 2457600; 132#endif /* AUTO_CLOCK */ 133#else /* IBM-PC */ 134u_int timer_freq = 1193182; 135#endif /* PC98 */ 136#endif 137int timer0_max_count; 138u_int timer0_overflow_threshold; 139u_int timer0_prescaler_count; 140int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 141 142static int beeping = 0; 143static u_int clk_imask = HWI_MASK | SWI_MASK; 144static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 145static u_int hardclock_max_count; 146/* 147 * XXX new_function and timer_func should not handle clockframes, but 148 * timer_func currently needs to hold hardclock to handle the 149 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 150 * to switch between clkintr() and a slightly different timerintr(). 151 */ 152static void (*new_function) __P((struct clockframe *frame)); 153static u_int new_rate; 154#ifndef PC98 155static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 156static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 157#endif 158 159/* Values for timerX_state: */ 160#define RELEASED 0 161#define RELEASE_PENDING 1 162#define ACQUIRED 2 163#define ACQUIRE_PENDING 3 164 165static u_char timer0_state; 166#ifdef PC98 167static u_char timer1_state; 168#endif 169static u_char timer2_state; 170static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 171int rtc_inb __P((void)); 172 173#if defined(I586_CPU) || defined(I686_CPU) 174static void set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq); 175#endif 176 177static void 178clkintr(struct clockframe frame) 179{ 180 timer_func(&frame); 181 switch (timer0_state) { 182 183 case RELEASED: 184 setdelayed(); 185 break; 186 187 case ACQUIRED: 188 if ((timer0_prescaler_count += timer0_max_count) 189 >= hardclock_max_count) { 190 hardclock(&frame); 191 setdelayed(); 192 timer0_prescaler_count -= hardclock_max_count; 193 } 194 break; 195 196 case ACQUIRE_PENDING: 197 setdelayed(); 198 timer0_max_count = TIMER_DIV(new_rate); 199 timer0_overflow_threshold = 200 timer0_max_count - TIMER0_LATCH_COUNT; 201 disable_intr(); 202 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 203 outb(TIMER_CNTR0, timer0_max_count & 0xff); 204 outb(TIMER_CNTR0, timer0_max_count >> 8); 205 enable_intr(); 206 timer0_prescaler_count = 0; 207 timer_func = new_function; 208 timer0_state = ACQUIRED; 209 break; 210 211 case RELEASE_PENDING: 212 if ((timer0_prescaler_count += timer0_max_count) 213 >= hardclock_max_count) { 214 hardclock(&frame); 215 setdelayed(); 216 timer0_max_count = hardclock_max_count; 217 timer0_overflow_threshold = 218 timer0_max_count - TIMER0_LATCH_COUNT; 219 disable_intr(); 220 outb(TIMER_MODE, 221 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 222 outb(TIMER_CNTR0, timer0_max_count & 0xff); 223 outb(TIMER_CNTR0, timer0_max_count >> 8); 224 enable_intr(); 225 /* 226 * See microtime.s for this magic. 227 */ 228#ifdef PC98 229#ifndef AUTO_CLOCK 230#ifndef PC98_8M 231 time.tv_usec += (6667 * 232 (timer0_prescaler_count - hardclock_max_count)) 233 >> 14; 234#else /* PC98_8M */ 235 time.tv_usec += (16411 * 236 (timer0_prescaler_count - hardclock_max_count)) 237 >> 15; 238#endif /* PC98_8M */ 239#else /* AUTO_CLOCK */ 240 if (pc98_machine_type & M_8M) { 241 /* PC98_8M */ 242 time.tv_usec += (16411 * 243 (timer0_prescaler_count - 244 hardclock_max_count)) >> 15; 245 } else { 246 time.tv_usec += (6667 * 247 (timer0_prescaler_count - 248 hardclock_max_count)) >> 14; 249 } 250#endif /* AUTO_CLOCK */ 251#else /* IBM-PC */ 252 time.tv_usec += (27465 * 253 (timer0_prescaler_count - hardclock_max_count)) 254 >> 15; 255#endif /* PC98 */ 256 if (time.tv_usec >= 1000000) 257 time.tv_usec -= 1000000; 258 timer0_prescaler_count = 0; 259 timer_func = hardclock; 260 timer0_state = RELEASED; 261 } 262 break; 263 } 264} 265 266/* 267 * The acquire and release functions must be called at ipl >= splclock(). 268 */ 269int 270acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 271{ 272 static int old_rate; 273 274 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 275 return (-1); 276 switch (timer0_state) { 277 278 case RELEASED: 279 timer0_state = ACQUIRE_PENDING; 280 break; 281 282 case RELEASE_PENDING: 283 if (rate != old_rate) 284 return (-1); 285 /* 286 * The timer has been released recently, but is being 287 * re-acquired before the release completed. In this 288 * case, we simply reclaim it as if it had not been 289 * released at all. 290 */ 291 timer0_state = ACQUIRED; 292 break; 293 294 default: 295 return (-1); /* busy */ 296 } 297 new_function = function; 298 old_rate = new_rate = rate; 299 return (0); 300} 301 302#ifdef PC98 303int 304acquire_timer1(int mode) 305{ 306 307 if (timer1_state != RELEASED) 308 return (-1); 309 timer1_state = ACQUIRED; 310 311 /* 312 * This access to the timer registers is as atomic as possible 313 * because it is a single instruction. We could do better if we 314 * knew the rate. Use of splclock() limits glitches to 10-100us, 315 * and this is probably good enough for timer2, so we aren't as 316 * careful with it as with timer0. 317 */ 318 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 319 320 return (0); 321} 322#endif 323 324int 325acquire_timer2(int mode) 326{ 327 328 if (timer2_state != RELEASED) 329 return (-1); 330 timer2_state = ACQUIRED; 331 332 /* 333 * This access to the timer registers is as atomic as possible 334 * because it is a single instruction. We could do better if we 335 * knew the rate. Use of splclock() limits glitches to 10-100us, 336 * and this is probably good enough for timer2, so we aren't as 337 * careful with it as with timer0. 338 */ 339 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 340 341 return (0); 342} 343 344int 345release_timer0() 346{ 347 switch (timer0_state) { 348 349 case ACQUIRED: 350 timer0_state = RELEASE_PENDING; 351 break; 352 353 case ACQUIRE_PENDING: 354 /* Nothing happened yet, release quickly. */ 355 timer0_state = RELEASED; 356 break; 357 358 default: 359 return (-1); 360 } 361 return (0); 362} 363 364#ifdef PC98 365int 366release_timer1() 367{ 368 369 if (timer1_state != ACQUIRED) 370 return (-1); 371 timer1_state = RELEASED; 372 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 373 return (0); 374} 375#endif 376 377int 378release_timer2() 379{ 380 381 if (timer2_state != ACQUIRED) 382 return (-1); 383 timer2_state = RELEASED; 384 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 385 return (0); 386} 387 388#ifndef PC98 389/* 390 * This routine receives statistical clock interrupts from the RTC. 391 * As explained above, these occur at 128 interrupts per second. 392 * When profiling, we receive interrupts at a rate of 1024 Hz. 393 * 394 * This does not actually add as much overhead as it sounds, because 395 * when the statistical clock is active, the hardclock driver no longer 396 * needs to keep (inaccurate) statistics on its own. This decouples 397 * statistics gathering from scheduling interrupts. 398 * 399 * The RTC chip requires that we read status register C (RTC_INTR) 400 * to acknowledge an interrupt, before it will generate the next one. 401 */ 402static void 403rtcintr(struct clockframe frame) 404{ 405 u_char stat; 406 stat = rtcin(RTC_INTR); 407 if(stat & RTCIR_PERIOD) { 408 statclock(&frame); 409 } 410} 411 412#include "opt_ddb.h" 413#ifdef DDB 414#include <ddb/ddb.h> 415 416DB_SHOW_COMMAND(rtc, rtc) 417{ 418 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 419 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 420 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 421 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 422} 423#endif /* DDB */ 424#endif /* for PC98 */ 425 426static int 427getit(void) 428{ 429 u_long ef; 430 int high, low; 431 432 ef = read_eflags(); 433 disable_intr(); 434 435 /* Select timer0 and latch counter value. */ 436 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 437 438 low = inb(TIMER_CNTR0); 439 high = inb(TIMER_CNTR0); 440 441 write_eflags(ef); 442 return ((high << 8) | low); 443} 444 445/* 446 * Wait "n" microseconds. 447 * Relies on timer 1 counting down from (timer_freq / hz) 448 * Note: timer had better have been programmed before this is first used! 449 */ 450void 451DELAY(int n) 452{ 453 int prev_tick, tick, ticks_left, sec, usec; 454 455#ifdef DELAYDEBUG 456 int getit_calls = 1; 457 int n1; 458 static int state = 0; 459 460 if (state == 0) { 461 state = 1; 462 for (n1 = 1; n1 <= 10000000; n1 *= 10) 463 DELAY(n1); 464 state = 2; 465 } 466 if (state == 1) 467 printf("DELAY(%d)...", n); 468#endif 469 /* 470 * Read the counter first, so that the rest of the setup overhead is 471 * counted. Guess the initial overhead is 20 usec (on most systems it 472 * takes about 1.5 usec for each of the i/o's in getit(). The loop 473 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 474 * multiplications and divisions to scale the count take a while). 475 */ 476 prev_tick = getit(); 477 n -= 20; 478 /* 479 * Calculate (n * (timer_freq / 1e6)) without using floating point 480 * and without any avoidable overflows. 481 */ 482 sec = n / 1000000; 483 usec = n - sec * 1000000; 484 ticks_left = sec * timer_freq 485 + usec * (timer_freq / 1000000) 486 + usec * ((timer_freq % 1000000) / 1000) / 1000 487 + usec * (timer_freq % 1000) / 1000000; 488 if (n < 0) 489 ticks_left = 0; /* XXX timer_freq is unsigned */ 490 491 while (ticks_left > 0) { 492 tick = getit(); 493#ifdef DELAYDEBUG 494 ++getit_calls; 495#endif 496 if (tick > prev_tick) 497 ticks_left -= prev_tick - (tick - timer0_max_count); 498 else 499 ticks_left -= prev_tick - tick; 500 prev_tick = tick; 501 } 502#ifdef DELAYDEBUG 503 if (state == 1) 504 printf(" %d calls to getit() at %d usec each\n", 505 getit_calls, (n + 5) / getit_calls); 506#endif 507} 508 509static void 510sysbeepstop(void *chan) 511{ 512#ifdef PC98 /* PC98 */ 513 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 514 release_timer1(); 515#else 516 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 517 release_timer2(); 518#endif 519 beeping = 0; 520} 521 522int 523sysbeep(int pitch, int period) 524{ 525 int x = splclock(); 526 527#ifdef PC98 528 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 529 if (!beeping) { 530 /* Something else owns it. */ 531 splx(x); 532 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 533 } 534 disable_intr(); 535 outb(0x3fdb, pitch); 536 outb(0x3fdb, (pitch>>8)); 537 enable_intr(); 538 if (!beeping) { 539 /* enable counter1 output to speaker */ 540 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 541 beeping = period; 542 timeout(sysbeepstop, (void *)NULL, period); 543 } 544#else 545 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 546 if (!beeping) { 547 /* Something else owns it. */ 548 splx(x); 549 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 550 } 551 disable_intr(); 552 outb(TIMER_CNTR2, pitch); 553 outb(TIMER_CNTR2, (pitch>>8)); 554 enable_intr(); 555 if (!beeping) { 556 /* enable counter2 output to speaker */ 557 outb(IO_PPI, inb(IO_PPI) | 3); 558 beeping = period; 559 timeout(sysbeepstop, (void *)NULL, period); 560 } 561#endif 562 splx(x); 563 return (0); 564} 565 566#ifndef PC98 567/* 568 * RTC support routines 569 */ 570 571int 572rtcin(reg) 573 int reg; 574{ 575 u_char val; 576 577 outb(IO_RTC, reg); 578 inb(0x84); 579 val = inb(IO_RTC + 1); 580 inb(0x84); 581 return (val); 582} 583 584static __inline void 585writertc(u_char reg, u_char val) 586{ 587 outb(IO_RTC, reg); 588 outb(IO_RTC + 1, val); 589} 590 591static __inline int 592readrtc(int port) 593{ 594 return(bcd2bin(rtcin(port))); 595} 596#endif 597 598#ifdef PC98 599unsigned int delaycount; 600#define FIRST_GUESS 0x2000 601static void findcpuspeed(void) 602{ 603 int i; 604 int remainder; 605 606 /* Put counter in count down mode */ 607 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 608 outb(TIMER_CNTR0, 0xff); 609 outb(TIMER_CNTR0, 0xff); 610 for (i = FIRST_GUESS; i; i--) 611 ; 612 remainder = getit(); 613 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 614} 615#endif 616 617#ifndef PC98 618static u_int 619calibrate_clocks(void) 620{ 621 u_int count, prev_count, tot_count; 622 int sec, start_sec, timeout; 623 624 printf("Calibrating clock(s) relative to mc146818A clock ... "); 625 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 626 goto fail; 627 timeout = 100000000; 628 629 /* Read the mc146818A seconds counter. */ 630 for (;;) { 631 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 632 sec = rtcin(RTC_SEC); 633 break; 634 } 635 if (--timeout == 0) 636 goto fail; 637 } 638 639 /* Wait for the mC146818A seconds counter to change. */ 640 start_sec = sec; 641 for (;;) { 642 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 643 sec = rtcin(RTC_SEC); 644 if (sec != start_sec) 645 break; 646 } 647 if (--timeout == 0) 648 goto fail; 649 } 650 651 /* Start keeping track of the i8254 counter. */ 652 prev_count = getit(); 653 if (prev_count == 0 || prev_count > timer0_max_count) 654 goto fail; 655 tot_count = 0; 656 657#if defined(I586_CPU) || defined(I686_CPU) 658 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) 659 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 660#endif 661 662 /* 663 * Wait for the mc146818A seconds counter to change. Read the i8254 664 * counter for each iteration since this is convenient and only 665 * costs a few usec of inaccuracy. The timing of the final reads 666 * of the counters almost matches the timing of the initial reads, 667 * so the main cause of inaccuracy is the varying latency from 668 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 669 * rtcin(RTC_SEC) that returns a changed seconds count. The 670 * maximum inaccuracy from this cause is < 10 usec on 486's. 671 */ 672 start_sec = sec; 673 for (;;) { 674 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 675 sec = rtcin(RTC_SEC); 676 count = getit(); 677 if (count == 0 || count > timer0_max_count) 678 goto fail; 679 if (count > prev_count) 680 tot_count += prev_count - (count - timer0_max_count); 681 else 682 tot_count += prev_count - count; 683 prev_count = count; 684 if (sec != start_sec) 685 break; 686 if (--timeout == 0) 687 goto fail; 688 } 689 690#if defined(I586_CPU) || defined(I686_CPU) 691 /* 692 * Read the cpu cycle counter. The timing considerations are 693 * similar to those for the i8254 clock. 694 */ 695 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) { 696 set_i586_ctr_freq((u_int)rdtsc(), tot_count); 697 printf("i586 clock: %u Hz, ", i586_ctr_freq); 698 } 699#endif 700 701 printf("i8254 clock: %u Hz\n", tot_count); 702 return (tot_count); 703 704fail: 705 printf("failed, using default i8254 clock of %u Hz\n", timer_freq); 706 return (timer_freq); 707} 708#endif /* !PC98 */ 709 710static void 711set_timer_freq(u_int freq, int intr_freq) 712{ 713 u_long ef; 714 715 ef = read_eflags(); 716 disable_intr(); 717 timer_freq = freq; 718 timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 719 timer0_overflow_threshold = timer0_max_count - TIMER0_LATCH_COUNT; 720 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 721 outb(TIMER_CNTR0, timer0_max_count & 0xff); 722 outb(TIMER_CNTR0, timer0_max_count >> 8); 723 write_eflags(ef); 724} 725 726/* 727 * Initialize 8253 timer 0 early so that it can be used in DELAY(). 728 * XXX initialization of other timers is unintentionally left blank. 729 */ 730void 731startrtclock() 732{ 733 u_int delta, freq; 734 735#ifdef PC98 736 findcpuspeed(); 737#ifndef AUTO_CLOCK 738 if (pc98_machine_type & M_8M) { 739#ifndef PC98_8M 740 printf("you must reconfig a kernel with \"PC98_8M\" option.\n"); 741#endif 742 } else { 743#ifdef PC98_8M 744 printf("You must reconfig a kernel without \"PC98_8M\" option.\n"); 745#endif 746 } 747#else /* AUTO_CLOCK */ 748 if (pc98_machine_type & M_8M) 749 timer_freq = 1996800L; /* 1.9968 MHz */ 750 else 751 timer_freq = 2457600L; /* 2.4576 MHz */ 752#endif /* AUTO_CLOCK */ 753#endif /* PC98 */ 754 755#ifndef PC98 756 writertc(RTC_STATUSA, rtc_statusa); 757 writertc(RTC_STATUSB, RTCSB_24HR); 758#endif 759 760#ifndef PC98 761 set_timer_freq(timer_freq, hz); 762 freq = calibrate_clocks(); 763#ifdef CLK_CALIBRATION_LOOP 764 if (bootverbose) { 765 printf( 766 "Press a key on the console to abort clock calibration\n"); 767 while (cncheckc() == -1) 768 calibrate_clocks(); 769 } 770#endif 771 772 /* 773 * Use the calibrated i8254 frequency if it seems reasonable. 774 * Otherwise use the default, and don't use the calibrated i586 775 * frequency. 776 */ 777 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 778 if (delta < timer_freq / 100) { 779#ifndef CLK_USE_I8254_CALIBRATION 780 if (bootverbose) 781 printf( 782"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 783 freq = timer_freq; 784#endif 785 timer_freq = freq; 786 } else { 787 printf("%d Hz differs from default of %d Hz by more than 1%%\n", 788 freq, timer_freq); 789#if defined(I586_CPU) || defined(I686_CPU) 790 i586_ctr_freq = 0; 791#endif 792 } 793#endif 794 795 set_timer_freq(timer_freq, hz); 796 797#if defined(I586_CPU) || defined(I686_CPU) 798#ifndef CLK_USE_I586_CALIBRATION 799 if (i586_ctr_freq != 0) { 800 if (bootverbose) 801 printf( 802"CLK_USE_I586_CALIBRATION not specified - using old calibration method\n"); 803 i586_ctr_freq = 0; 804 } 805#endif 806 if (i586_ctr_freq == 0 && 807 (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686)) { 808 /* 809 * Calibration of the i586 clock relative to the mc146818A 810 * clock failed. Do a less accurate calibration relative 811 * to the i8254 clock. 812 */ 813 wrmsr(0x10, 0LL); /* XXX */ 814 DELAY(1000000); 815 set_i586_ctr_freq((u_int)rdtsc(), timer_freq); 816#ifdef CLK_USE_I586_CALIBRATION 817 printf("i586 clock: %u Hz\n", i586_ctr_freq); 818#endif 819 } 820#endif 821} 822 823#ifdef PC98 824void 825rtc_serialcombit(int i) 826{ 827 outb(IO_RTC, ((i&0x01)<<5)|0x07); 828 DELAY(1); 829 outb(IO_RTC, ((i&0x01)<<5)|0x17); 830 DELAY(1); 831 outb(IO_RTC, ((i&0x01)<<5)|0x07); 832 DELAY(1); 833} 834 835void 836rtc_serialcom(int i) 837{ 838 rtc_serialcombit(i&0x01); 839 rtc_serialcombit((i&0x02)>>1); 840 rtc_serialcombit((i&0x04)>>2); 841 rtc_serialcombit((i&0x08)>>3); 842 outb(IO_RTC, 0x07); 843 DELAY(1); 844 outb(IO_RTC, 0x0f); 845 DELAY(1); 846 outb(IO_RTC, 0x07); 847 DELAY(1); 848} 849 850void 851rtc_outb(int val) 852{ 853 int s; 854 int sa = 0; 855 856 for (s=0;s<8;s++) { 857 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 858 outb(IO_RTC, sa); /* set DI & CLK 0 */ 859 DELAY(1); 860 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 861 DELAY(1); 862 } 863 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 864} 865 866int 867rtc_inb(void) 868{ 869 int s; 870 int sa = 0; 871 872 for (s=0;s<8;s++) { 873 sa |= ((inb(0x33) & 0x01) << s); 874 outb(IO_RTC, 0x17); /* CLK 1 */ 875 DELAY(1); 876 outb(IO_RTC, 0x07); /* CLK 0 */ 877 DELAY(2); 878 } 879 return sa; 880} 881#endif /* PC-98 */ 882 883/* 884 * Initialize the time of day register, based on the time base which is, e.g. 885 * from a filesystem. 886 */ 887void 888inittodr(time_t base) 889{ 890 unsigned long sec, days; 891 int yd; 892 int year, month; 893 int y, m, s; 894#ifdef PC98 895 int second, min, hour; 896#endif 897 898 s = splclock(); 899 time.tv_sec = base; 900 time.tv_usec = 0; 901 splx(s); 902 903#ifdef PC98 904 rtc_serialcom(0x03); /* Time Read */ 905 rtc_serialcom(0x01); /* Register shift command. */ 906 DELAY(20); 907 908 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 909 min = bcd2bin(rtc_inb() & 0xff); /* min */ 910 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 911 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 912 913 month = (rtc_inb() >> 4) & 0x0f; /* month */ 914 for (m = 1; m < month; m++) 915 days += daysinmonth[m-1]; 916 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 917 /* 2000 year problem */ 918 if (year < 1995) 919 year += 100; 920 if (year < 1970) 921 goto wrong_time; 922 for (y = 1970; y < year; y++) 923 days += DAYSPERYEAR + LEAPYEAR(y); 924 if ((month > 2) && LEAPYEAR(year)) 925 days ++; 926 sec = ((( days * 24 + 927 hour) * 60 + 928 min) * 60 + 929 second); 930 /* sec now contains the number of seconds, since Jan 1 1970, 931 in the local time zone */ 932#else /* IBM-PC */ 933 /* Look if we have a RTC present and the time is valid */ 934 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 935 goto wrong_time; 936 937 /* wait for time update to complete */ 938 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 939 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 940 941 days = 0; 942#ifdef USE_RTC_CENTURY 943 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 944#else 945 year = readrtc(RTC_YEAR) + 1900; 946 if (year < 1970) 947 year += 100; 948#endif 949 if (year < 1970) 950 goto wrong_time; 951 month = readrtc(RTC_MONTH); 952 for (m = 1; m < month; m++) 953 days += daysinmonth[m-1]; 954 if ((month > 2) && LEAPYEAR(year)) 955 days ++; 956 days += readrtc(RTC_DAY) - 1; 957 yd = days; 958 for (y = 1970; y < year; y++) 959 days += DAYSPERYEAR + LEAPYEAR(y); 960 sec = ((( days * 24 + 961 readrtc(RTC_HRS)) * 60 + 962 readrtc(RTC_MIN)) * 60 + 963 readrtc(RTC_SEC)); 964 /* sec now contains the number of seconds, since Jan 1 1970, 965 in the local time zone */ 966#endif 967 968 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 969 970 s = splclock(); 971 time.tv_sec = sec; 972 splx(s); 973 return; 974 975wrong_time: 976 printf("Invalid time in real time clock.\n"); 977 printf("Check and reset the date immediately!\n"); 978} 979 980/* 981 * Write system time back to RTC 982 */ 983void 984resettodr() 985{ 986 unsigned long tm; 987 int y, m, s; 988#ifdef PC98 989 int wd; 990#endif 991 992 if (disable_rtc_set) 993 return; 994 995 s = splclock(); 996 tm = time.tv_sec; 997 splx(s); 998 999#ifdef PC98 1000 rtc_serialcom(0x01); /* Register shift command. */ 1001 1002 /* Calculate local time to put in RTC */ 1003 1004 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1005 1006 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1007 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1008 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1009 1010 /* We have now the days since 01-01-1970 in tm */ 1011 wd = (tm+4)%7; 1012 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1013 tm >= m; 1014 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1015 tm -= m; 1016 1017 /* Now we have the years in y and the day-of-the-year in tm */ 1018 for (m = 0; ; m++) { 1019 int ml; 1020 1021 ml = daysinmonth[m]; 1022 if (m == 1 && LEAPYEAR(y)) 1023 ml++; 1024 if (tm < ml) 1025 break; 1026 tm -= ml; 1027 } 1028 1029 m++; 1030 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1031 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1032 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1033 1034 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1035 rtc_serialcom(0x00); /* Register hold command. */ 1036#else 1037 /* Disable RTC updates and interrupts. */ 1038 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1039 1040 /* Calculate local time to put in RTC */ 1041 1042 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1043 1044 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1045 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1046 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1047 1048 /* We have now the days since 01-01-1970 in tm */ 1049 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1050 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1051 tm >= m; 1052 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1053 tm -= m; 1054 1055 /* Now we have the years in y and the day-of-the-year in tm */ 1056 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1057#ifdef USE_RTC_CENTURY 1058 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1059#endif 1060 for (m = 0; ; m++) { 1061 int ml; 1062 1063 ml = daysinmonth[m]; 1064 if (m == 1 && LEAPYEAR(y)) 1065 ml++; 1066 if (tm < ml) 1067 break; 1068 tm -= ml; 1069 } 1070 1071 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1072 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1073 1074 /* Reenable RTC updates and interrupts. */ 1075 writertc(RTC_STATUSB, rtc_statusb); 1076#endif 1077} 1078 1079/* 1080 * Start both clocks running. 1081 */ 1082void 1083cpu_initclocks() 1084{ 1085#ifndef PC98 1086 int diag; 1087 1088 if (statclock_disable) { 1089 /* 1090 * The stat interrupt mask is different without the 1091 * statistics clock. Also, don't set the interrupt 1092 * flag which would normally cause the RTC to generate 1093 * interrupts. 1094 */ 1095 stat_imask = HWI_MASK | SWI_MASK; 1096 rtc_statusb = RTCSB_24HR; 1097 } else { 1098 /* Setting stathz to nonzero early helps avoid races. */ 1099 stathz = RTC_NOPROFRATE; 1100 profhz = RTC_PROFRATE; 1101 } 1102#endif 1103 1104 /* Finish initializing 8253 timer 0. */ 1105 register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, 1106 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1107 /* unit */ 0); 1108 INTREN(IRQ0); 1109#if defined(I586_CPU) || defined(I686_CPU) 1110 /* 1111 * Finish setting up anti-jitter measures. 1112 */ 1113 if (i586_ctr_freq != 0) 1114 i586_ctr_bias = rdtsc(); 1115#endif 1116 1117#ifndef PC98 1118 /* Initialize RTC. */ 1119 writertc(RTC_STATUSA, rtc_statusa); 1120 writertc(RTC_STATUSB, RTCSB_24HR); 1121 1122 /* Don't bother enabling the statistics clock. */ 1123 if (statclock_disable) 1124 return; 1125 diag = rtcin(RTC_DIAG); 1126 if (diag != 0) 1127 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1128 register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, 1129 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1130 /* unit */ 0); 1131 INTREN(IRQ8); 1132 writertc(RTC_STATUSB, rtc_statusb); 1133#endif 1134} 1135 1136void 1137setstatclockrate(int newhz) 1138{ 1139#ifndef PC98 1140 if (newhz == RTC_PROFRATE) 1141 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1142 else 1143 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1144 writertc(RTC_STATUSA, rtc_statusa); 1145#endif 1146} 1147 1148static int 1149sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1150{ 1151 int error; 1152 u_int freq; 1153 1154 /* 1155 * Use `i8254' instead of `timer' in external names because `timer' 1156 * is is too generic. Should use it everywhere. 1157 */ 1158 freq = timer_freq; 1159 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1160 if (error == 0 && req->newptr != NULL) { 1161 if (timer0_state != 0) 1162 return (EBUSY); /* too much trouble to handle */ 1163 set_timer_freq(freq, hz); 1164#if defined(I586_CPU) || defined(I686_CPU) 1165 set_i586_ctr_freq(i586_ctr_freq, timer_freq); 1166#endif 1167 } 1168 return (error); 1169} 1170 1171SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1172 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1173 1174#if defined(I586_CPU) || defined(I686_CPU) 1175static void 1176set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq) 1177{ 1178 u_int comultiplier, multiplier; 1179 u_long ef; 1180 1181 if (i586_freq == 0) { 1182 i586_ctr_freq = i586_freq; 1183 return; 1184 } 1185 comultiplier = ((unsigned long long)i586_freq 1186 << I586_CTR_COMULTIPLIER_SHIFT) / i8254_freq; 1187 multiplier = (1000000LL << I586_CTR_MULTIPLIER_SHIFT) / i586_freq; 1188 ef = read_eflags(); 1189 disable_intr(); 1190 i586_ctr_freq = i586_freq; 1191 i586_ctr_comultiplier = comultiplier; 1192 i586_ctr_multiplier = multiplier; 1193 write_eflags(ef); 1194} 1195 1196static int 1197sysctl_machdep_i586_freq SYSCTL_HANDLER_ARGS 1198{ 1199 int error; 1200 u_int freq; 1201 1202 if (cpu_class != CPUCLASS_586 && cpu_class != CPUCLASS_686) 1203 return (EOPNOTSUPP); 1204 freq = i586_ctr_freq; 1205 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1206 if (error == 0 && req->newptr != NULL) 1207 set_i586_ctr_freq(freq, timer_freq); 1208 return (error); 1209} 1210 1211SYSCTL_PROC(_machdep, OID_AUTO, i586_freq, CTLTYPE_INT | CTLFLAG_RW, 1212 0, sizeof(u_int), sysctl_machdep_i586_freq, "I", ""); 1213#endif /* defined(I586_CPU) || defined(I686_CPU) */ 1214