pcrtc.c revision 18842
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $Id: clock.c,v 1.5 1996/09/07 02:13:39 asami Exp $ 38 */ 39 40/* 41 * inittodr, settodr and support routines written 42 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 43 * 44 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 45 */ 46 47/* 48 * modified for PC98 49 * $Id: clock.c,v 1.5 1996/09/07 02:13:39 asami Exp $ 50 */ 51 52/* 53 * Primitive clock interrupt routines. 54 */ 55#include "opt_ddb.h" 56#include "opt_clock.h" 57#include "opt_cpu.h" 58 59#include <sys/param.h> 60#include <sys/systm.h> 61#include <sys/time.h> 62#include <sys/kernel.h> 63#include <sys/sysctl.h> 64 65#include <machine/clock.h> 66#ifdef CLK_CALIBRATION_LOOP 67#include <machine/cons.h> 68#endif 69#include <machine/cpu.h> 70#include <machine/frame.h> 71 72#include <i386/isa/icu.h> 73#ifdef PC98 74#include <pc98/pc98/pc98.h> 75#include <i386/isa/isa_device.h> 76#include <pc98/pc98/timerreg.h> 77#else 78#include <i386/isa/isa.h> 79#include <i386/isa/isa_device.h> 80#include <i386/isa/rtc.h> 81#include <i386/isa/timerreg.h> 82#endif 83 84/* 85 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 86 * can use a simple formula for leap years. 87 */ 88#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 89#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 90 91#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 92 93/* 94 * Time in timer cycles that it takes for microtime() to disable interrupts 95 * and latch the count. microtime() currently uses "cli; outb ..." so it 96 * normally takes less than 2 timer cycles. Add a few for cache misses. 97 * Add a few more to allow for latency in bogus calls to microtime() with 98 * interrupts already disabled. 99 */ 100#define TIMER0_LATCH_COUNT 20 101 102/* 103 * Maximum frequency that we are willing to allow for timer0. Must be 104 * low enough to guarantee that the timer interrupt handler returns 105 * before the next timer interrupt. Must result in a lower TIMER_DIV 106 * value than TIMER0_LATCH_COUNT so that we don't have to worry about 107 * underflow in the calculation of timer0_overflow_threshold. 108 */ 109#define TIMER0_MAX_FREQ 20000 110 111int adjkerntz; /* local offset from GMT in seconds */ 112int disable_rtc_set; /* disable resettodr() if != 0 */ 113int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 114 115u_int idelayed; 116#if defined(I586_CPU) || defined(I686_CPU) 117u_int i586_ctr_bias; 118u_int i586_ctr_comultiplier; 119u_int i586_ctr_freq; 120u_int i586_ctr_multiplier; 121long long i586_last_tick; 122unsigned long i586_avg_tick; 123#endif 124int statclock_disable; 125u_int stat_imask = SWI_CLOCK_MASK; 126#ifdef TIMER_FREQ 127static u_int timer_freq = TIMER_FREQ; 128#else 129#ifdef PC98 130#ifndef AUTO_CLOCK 131#ifndef PC98_8M 132static u_int timer_freq = 2457600; 133#else /* !PC98_8M */ 134static u_int timer_freq = 1996800; 135#endif /* PC98_8M */ 136#else /* AUTO_CLOCK */ 137static u_int timer_freq = 2457600; 138#endif /* AUTO_CLOCK */ 139#else /* IBM-PC */ 140static u_int timer_freq = 1193182; 141#endif /* PC98 */ 142#endif 143int timer0_max_count; 144u_int timer0_overflow_threshold; 145u_int timer0_prescaler_count; 146 147static int beeping = 0; 148static u_int clk_imask = HWI_MASK | SWI_MASK; 149static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 150static u_int hardclock_max_count; 151/* 152 * XXX new_function and timer_func should not handle clockframes, but 153 * timer_func currently needs to hold hardclock to handle the 154 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 155 * to switch between clkintr() and a slightly different timerintr(). 156 */ 157static void (*new_function) __P((struct clockframe *frame)); 158static u_int new_rate; 159#ifndef PC98 160static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 161static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 162#endif 163 164/* Values for timerX_state: */ 165#define RELEASED 0 166#define RELEASE_PENDING 1 167#define ACQUIRED 2 168#define ACQUIRE_PENDING 3 169 170static u_char timer0_state; 171#ifdef PC98 172static u_char timer1_state; 173#endif 174static u_char timer2_state; 175static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 176int rtc_inb __P((void)); 177 178#if defined(I586_CPU) || defined(I686_CPU) 179static void set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq); 180#endif 181 182static void 183clkintr(struct clockframe frame) 184{ 185 timer_func(&frame); 186 switch (timer0_state) { 187 188 case RELEASED: 189 setdelayed(); 190 break; 191 192 case ACQUIRED: 193 if ((timer0_prescaler_count += timer0_max_count) 194 >= hardclock_max_count) { 195 hardclock(&frame); 196 setdelayed(); 197 timer0_prescaler_count -= hardclock_max_count; 198 } 199 break; 200 201 case ACQUIRE_PENDING: 202 setdelayed(); 203 timer0_max_count = TIMER_DIV(new_rate); 204 timer0_overflow_threshold = 205 timer0_max_count - TIMER0_LATCH_COUNT; 206 disable_intr(); 207 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 208 outb(TIMER_CNTR0, timer0_max_count & 0xff); 209 outb(TIMER_CNTR0, timer0_max_count >> 8); 210 enable_intr(); 211 timer0_prescaler_count = 0; 212 timer_func = new_function; 213 timer0_state = ACQUIRED; 214 break; 215 216 case RELEASE_PENDING: 217 if ((timer0_prescaler_count += timer0_max_count) 218 >= hardclock_max_count) { 219 hardclock(&frame); 220 setdelayed(); 221 timer0_max_count = hardclock_max_count; 222 timer0_overflow_threshold = 223 timer0_max_count - TIMER0_LATCH_COUNT; 224 disable_intr(); 225 outb(TIMER_MODE, 226 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 227 outb(TIMER_CNTR0, timer0_max_count & 0xff); 228 outb(TIMER_CNTR0, timer0_max_count >> 8); 229 enable_intr(); 230 /* 231 * See microtime.s for this magic. 232 */ 233#ifdef PC98 234#ifndef AUTO_CLOCK 235#ifndef PC98_8M 236 time.tv_usec += (6667 * 237 (timer0_prescaler_count - hardclock_max_count)) 238 >> 14; 239#else /* PC98_8M */ 240 time.tv_usec += (16411 * 241 (timer0_prescaler_count - hardclock_max_count)) 242 >> 15; 243#endif /* PC98_8M */ 244#else /* AUTO_CLOCK */ 245 if (pc98_machine_type & M_8M) { 246 /* PC98_8M */ 247 time.tv_usec += (16411 * 248 (timer0_prescaler_count - 249 hardclock_max_count)) >> 15; 250 } else { 251 time.tv_usec += (6667 * 252 (timer0_prescaler_count - 253 hardclock_max_count)) >> 14; 254 } 255#endif /* AUTO_CLOCK */ 256#else /* IBM-PC */ 257 time.tv_usec += (27465 * 258 (timer0_prescaler_count - hardclock_max_count)) 259 >> 15; 260#endif /* PC98 */ 261 if (time.tv_usec >= 1000000) 262 time.tv_usec -= 1000000; 263 timer0_prescaler_count = 0; 264 timer_func = hardclock; 265 timer0_state = RELEASED; 266 } 267 break; 268 } 269} 270 271/* 272 * The acquire and release functions must be called at ipl >= splclock(). 273 */ 274int 275acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 276{ 277 static int old_rate; 278 279 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 280 return (-1); 281 switch (timer0_state) { 282 283 case RELEASED: 284 timer0_state = ACQUIRE_PENDING; 285 break; 286 287 case RELEASE_PENDING: 288 if (rate != old_rate) 289 return (-1); 290 /* 291 * The timer has been released recently, but is being 292 * re-acquired before the release completed. In this 293 * case, we simply reclaim it as if it had not been 294 * released at all. 295 */ 296 timer0_state = ACQUIRED; 297 break; 298 299 default: 300 return (-1); /* busy */ 301 } 302 new_function = function; 303 old_rate = new_rate = rate; 304 return (0); 305} 306 307#ifdef PC98 308int 309acquire_timer1(int mode) 310{ 311 312 if (timer1_state != RELEASED) 313 return (-1); 314 timer1_state = ACQUIRED; 315 316 /* 317 * This access to the timer registers is as atomic as possible 318 * because it is a single instruction. We could do better if we 319 * knew the rate. Use of splclock() limits glitches to 10-100us, 320 * and this is probably good enough for timer2, so we aren't as 321 * careful with it as with timer0. 322 */ 323 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 324 325 return (0); 326} 327#endif 328 329int 330acquire_timer2(int mode) 331{ 332 333 if (timer2_state != RELEASED) 334 return (-1); 335 timer2_state = ACQUIRED; 336 337 /* 338 * This access to the timer registers is as atomic as possible 339 * because it is a single instruction. We could do better if we 340 * knew the rate. Use of splclock() limits glitches to 10-100us, 341 * and this is probably good enough for timer2, so we aren't as 342 * careful with it as with timer0. 343 */ 344 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 345 346 return (0); 347} 348 349int 350release_timer0() 351{ 352 switch (timer0_state) { 353 354 case ACQUIRED: 355 timer0_state = RELEASE_PENDING; 356 break; 357 358 case ACQUIRE_PENDING: 359 /* Nothing happened yet, release quickly. */ 360 timer0_state = RELEASED; 361 break; 362 363 default: 364 return (-1); 365 } 366 return (0); 367} 368 369#ifdef PC98 370int 371release_timer1() 372{ 373 374 if (timer1_state != ACQUIRED) 375 return (-1); 376 timer1_state = RELEASED; 377 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 378 return (0); 379} 380#endif 381 382int 383release_timer2() 384{ 385 386 if (timer2_state != ACQUIRED) 387 return (-1); 388 timer2_state = RELEASED; 389 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 390 return (0); 391} 392 393#ifndef PC98 394/* 395 * This routine receives statistical clock interrupts from the RTC. 396 * As explained above, these occur at 128 interrupts per second. 397 * When profiling, we receive interrupts at a rate of 1024 Hz. 398 * 399 * This does not actually add as much overhead as it sounds, because 400 * when the statistical clock is active, the hardclock driver no longer 401 * needs to keep (inaccurate) statistics on its own. This decouples 402 * statistics gathering from scheduling interrupts. 403 * 404 * The RTC chip requires that we read status register C (RTC_INTR) 405 * to acknowledge an interrupt, before it will generate the next one. 406 */ 407static void 408rtcintr(struct clockframe frame) 409{ 410 u_char stat; 411 stat = rtcin(RTC_INTR); 412 if(stat & RTCIR_PERIOD) { 413 statclock(&frame); 414 } 415} 416 417#ifdef DDB 418static void 419DDB_printrtc(void) 420{ 421 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 422 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 423 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 424 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 425} 426#endif 427#endif /* for PC98 */ 428 429static int 430getit(void) 431{ 432 u_long ef; 433 int high, low; 434 435 ef = read_eflags(); 436 disable_intr(); 437 438 /* Select timer0 and latch counter value. */ 439 outb(TIMER_MODE, TIMER_SEL0); 440 441 low = inb(TIMER_CNTR0); 442 high = inb(TIMER_CNTR0); 443 444 write_eflags(ef); 445 return ((high << 8) | low); 446} 447 448/* 449 * Wait "n" microseconds. 450 * Relies on timer 1 counting down from (timer_freq / hz) 451 * Note: timer had better have been programmed before this is first used! 452 */ 453void 454DELAY(int n) 455{ 456 int prev_tick, tick, ticks_left, sec, usec; 457 458#ifdef DELAYDEBUG 459 int getit_calls = 1; 460 int n1; 461 static int state = 0; 462 463 if (state == 0) { 464 state = 1; 465 for (n1 = 1; n1 <= 10000000; n1 *= 10) 466 DELAY(n1); 467 state = 2; 468 } 469 if (state == 1) 470 printf("DELAY(%d)...", n); 471#endif 472 /* 473 * Read the counter first, so that the rest of the setup overhead is 474 * counted. Guess the initial overhead is 20 usec (on most systems it 475 * takes about 1.5 usec for each of the i/o's in getit(). The loop 476 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 477 * multiplications and divisions to scale the count take a while). 478 */ 479 prev_tick = getit(); 480 n -= 20; 481 /* 482 * Calculate (n * (timer_freq / 1e6)) without using floating point 483 * Calculate (n * (TIMER_FREQ / 1e6)) without using floating point 484 * and without any avoidable overflows. 485 */ 486 sec = n / 1000000; 487 usec = n - sec * 1000000; 488 ticks_left = sec * timer_freq 489 + usec * (timer_freq / 1000000) 490 + usec * ((timer_freq % 1000000) / 1000) / 1000 491 + usec * (timer_freq % 1000) / 1000000; 492 if (n < 0) 493 ticks_left = 0; /* XXX timer_freq is unsigned */ 494 495 while (ticks_left > 0) { 496 tick = getit(); 497#ifdef DELAYDEBUG 498 ++getit_calls; 499#endif 500 if (tick > prev_tick) 501 ticks_left -= prev_tick - (tick - timer0_max_count); 502 else 503 ticks_left -= prev_tick - tick; 504 prev_tick = tick; 505 } 506#ifdef DELAYDEBUG 507 if (state == 1) 508 printf(" %d calls to getit() at %d usec each\n", 509 getit_calls, (n + 5) / getit_calls); 510#endif 511} 512 513static void 514sysbeepstop(void *chan) 515{ 516#ifdef PC98 /* PC98 */ 517 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 518 release_timer1(); 519#else 520 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 521 release_timer2(); 522#endif 523 beeping = 0; 524} 525 526int 527sysbeep(int pitch, int period) 528{ 529 int x = splclock(); 530 531#ifdef PC98 532 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 533 if (!beeping) { 534 /* Something else owns it. */ 535 splx(x); 536 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 537 } 538 disable_intr(); 539 outb(0x3fdb, pitch); 540 outb(0x3fdb, (pitch>>8)); 541 enable_intr(); 542 if (!beeping) { 543 /* enable counter1 output to speaker */ 544 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 545 beeping = period; 546 timeout(sysbeepstop, (void *)NULL, period); 547 } 548#else 549 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 550 if (!beeping) { 551 /* Something else owns it. */ 552 splx(x); 553 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 554 } 555 disable_intr(); 556 outb(TIMER_CNTR2, pitch); 557 outb(TIMER_CNTR2, (pitch>>8)); 558 enable_intr(); 559 if (!beeping) { 560 /* enable counter2 output to speaker */ 561 outb(IO_PPI, inb(IO_PPI) | 3); 562 beeping = period; 563 timeout(sysbeepstop, (void *)NULL, period); 564 } 565#endif 566 splx(x); 567 return (0); 568} 569 570#ifndef PC98 571/* 572 * RTC support routines 573 */ 574 575int 576rtcin(reg) 577 int reg; 578{ 579 u_char val; 580 581 outb(IO_RTC, reg); 582 inb(0x84); 583 val = inb(IO_RTC + 1); 584 inb(0x84); 585 return (val); 586} 587 588static __inline void 589writertc(u_char reg, u_char val) 590{ 591 outb(IO_RTC, reg); 592 outb(IO_RTC + 1, val); 593} 594 595static __inline int 596readrtc(int port) 597{ 598 return(bcd2bin(rtcin(port))); 599} 600#endif 601 602#ifdef PC98 603unsigned int delaycount; 604#define FIRST_GUESS 0x2000 605static void findcpuspeed(void) 606{ 607 int i; 608 int remainder; 609 610 /* Put counter in count down mode */ 611 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 612 outb(TIMER_CNTR0, 0xff); 613 outb(TIMER_CNTR0, 0xff); 614 for (i = FIRST_GUESS; i; i--) 615 ; 616 remainder = getit(); 617 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 618} 619#endif 620 621#ifndef PC98 622static u_int 623calibrate_clocks(void) 624{ 625 u_int count, prev_count, tot_count; 626 int sec, start_sec, timeout; 627 628 printf("Calibrating clock(s) relative to mc146818A clock...\n"); 629 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 630 goto fail; 631 timeout = 100000000; 632 633 /* Read the mc146818A seconds counter. */ 634 for (;;) { 635 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 636 sec = rtcin(RTC_SEC); 637 break; 638 } 639 if (--timeout == 0) 640 goto fail; 641 } 642 643 /* Wait for the mC146818A seconds counter to change. */ 644 start_sec = sec; 645 for (;;) { 646 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 647 sec = rtcin(RTC_SEC); 648 if (sec != start_sec) 649 break; 650 } 651 if (--timeout == 0) 652 goto fail; 653 } 654 655 /* Start keeping track of the i8254 counter. */ 656 prev_count = getit(); 657 if (prev_count == 0 || prev_count > timer0_max_count) 658 goto fail; 659 tot_count = 0; 660 661#if defined(I586_CPU) || defined(I686_CPU) 662 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) 663 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 664#endif 665 666 /* 667 * Wait for the mc146818A seconds counter to change. Read the i8254 668 * counter for each iteration since this is convenient and only 669 * costs a few usec of inaccuracy. The timing of the final reads 670 * of the counters almost matches the timing of the initial reads, 671 * so the main cause of inaccuracy is the varying latency from 672 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 673 * rtcin(RTC_SEC) that returns a changed seconds count. The 674 * maximum inaccuracy from this cause is < 10 usec on 486's. 675 */ 676 start_sec = sec; 677 for (;;) { 678 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 679 sec = rtcin(RTC_SEC); 680 count = getit(); 681 if (count == 0 || count > timer0_max_count) 682 goto fail; 683 if (count > prev_count) 684 tot_count += prev_count - (count - timer0_max_count); 685 else 686 tot_count += prev_count - count; 687 prev_count = count; 688 if (sec != start_sec) 689 break; 690 if (--timeout == 0) 691 goto fail; 692 } 693 694#if defined(I586_CPU) || defined(I686_CPU) 695 /* 696 * Read the cpu cycle counter. The timing considerations are 697 * similar to those for the i8254 clock. 698 */ 699 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) { 700 set_i586_ctr_freq((u_int)rdtsc(), tot_count); 701 printf("i586 clock: %u Hz, ", i586_ctr_freq); 702 } 703#endif 704 705 printf("i8254 clock: %u Hz\n", tot_count); 706 return (tot_count); 707 708fail: 709 printf("failed, using default i8254 clock of %u Hz\n", timer_freq); 710 return (timer_freq); 711} 712#endif /* !PC98 */ 713 714static void 715set_timer_freq(u_int freq, int intr_freq) 716{ 717 u_long ef; 718 719 ef = read_eflags(); 720 disable_intr(); 721 timer_freq = freq; 722 timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 723 timer0_overflow_threshold = timer0_max_count - TIMER0_LATCH_COUNT; 724 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 725 outb(TIMER_CNTR0, timer0_max_count & 0xff); 726 outb(TIMER_CNTR0, timer0_max_count >> 8); 727 write_eflags(ef); 728} 729 730/* 731 * Initialize 8253 timer 0 early so that it can be used in DELAY(). 732 * XXX initialization of other timers is unintentionally left blank. 733 */ 734void 735startrtclock() 736{ 737 u_int delta, freq; 738 739#ifdef PC98 740 findcpuspeed(); 741#ifndef AUTO_CLOCK 742 if (pc98_machine_type & M_8M) { 743#ifndef PC98_8M 744 printf("you must reconfig a kernel with \"PC98_8M\" option.\n"); 745#endif 746 } else { 747#ifdef PC98_8M 748 printf("You must reconfig a kernel without \"PC98_8M\" option.\n"); 749#endif 750 } 751#else /* AUTO_CLOCK */ 752 if (pc98_machine_type & M_8M) 753 timer_freq = 1996800L; /* 1.9968 MHz */ 754 else 755 timer_freq = 2457600L; /* 2.4576 MHz */ 756#endif /* AUTO_CLOCK */ 757#endif /* PC98 */ 758 759#ifndef PC98 760 writertc(RTC_STATUSA, rtc_statusa); 761 writertc(RTC_STATUSB, RTCSB_24HR); 762#endif 763 764#ifndef PC98 765 set_timer_freq(timer_freq, hz); 766 freq = calibrate_clocks(); 767#ifdef CLK_CALIBRATION_LOOP 768 if (bootverbose) { 769 printf( 770 "Press a key on the console to abort clock calibration\n"); 771 while (!cncheckc()) 772 calibrate_clocks(); 773 } 774#endif 775 776 /* 777 * Use the calibrated i8254 frequency if it seems reasonable. 778 * Otherwise use the default, and don't use the calibrated i586 779 * frequency. 780 */ 781 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 782 if (delta < timer_freq / 100) { 783#ifndef CLK_USE_I8254_CALIBRATION 784 if (bootverbose) 785 printf( 786"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 787 freq = timer_freq; 788#endif 789 timer_freq = freq; 790 } else { 791 printf("%d Hz differs from default of %d Hz by more than 1%%\n", 792 freq, timer_freq); 793#if defined(I586_CPU) || defined(I686_CPU) 794 i586_ctr_freq = 0; 795#endif 796 } 797#endif 798 799 set_timer_freq(timer_freq, hz); 800 801#if defined(I586_CPU) || defined(I686_CPU) 802#ifndef CLK_USE_I586_CALIBRATION 803 if (i586_ctr_freq != 0) { 804 if (bootverbose) 805 printf( 806"CLK_USE_I586_CALIBRATION not specified - using old calibration method\n"); 807 i586_ctr_freq = 0; 808 } 809#endif 810 if (i586_ctr_freq == 0 && 811 (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686)) { 812 /* 813 * Calibration of the i586 clock relative to the mc146818A 814 * clock failed. Do a less accurate calibration relative 815 * to the i8254 clock. 816 */ 817 wrmsr(0x10, 0LL); /* XXX */ 818 DELAY(1000000); 819 set_i586_ctr_freq((u_int)rdtsc(), timer_freq); 820#ifdef CLK_USE_I586_CALIBRATION 821 printf("i586 clock: %u Hz\n", i586_ctr_freq); 822#endif 823 } 824#endif 825} 826 827#ifdef PC98 828void 829rtc_serialcombit(int i) 830{ 831 outb(IO_RTC, ((i&0x01)<<5)|0x07); 832 DELAY(1); 833 outb(IO_RTC, ((i&0x01)<<5)|0x17); 834 DELAY(1); 835 outb(IO_RTC, ((i&0x01)<<5)|0x07); 836 DELAY(1); 837} 838 839void 840rtc_serialcom(int i) 841{ 842 rtc_serialcombit(i&0x01); 843 rtc_serialcombit((i&0x02)>>1); 844 rtc_serialcombit((i&0x04)>>2); 845 rtc_serialcombit((i&0x08)>>3); 846 outb(IO_RTC, 0x07); 847 DELAY(1); 848 outb(IO_RTC, 0x0f); 849 DELAY(1); 850 outb(IO_RTC, 0x07); 851 DELAY(1); 852} 853 854void 855rtc_outb(int val) 856{ 857 int s; 858 int sa = 0; 859 860 for (s=0;s<8;s++) { 861 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 862 outb(IO_RTC, sa); /* set DI & CLK 0 */ 863 DELAY(1); 864 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 865 DELAY(1); 866 } 867 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 868} 869 870int 871rtc_inb(void) 872{ 873 int s; 874 int sa = 0; 875 876 for (s=0;s<8;s++) { 877 sa |= ((inb(0x33) & 0x01) << s); 878 outb(IO_RTC, 0x17); /* CLK 1 */ 879 DELAY(1); 880 outb(IO_RTC, 0x07); /* CLK 0 */ 881 DELAY(2); 882 } 883 return sa; 884} 885#endif /* PC-98 */ 886 887/* 888 * Initialize the time of day register, based on the time base which is, e.g. 889 * from a filesystem. 890 */ 891void 892inittodr(time_t base) 893{ 894 unsigned long sec, days; 895 int yd; 896 int year, month; 897 int y, m, s; 898#ifdef PC98 899 int second, min, hour; 900#endif 901 902 s = splclock(); 903 time.tv_sec = base; 904 time.tv_usec = 0; 905 splx(s); 906 907#ifdef PC98 908 rtc_serialcom(0x03); /* Time Read */ 909 rtc_serialcom(0x01); /* Register shift command. */ 910 DELAY(20); 911 912 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 913 min = bcd2bin(rtc_inb() & 0xff); /* min */ 914 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 915 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 916 917 month = (rtc_inb() >> 4) & 0x0f; /* month */ 918 for (m = 1; m < month; m++) 919 days += daysinmonth[m-1]; 920 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 921 /* 2000 year problem */ 922 if (year < 1995) 923 year += 100; 924 if (year < 1970) 925 goto wrong_time; 926 for (y = 1970; y < year; y++) 927 days += DAYSPERYEAR + LEAPYEAR(y); 928 if ((month > 2) && LEAPYEAR(year)) 929 days ++; 930 sec = ((( days * 24 + 931 hour) * 60 + 932 min) * 60 + 933 second); 934 /* sec now contains the number of seconds, since Jan 1 1970, 935 in the local time zone */ 936#else /* IBM-PC */ 937 /* Look if we have a RTC present and the time is valid */ 938 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 939 goto wrong_time; 940 941 /* wait for time update to complete */ 942 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 943 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 944 945 days = 0; 946#ifdef USE_RTC_CENTURY 947 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 948#else 949 year = readrtc(RTC_YEAR) + 1900; 950 if (year < 1970) 951 year += 100; 952#endif 953 if (year < 1970) 954 goto wrong_time; 955 month = readrtc(RTC_MONTH); 956 for (m = 1; m < month; m++) 957 days += daysinmonth[m-1]; 958 if ((month > 2) && LEAPYEAR(year)) 959 days ++; 960 days += readrtc(RTC_DAY) - 1; 961 yd = days; 962 for (y = 1970; y < year; y++) 963 days += DAYSPERYEAR + LEAPYEAR(y); 964 sec = ((( days * 24 + 965 readrtc(RTC_HRS)) * 60 + 966 readrtc(RTC_MIN)) * 60 + 967 readrtc(RTC_SEC)); 968 /* sec now contains the number of seconds, since Jan 1 1970, 969 in the local time zone */ 970#endif 971 972 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 973 974 s = splclock(); 975 time.tv_sec = sec; 976 splx(s); 977 return; 978 979wrong_time: 980 printf("Invalid time in real time clock.\n"); 981 printf("Check and reset the date immediately!\n"); 982} 983 984/* 985 * Write system time back to RTC 986 */ 987void 988resettodr() 989{ 990 unsigned long tm; 991 int y, m, s; 992#ifdef PC98 993 int wd; 994#endif 995 996 if (disable_rtc_set) 997 return; 998 999 s = splclock(); 1000 tm = time.tv_sec; 1001 splx(s); 1002 1003#ifdef PC98 1004 rtc_serialcom(0x01); /* Register shift command. */ 1005 1006 /* Calculate local time to put in RTC */ 1007 1008 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1009 1010 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1011 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1012 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1013 1014 /* We have now the days since 01-01-1970 in tm */ 1015 wd = (tm+4)%7; 1016 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1017 tm >= m; 1018 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1019 tm -= m; 1020 1021 /* Now we have the years in y and the day-of-the-year in tm */ 1022 for (m = 0; ; m++) { 1023 int ml; 1024 1025 ml = daysinmonth[m]; 1026 if (m == 1 && LEAPYEAR(y)) 1027 ml++; 1028 if (tm < ml) 1029 break; 1030 tm -= ml; 1031 } 1032 1033 m++; 1034 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1035 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1036 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1037 1038 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1039 rtc_serialcom(0x00); /* Register hold command. */ 1040#else 1041 /* Disable RTC updates and interrupts. */ 1042 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1043 1044 /* Calculate local time to put in RTC */ 1045 1046 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1047 1048 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1049 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1050 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1051 1052 /* We have now the days since 01-01-1970 in tm */ 1053 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1054 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1055 tm >= m; 1056 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1057 tm -= m; 1058 1059 /* Now we have the years in y and the day-of-the-year in tm */ 1060 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1061#ifdef USE_RTC_CENTURY 1062 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1063#endif 1064 for (m = 0; ; m++) { 1065 int ml; 1066 1067 ml = daysinmonth[m]; 1068 if (m == 1 && LEAPYEAR(y)) 1069 ml++; 1070 if (tm < ml) 1071 break; 1072 tm -= ml; 1073 } 1074 1075 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1076 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1077 1078 /* Reenable RTC updates and interrupts. */ 1079 writertc(RTC_STATUSB, rtc_statusb); 1080#endif 1081} 1082 1083/* 1084 * Start both clocks running. 1085 */ 1086void 1087cpu_initclocks() 1088{ 1089#ifndef PC98 1090 int diag; 1091 1092 if (statclock_disable) { 1093 /* 1094 * The stat interrupt mask is different without the 1095 * statistics clock. Also, don't set the interrupt 1096 * flag which would normally cause the RTC to generate 1097 * interrupts. 1098 */ 1099 stat_imask = HWI_MASK | SWI_MASK; 1100 rtc_statusb = RTCSB_24HR; 1101 } else { 1102 /* Setting stathz to nonzero early helps avoid races. */ 1103 stathz = RTC_NOPROFRATE; 1104 profhz = RTC_PROFRATE; 1105 } 1106#endif 1107 1108 /* Finish initializing 8253 timer 0. */ 1109 register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, 1110 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1111 /* unit */ 0); 1112 INTREN(IRQ0); 1113#if defined(I586_CPU) || defined(I686_CPU) 1114 /* 1115 * Finish setting up anti-jitter measures. 1116 */ 1117 if (i586_ctr_freq != 0) { 1118 i586_last_tick = rdtsc(); 1119 i586_ctr_bias = i586_last_tick; 1120 } 1121#endif 1122 1123#ifndef PC98 1124 /* Initialize RTC. */ 1125 writertc(RTC_STATUSA, rtc_statusa); 1126 writertc(RTC_STATUSB, RTCSB_24HR); 1127 1128static int 1129sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1130{ 1131 int error; 1132 u_int freq; 1133 1134 /* 1135 * Use `i8254' instead of `timer' in external names because `timer' 1136 * is is too generic. Should use it everywhere. 1137 */ 1138 freq = timer_freq; 1139 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1140 if (error == 0 && req->newptr != NULL) { 1141 if (timer0_state != 0) 1142 return (EBUSY); /* too much trouble to handle */ 1143 set_timer_freq(freq, hz); 1144#if defined(I586_CPU) || defined(I686_CPU) 1145 set_i586_ctr_freq(i586_ctr_freq, timer_freq); 1146#endif 1147 } 1148 return (error); 1149} 1150 1151SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1152 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1153 1154#if defined(I586_CPU) || defined(I686_CPU) 1155static void 1156set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq) 1157{ 1158 u_int comultiplier, multiplier; 1159 u_long ef; 1160 1161 if (i586_freq == 0) { 1162 i586_ctr_freq = i586_freq; 1163 return; 1164 } 1165 comultiplier = ((unsigned long long)i586_freq 1166 << I586_CTR_COMULTIPLIER_SHIFT) / i8254_freq; 1167 multiplier = (1000000LL << I586_CTR_MULTIPLIER_SHIFT) / i586_freq; 1168 ef = read_eflags(); 1169 disable_intr(); 1170 i586_ctr_freq = i586_freq; 1171 i586_ctr_comultiplier = comultiplier; 1172 i586_ctr_multiplier = multiplier; 1173 write_eflags(ef); 1174} 1175 1176static int 1177sysctl_machdep_i586_freq SYSCTL_HANDLER_ARGS 1178{ 1179 int error; 1180 u_int freq; 1181 1182 if (cpu_class != CPUCLASS_586 && cpu_class != CPUCLASS_686) 1183 return (EOPNOTSUPP); 1184 freq = i586_ctr_freq; 1185 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1186 if (error == 0 && req->newptr != NULL) 1187 set_i586_ctr_freq(freq, timer_freq); 1188 return (error); 1189} 1190 1191SYSCTL_PROC(_machdep, OID_AUTO, i586_freq, CTLTYPE_INT | CTLFLAG_RW, 1192 0, sizeof(u_int), sysctl_machdep_i586_freq, "I", ""); 1193#endif /* defined(I586_CPU) || defined(I686_CPU) */ 1194 1195 /* Don't bother enabling the statistics clock. */ 1196 if (statclock_disable) 1197 return; 1198 diag = rtcin(RTC_DIAG); 1199 if (diag != 0) 1200 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1201 register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, 1202 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1203 /* unit */ 0); 1204 INTREN(IRQ8); 1205 writertc(RTC_STATUSB, rtc_statusb); 1206#endif 1207} 1208 1209void 1210setstatclockrate(int newhz) 1211{ 1212#ifndef PC98 1213 if (newhz == RTC_PROFRATE) 1214 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1215 else 1216 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1217 writertc(RTC_STATUSA, rtc_statusa); 1218#endif 1219} 1220