pcrtc.c revision 18095
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $Id: clock.c,v 1.4 1996/09/03 10:23:24 asami Exp $ 38 */ 39 40/* 41 * inittodr, settodr and support routines written 42 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 43 * 44 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 45 */ 46 47/* 48 * modified for PC98 49 * $Id: clock.c,v 1.4 1996/09/03 10:23:24 asami Exp $ 50 */ 51 52/* 53 * Primitive clock interrupt routines. 54 */ 55#include "opt_ddb.h" 56#include "opt_clock.h" 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/time.h> 61#include <sys/kernel.h> 62#include <sys/sysctl.h> 63 64#include <machine/clock.h> 65#ifdef CLK_CALIBRATION_LOOP 66#include <machine/cons.h> 67#endif 68#include <machine/cpu.h> 69#include <machine/frame.h> 70 71#include <i386/isa/icu.h> 72#ifdef PC98 73#include <pc98/pc98/pc98.h> 74#include <i386/isa/isa_device.h> 75#include <pc98/pc98/timerreg.h> 76#else 77#include <i386/isa/isa.h> 78#include <i386/isa/isa_device.h> 79#include <i386/isa/rtc.h> 80#include <i386/isa/timerreg.h> 81#endif 82 83/* 84 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 85 * can use a simple formula for leap years. 86 */ 87#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 88#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 89 90#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 91 92/* 93 * Time in timer cycles that it takes for microtime() to disable interrupts 94 * and latch the count. microtime() currently uses "cli; outb ..." so it 95 * normally takes less than 2 timer cycles. Add a few for cache misses. 96 * Add a few more to allow for latency in bogus calls to microtime() with 97 * interrupts already disabled. 98 */ 99#define TIMER0_LATCH_COUNT 20 100 101/* 102 * Maximum frequency that we are willing to allow for timer0. Must be 103 * low enough to guarantee that the timer interrupt handler returns 104 * before the next timer interrupt. Must result in a lower TIMER_DIV 105 * value than TIMER0_LATCH_COUNT so that we don't have to worry about 106 * underflow in the calculation of timer0_overflow_threshold. 107 */ 108#define TIMER0_MAX_FREQ 20000 109 110int adjkerntz; /* local offset from GMT in seconds */ 111int disable_rtc_set; /* disable resettodr() if != 0 */ 112int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 113 114u_int idelayed; 115#if defined(I586_CPU) || defined(I686_CPU) 116u_int i586_ctr_bias; 117u_int i586_ctr_comultiplier; 118u_int i586_ctr_freq; 119u_int i586_ctr_multiplier; 120long long i586_last_tick; 121unsigned long i586_avg_tick; 122#endif 123int statclock_disable; 124u_int stat_imask = SWI_CLOCK_MASK; 125#ifdef TIMER_FREQ 126static u_int timer_freq = TIMER_FREQ; 127#else 128#ifdef PC98 129#ifndef AUTO_CLOCK 130#ifndef PC98_8M 131static u_int timer_freq = 2457600; 132#else /* !PC98_8M */ 133static u_int timer_freq = 1996800; 134#endif /* PC98_8M */ 135#else /* AUTO_CLOCK */ 136static u_int timer_freq = 2457600; 137#endif /* AUTO_CLOCK */ 138#else /* IBM-PC */ 139static u_int timer_freq = 1193182; 140#endif /* PC98 */ 141#endif 142int timer0_max_count; 143u_int timer0_overflow_threshold; 144u_int timer0_prescaler_count; 145 146static int beeping = 0; 147static u_int clk_imask = HWI_MASK | SWI_MASK; 148static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 149static u_int hardclock_max_count; 150/* 151 * XXX new_function and timer_func should not handle clockframes, but 152 * timer_func currently needs to hold hardclock to handle the 153 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 154 * to switch between clkintr() and a slightly different timerintr(). 155 */ 156static void (*new_function) __P((struct clockframe *frame)); 157static u_int new_rate; 158#ifndef PC98 159static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 160static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 161#endif 162 163/* Values for timerX_state: */ 164#define RELEASED 0 165#define RELEASE_PENDING 1 166#define ACQUIRED 2 167#define ACQUIRE_PENDING 3 168 169static u_char timer0_state; 170#ifdef PC98 171static u_char timer1_state; 172#endif 173static u_char timer2_state; 174static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 175int rtc_inb __P((void)); 176 177#if defined(I586_CPU) || defined(I686_CPU) 178static void set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq); 179#endif 180 181static void 182clkintr(struct clockframe frame) 183{ 184 timer_func(&frame); 185 switch (timer0_state) { 186 187 case RELEASED: 188 setdelayed(); 189 break; 190 191 case ACQUIRED: 192 if ((timer0_prescaler_count += timer0_max_count) 193 >= hardclock_max_count) { 194 hardclock(&frame); 195 setdelayed(); 196 timer0_prescaler_count -= hardclock_max_count; 197 } 198 break; 199 200 case ACQUIRE_PENDING: 201 setdelayed(); 202 timer0_max_count = TIMER_DIV(new_rate); 203 timer0_overflow_threshold = 204 timer0_max_count - TIMER0_LATCH_COUNT; 205 disable_intr(); 206 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 207 outb(TIMER_CNTR0, timer0_max_count & 0xff); 208 outb(TIMER_CNTR0, timer0_max_count >> 8); 209 enable_intr(); 210 timer0_prescaler_count = 0; 211 timer_func = new_function; 212 timer0_state = ACQUIRED; 213 break; 214 215 case RELEASE_PENDING: 216 if ((timer0_prescaler_count += timer0_max_count) 217 >= hardclock_max_count) { 218 hardclock(&frame); 219 setdelayed(); 220 timer0_max_count = hardclock_max_count; 221 timer0_overflow_threshold = 222 timer0_max_count - TIMER0_LATCH_COUNT; 223 disable_intr(); 224 outb(TIMER_MODE, 225 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 226 outb(TIMER_CNTR0, timer0_max_count & 0xff); 227 outb(TIMER_CNTR0, timer0_max_count >> 8); 228 enable_intr(); 229 /* 230 * See microtime.s for this magic. 231 */ 232#ifdef PC98 233#ifndef AUTO_CLOCK 234#ifndef PC98_8M 235 time.tv_usec += (6667 * 236 (timer0_prescaler_count - hardclock_max_count)) 237 >> 14; 238#else /* PC98_8M */ 239 time.tv_usec += (16411 * 240 (timer0_prescaler_count - hardclock_max_count)) 241 >> 15; 242#endif /* PC98_8M */ 243#else /* AUTO_CLOCK */ 244 if (pc98_machine_type & M_8M) { 245 /* PC98_8M */ 246 time.tv_usec += (16411 * 247 (timer0_prescaler_count - 248 hardclock_max_count)) >> 15; 249 } else { 250 time.tv_usec += (6667 * 251 (timer0_prescaler_count - 252 hardclock_max_count)) >> 14; 253 } 254#endif /* AUTO_CLOCK */ 255#else /* IBM-PC */ 256 time.tv_usec += (27465 * 257 (timer0_prescaler_count - hardclock_max_count)) 258 >> 15; 259#endif /* PC98 */ 260 if (time.tv_usec >= 1000000) 261 time.tv_usec -= 1000000; 262 timer0_prescaler_count = 0; 263 timer_func = hardclock; 264 timer0_state = RELEASED; 265 } 266 break; 267 } 268} 269 270/* 271 * The acquire and release functions must be called at ipl >= splclock(). 272 */ 273int 274acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 275{ 276 static int old_rate; 277 278 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 279 return (-1); 280 switch (timer0_state) { 281 282 case RELEASED: 283 timer0_state = ACQUIRE_PENDING; 284 break; 285 286 case RELEASE_PENDING: 287 if (rate != old_rate) 288 return (-1); 289 /* 290 * The timer has been released recently, but is being 291 * re-acquired before the release completed. In this 292 * case, we simply reclaim it as if it had not been 293 * released at all. 294 */ 295 timer0_state = ACQUIRED; 296 break; 297 298 default: 299 return (-1); /* busy */ 300 } 301 new_function = function; 302 old_rate = new_rate = rate; 303 return (0); 304} 305 306#ifdef PC98 307int 308acquire_timer1(int mode) 309{ 310 311 if (timer1_state != RELEASED) 312 return (-1); 313 timer1_state = ACQUIRED; 314 315 /* 316 * This access to the timer registers is as atomic as possible 317 * because it is a single instruction. We could do better if we 318 * knew the rate. Use of splclock() limits glitches to 10-100us, 319 * and this is probably good enough for timer2, so we aren't as 320 * careful with it as with timer0. 321 */ 322 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 323 324 return (0); 325} 326#endif 327 328int 329acquire_timer2(int mode) 330{ 331 332 if (timer2_state != RELEASED) 333 return (-1); 334 timer2_state = ACQUIRED; 335 336 /* 337 * This access to the timer registers is as atomic as possible 338 * because it is a single instruction. We could do better if we 339 * knew the rate. Use of splclock() limits glitches to 10-100us, 340 * and this is probably good enough for timer2, so we aren't as 341 * careful with it as with timer0. 342 */ 343 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 344 345 return (0); 346} 347 348int 349release_timer0() 350{ 351 switch (timer0_state) { 352 353 case ACQUIRED: 354 timer0_state = RELEASE_PENDING; 355 break; 356 357 case ACQUIRE_PENDING: 358 /* Nothing happened yet, release quickly. */ 359 timer0_state = RELEASED; 360 break; 361 362 default: 363 return (-1); 364 } 365 return (0); 366} 367 368#ifdef PC98 369int 370release_timer1() 371{ 372 373 if (timer1_state != ACQUIRED) 374 return (-1); 375 timer1_state = RELEASED; 376 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 377 return (0); 378} 379#endif 380 381int 382release_timer2() 383{ 384 385 if (timer2_state != ACQUIRED) 386 return (-1); 387 timer2_state = RELEASED; 388 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 389 return (0); 390} 391 392#ifndef PC98 393/* 394 * This routine receives statistical clock interrupts from the RTC. 395 * As explained above, these occur at 128 interrupts per second. 396 * When profiling, we receive interrupts at a rate of 1024 Hz. 397 * 398 * This does not actually add as much overhead as it sounds, because 399 * when the statistical clock is active, the hardclock driver no longer 400 * needs to keep (inaccurate) statistics on its own. This decouples 401 * statistics gathering from scheduling interrupts. 402 * 403 * The RTC chip requires that we read status register C (RTC_INTR) 404 * to acknowledge an interrupt, before it will generate the next one. 405 */ 406static void 407rtcintr(struct clockframe frame) 408{ 409 u_char stat; 410 stat = rtcin(RTC_INTR); 411 if(stat & RTCIR_PERIOD) { 412 statclock(&frame); 413 } 414} 415 416#ifdef DDB 417static void 418DDB_printrtc(void) 419{ 420 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 421 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 422 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 423 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 424} 425#endif 426#endif /* for PC98 */ 427 428static int 429getit(void) 430{ 431 u_long ef; 432 int high, low; 433 434 ef = read_eflags(); 435 disable_intr(); 436 437 /* Select timer0 and latch counter value. */ 438 outb(TIMER_MODE, TIMER_SEL0); 439 440 low = inb(TIMER_CNTR0); 441 high = inb(TIMER_CNTR0); 442 443 write_eflags(ef); 444 return ((high << 8) | low); 445} 446 447/* 448 * Wait "n" microseconds. 449 * Relies on timer 1 counting down from (timer_freq / hz) 450 * Note: timer had better have been programmed before this is first used! 451 */ 452void 453DELAY(int n) 454{ 455 int prev_tick, tick, ticks_left, sec, usec; 456 457#ifdef DELAYDEBUG 458 int getit_calls = 1; 459 int n1; 460 static int state = 0; 461 462 if (state == 0) { 463 state = 1; 464 for (n1 = 1; n1 <= 10000000; n1 *= 10) 465 DELAY(n1); 466 state = 2; 467 } 468 if (state == 1) 469 printf("DELAY(%d)...", n); 470#endif 471 /* 472 * Read the counter first, so that the rest of the setup overhead is 473 * counted. Guess the initial overhead is 20 usec (on most systems it 474 * takes about 1.5 usec for each of the i/o's in getit(). The loop 475 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 476 * multiplications and divisions to scale the count take a while). 477 */ 478 prev_tick = getit(); 479 n -= 20; 480 /* 481 * Calculate (n * (timer_freq / 1e6)) without using floating point 482 * Calculate (n * (TIMER_FREQ / 1e6)) without using floating point 483 * and without any avoidable overflows. 484 */ 485 sec = n / 1000000; 486 usec = n - sec * 1000000; 487 ticks_left = sec * timer_freq 488 + usec * (timer_freq / 1000000) 489 + usec * ((timer_freq % 1000000) / 1000) / 1000 490 + usec * (timer_freq % 1000) / 1000000; 491 if (n < 0) 492 ticks_left = 0; /* XXX timer_freq is unsigned */ 493 494 while (ticks_left > 0) { 495 tick = getit(); 496#ifdef DELAYDEBUG 497 ++getit_calls; 498#endif 499 if (tick > prev_tick) 500 ticks_left -= prev_tick - (tick - timer0_max_count); 501 else 502 ticks_left -= prev_tick - tick; 503 prev_tick = tick; 504 } 505#ifdef DELAYDEBUG 506 if (state == 1) 507 printf(" %d calls to getit() at %d usec each\n", 508 getit_calls, (n + 5) / getit_calls); 509#endif 510} 511 512static void 513sysbeepstop(void *chan) 514{ 515#ifdef PC98 /* PC98 */ 516 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 517 release_timer1(); 518#else 519 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 520 release_timer2(); 521#endif 522 beeping = 0; 523} 524 525int 526sysbeep(int pitch, int period) 527{ 528 int x = splclock(); 529 530#ifdef PC98 531 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 532 if (!beeping) { 533 /* Something else owns it. */ 534 splx(x); 535 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 536 } 537 disable_intr(); 538 outb(0x3fdb, pitch); 539 outb(0x3fdb, (pitch>>8)); 540 enable_intr(); 541 if (!beeping) { 542 /* enable counter1 output to speaker */ 543 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 544 beeping = period; 545 timeout(sysbeepstop, (void *)NULL, period); 546 } 547#else 548 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 549 if (!beeping) { 550 /* Something else owns it. */ 551 splx(x); 552 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 553 } 554 disable_intr(); 555 outb(TIMER_CNTR2, pitch); 556 outb(TIMER_CNTR2, (pitch>>8)); 557 enable_intr(); 558 if (!beeping) { 559 /* enable counter2 output to speaker */ 560 outb(IO_PPI, inb(IO_PPI) | 3); 561 beeping = period; 562 timeout(sysbeepstop, (void *)NULL, period); 563 } 564#endif 565 splx(x); 566 return (0); 567} 568 569#ifndef PC98 570/* 571 * RTC support routines 572 */ 573 574int 575rtcin(reg) 576 int reg; 577{ 578 u_char val; 579 580 outb(IO_RTC, reg); 581 inb(0x84); 582 val = inb(IO_RTC + 1); 583 inb(0x84); 584 return (val); 585} 586 587static __inline void 588writertc(u_char reg, u_char val) 589{ 590 outb(IO_RTC, reg); 591 outb(IO_RTC + 1, val); 592} 593 594static __inline int 595readrtc(int port) 596{ 597 return(bcd2bin(rtcin(port))); 598} 599#endif 600 601#ifdef PC98 602unsigned int delaycount; 603#define FIRST_GUESS 0x2000 604static void findcpuspeed(void) 605{ 606 int i; 607 int remainder; 608 609 /* Put counter in count down mode */ 610 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 611 outb(TIMER_CNTR0, 0xff); 612 outb(TIMER_CNTR0, 0xff); 613 for (i = FIRST_GUESS; i; i--) 614 ; 615 remainder = getit(); 616 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 617} 618#endif 619 620#ifndef PC98 621static u_int 622calibrate_clocks(void) 623{ 624 u_int count, prev_count, tot_count; 625 int sec, start_sec, timeout; 626 627 printf("Calibrating clock(s) relative to mc146818A clock...\n"); 628 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 629 goto fail; 630 timeout = 100000000; 631 632 /* Read the mc146818A seconds counter. */ 633 for (;;) { 634 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 635 sec = rtcin(RTC_SEC); 636 break; 637 } 638 if (--timeout == 0) 639 goto fail; 640 } 641 642 /* Wait for the mC146818A seconds counter to change. */ 643 start_sec = sec; 644 for (;;) { 645 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 646 sec = rtcin(RTC_SEC); 647 if (sec != start_sec) 648 break; 649 } 650 if (--timeout == 0) 651 goto fail; 652 } 653 654 /* Start keeping track of the i8254 counter. */ 655 prev_count = getit(); 656 if (prev_count == 0 || prev_count > timer0_max_count) 657 goto fail; 658 tot_count = 0; 659 660#if defined(I586_CPU) || defined(I686_CPU) 661 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) 662 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 663#endif 664 665 /* 666 * Wait for the mc146818A seconds counter to change. Read the i8254 667 * counter for each iteration since this is convenient and only 668 * costs a few usec of inaccuracy. The timing of the final reads 669 * of the counters almost matches the timing of the initial reads, 670 * so the main cause of inaccuracy is the varying latency from 671 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 672 * rtcin(RTC_SEC) that returns a changed seconds count. The 673 * maximum inaccuracy from this cause is < 10 usec on 486's. 674 */ 675 start_sec = sec; 676 for (;;) { 677 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 678 sec = rtcin(RTC_SEC); 679 count = getit(); 680 if (count == 0 || count > timer0_max_count) 681 goto fail; 682 if (count > prev_count) 683 tot_count += prev_count - (count - timer0_max_count); 684 else 685 tot_count += prev_count - count; 686 prev_count = count; 687 if (sec != start_sec) 688 break; 689 if (--timeout == 0) 690 goto fail; 691 } 692 693#if defined(I586_CPU) || defined(I686_CPU) 694 /* 695 * Read the cpu cycle counter. The timing considerations are 696 * similar to those for the i8254 clock. 697 */ 698 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) { 699 set_i586_ctr_freq((u_int)rdtsc(), tot_count); 700 printf("i586 clock: %u Hz, ", i586_ctr_freq); 701 } 702#endif 703 704 printf("i8254 clock: %u Hz\n", tot_count); 705 return (tot_count); 706 707fail: 708 printf("failed, using default i8254 clock of %u Hz\n", timer_freq); 709 return (timer_freq); 710} 711#endif /* !PC98 */ 712 713static void 714set_timer_freq(u_int freq, int intr_freq) 715{ 716 u_long ef; 717 718 ef = read_eflags(); 719 disable_intr(); 720 timer_freq = freq; 721 timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 722 timer0_overflow_threshold = timer0_max_count - TIMER0_LATCH_COUNT; 723 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 724 outb(TIMER_CNTR0, timer0_max_count & 0xff); 725 outb(TIMER_CNTR0, timer0_max_count >> 8); 726 write_eflags(ef); 727} 728 729/* 730 * Initialize 8253 timer 0 early so that it can be used in DELAY(). 731 * XXX initialization of other timers is unintentionally left blank. 732 */ 733void 734startrtclock() 735{ 736 u_int delta, freq; 737 738#ifdef PC98 739 findcpuspeed(); 740#ifndef AUTO_CLOCK 741 if (pc98_machine_type & M_8M) { 742#ifndef PC98_8M 743 printf("you must reconfig a kernel with \"PC98_8M\" option.\n"); 744#endif 745 } else { 746#ifdef PC98_8M 747 printf("You must reconfig a kernel without \"PC98_8M\" option.\n"); 748#endif 749 } 750#else /* AUTO_CLOCK */ 751 if (pc98_machine_type & M_8M) 752 timer_freq = 1996800L; /* 1.9968 MHz */ 753 else 754 timer_freq = 2457600L; /* 2.4576 MHz */ 755#endif /* AUTO_CLOCK */ 756#endif /* PC98 */ 757 758#ifndef PC98 759 writertc(RTC_STATUSA, rtc_statusa); 760 writertc(RTC_STATUSB, RTCSB_24HR); 761#endif 762 763#ifndef PC98 764 set_timer_freq(timer_freq, hz); 765 freq = calibrate_clocks(); 766#ifdef CLK_CALIBRATION_LOOP 767 if (bootverbose) { 768 printf( 769 "Press a key on the console to abort clock calibration\n"); 770 while (!cncheckc()) 771 calibrate_clocks(); 772 } 773#endif 774 775 /* 776 * Use the calibrated i8254 frequency if it seems reasonable. 777 * Otherwise use the default, and don't use the calibrated i586 778 * frequency. 779 */ 780 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 781 if (delta < timer_freq / 100) { 782#ifndef CLK_USE_I8254_CALIBRATION 783 if (bootverbose) 784 printf( 785"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 786 freq = timer_freq; 787#endif 788 timer_freq = freq; 789 } else { 790 printf("%d Hz differs from default of %d Hz by more than 1%%\n", 791 freq, timer_freq); 792#if defined(I586_CPU) || defined(I686_CPU) 793 i586_ctr_freq = 0; 794#endif 795 } 796#endif 797 798 set_timer_freq(timer_freq, hz); 799 800#if defined(I586_CPU) || defined(I686_CPU) 801#ifndef CLK_USE_I586_CALIBRATION 802 if (i586_ctr_freq != 0) { 803 if (bootverbose) 804 printf( 805"CLK_USE_I586_CALIBRATION not specified - using old calibration method\n"); 806 i586_ctr_freq = 0; 807 } 808#endif 809 if (i586_ctr_freq == 0 && 810 (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686)) { 811 /* 812 * Calibration of the i586 clock relative to the mc146818A 813 * clock failed. Do a less accurate calibration relative 814 * to the i8254 clock. 815 */ 816 wrmsr(0x10, 0LL); /* XXX */ 817 DELAY(1000000); 818 set_i586_ctr_freq((u_int)rdtsc(), timer_freq); 819#ifdef CLK_USE_I586_CALIBRATION 820 printf("i586 clock: %u Hz\n", i586_ctr_freq); 821#endif 822 } 823#endif 824} 825 826#ifdef PC98 827void 828rtc_serialcombit(int i) 829{ 830 outb(IO_RTC, ((i&0x01)<<5)|0x07); 831 DELAY(1); 832 outb(IO_RTC, ((i&0x01)<<5)|0x17); 833 DELAY(1); 834 outb(IO_RTC, ((i&0x01)<<5)|0x07); 835 DELAY(1); 836} 837 838void 839rtc_serialcom(int i) 840{ 841 rtc_serialcombit(i&0x01); 842 rtc_serialcombit((i&0x02)>>1); 843 rtc_serialcombit((i&0x04)>>2); 844 rtc_serialcombit((i&0x08)>>3); 845 outb(IO_RTC, 0x07); 846 DELAY(1); 847 outb(IO_RTC, 0x0f); 848 DELAY(1); 849 outb(IO_RTC, 0x07); 850 DELAY(1); 851} 852 853void 854rtc_outb(int val) 855{ 856 int s; 857 int sa = 0; 858 859 for (s=0;s<8;s++) { 860 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 861 outb(IO_RTC, sa); /* set DI & CLK 0 */ 862 DELAY(1); 863 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 864 DELAY(1); 865 } 866 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 867} 868 869int 870rtc_inb(void) 871{ 872 int s; 873 int sa = 0; 874 875 for (s=0;s<8;s++) { 876 sa |= ((inb(0x33) & 0x01) << s); 877 outb(IO_RTC, 0x17); /* CLK 1 */ 878 DELAY(1); 879 outb(IO_RTC, 0x07); /* CLK 0 */ 880 DELAY(2); 881 } 882 return sa; 883} 884#endif /* PC-98 */ 885 886/* 887 * Initialize the time of day register, based on the time base which is, e.g. 888 * from a filesystem. 889 */ 890void 891inittodr(time_t base) 892{ 893 unsigned long sec, days; 894 int yd; 895 int year, month; 896 int y, m, s; 897#ifdef PC98 898 int second, min, hour; 899#endif 900 901 s = splclock(); 902 time.tv_sec = base; 903 time.tv_usec = 0; 904 splx(s); 905 906#ifdef PC98 907 rtc_serialcom(0x03); /* Time Read */ 908 rtc_serialcom(0x01); /* Register shift command. */ 909 DELAY(20); 910 911 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 912 min = bcd2bin(rtc_inb() & 0xff); /* min */ 913 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 914 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 915 916 month = (rtc_inb() >> 4) & 0x0f; /* month */ 917 for (m = 1; m < month; m++) 918 days += daysinmonth[m-1]; 919 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 920 /* 2000 year problem */ 921 if (year < 1995) 922 year += 100; 923 if (year < 1970) 924 goto wrong_time; 925 for (y = 1970; y < year; y++) 926 days += DAYSPERYEAR + LEAPYEAR(y); 927 if ((month > 2) && LEAPYEAR(year)) 928 days ++; 929 sec = ((( days * 24 + 930 hour) * 60 + 931 min) * 60 + 932 second); 933 /* sec now contains the number of seconds, since Jan 1 1970, 934 in the local time zone */ 935#else /* IBM-PC */ 936 /* Look if we have a RTC present and the time is valid */ 937 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 938 goto wrong_time; 939 940 /* wait for time update to complete */ 941 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 942 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 943 944 days = 0; 945#ifdef USE_RTC_CENTURY 946 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 947#else 948 year = readrtc(RTC_YEAR) + 1900; 949 if (year < 1970) 950 year += 100; 951#endif 952 if (year < 1970) 953 goto wrong_time; 954 month = readrtc(RTC_MONTH); 955 for (m = 1; m < month; m++) 956 days += daysinmonth[m-1]; 957 if ((month > 2) && LEAPYEAR(year)) 958 days ++; 959 days += readrtc(RTC_DAY) - 1; 960 yd = days; 961 for (y = 1970; y < year; y++) 962 days += DAYSPERYEAR + LEAPYEAR(y); 963 sec = ((( days * 24 + 964 readrtc(RTC_HRS)) * 60 + 965 readrtc(RTC_MIN)) * 60 + 966 readrtc(RTC_SEC)); 967 /* sec now contains the number of seconds, since Jan 1 1970, 968 in the local time zone */ 969#endif 970 971 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 972 973 s = splclock(); 974 time.tv_sec = sec; 975 splx(s); 976 return; 977 978wrong_time: 979 printf("Invalid time in real time clock.\n"); 980 printf("Check and reset the date immediately!\n"); 981} 982 983/* 984 * Write system time back to RTC 985 */ 986void 987resettodr() 988{ 989 unsigned long tm; 990 int y, m, s; 991#ifdef PC98 992 int wd; 993#endif 994 995 if (disable_rtc_set) 996 return; 997 998 s = splclock(); 999 tm = time.tv_sec; 1000 splx(s); 1001 1002#ifdef PC98 1003 rtc_serialcom(0x01); /* Register shift command. */ 1004 1005 /* Calculate local time to put in RTC */ 1006 1007 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1008 1009 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1010 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1011 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1012 1013 /* We have now the days since 01-01-1970 in tm */ 1014 wd = (tm+4)%7; 1015 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1016 tm >= m; 1017 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1018 tm -= m; 1019 1020 /* Now we have the years in y and the day-of-the-year in tm */ 1021 for (m = 0; ; m++) { 1022 int ml; 1023 1024 ml = daysinmonth[m]; 1025 if (m == 1 && LEAPYEAR(y)) 1026 ml++; 1027 if (tm < ml) 1028 break; 1029 tm -= ml; 1030 } 1031 1032 m++; 1033 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1034 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1035 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1036 1037 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1038 rtc_serialcom(0x00); /* Register hold command. */ 1039#else 1040 /* Disable RTC updates and interrupts. */ 1041 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1042 1043 /* Calculate local time to put in RTC */ 1044 1045 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1046 1047 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1048 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1049 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1050 1051 /* We have now the days since 01-01-1970 in tm */ 1052 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1053 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1054 tm >= m; 1055 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1056 tm -= m; 1057 1058 /* Now we have the years in y and the day-of-the-year in tm */ 1059 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1060#ifdef USE_RTC_CENTURY 1061 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1062#endif 1063 for (m = 0; ; m++) { 1064 int ml; 1065 1066 ml = daysinmonth[m]; 1067 if (m == 1 && LEAPYEAR(y)) 1068 ml++; 1069 if (tm < ml) 1070 break; 1071 tm -= ml; 1072 } 1073 1074 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1075 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1076 1077 /* Reenable RTC updates and interrupts. */ 1078 writertc(RTC_STATUSB, rtc_statusb); 1079#endif 1080} 1081 1082/* 1083 * Start both clocks running. 1084 */ 1085void 1086cpu_initclocks() 1087{ 1088#ifndef PC98 1089 int diag; 1090 1091 if (statclock_disable) { 1092 /* 1093 * The stat interrupt mask is different without the 1094 * statistics clock. Also, don't set the interrupt 1095 * flag which would normally cause the RTC to generate 1096 * interrupts. 1097 */ 1098 stat_imask = HWI_MASK | SWI_MASK; 1099 rtc_statusb = RTCSB_24HR; 1100 } else { 1101 /* Setting stathz to nonzero early helps avoid races. */ 1102 stathz = RTC_NOPROFRATE; 1103 profhz = RTC_PROFRATE; 1104 } 1105#endif 1106 1107 /* Finish initializing 8253 timer 0. */ 1108 register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, 1109 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1110 /* unit */ 0); 1111 INTREN(IRQ0); 1112#if defined(I586_CPU) || defined(I686_CPU) 1113 /* 1114 * Finish setting up anti-jitter measures. 1115 */ 1116 if (i586_ctr_freq != 0) { 1117 i586_last_tick = rdtsc(); 1118 i586_ctr_bias = i586_last_tick; 1119 } 1120#endif 1121 1122#ifndef PC98 1123 /* Initialize RTC. */ 1124 writertc(RTC_STATUSA, rtc_statusa); 1125 writertc(RTC_STATUSB, RTCSB_24HR); 1126 1127static int 1128sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1129{ 1130 int error; 1131 u_int freq; 1132 1133 /* 1134 * Use `i8254' instead of `timer' in external names because `timer' 1135 * is is too generic. Should use it everywhere. 1136 */ 1137 freq = timer_freq; 1138 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1139 if (error == 0 && req->newptr != NULL) { 1140 if (timer0_state != 0) 1141 return (EBUSY); /* too much trouble to handle */ 1142 set_timer_freq(freq, hz); 1143#if defined(I586_CPU) || defined(I686_CPU) 1144 set_i586_ctr_freq(i586_ctr_freq, timer_freq); 1145#endif 1146 } 1147 return (error); 1148} 1149 1150SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1151 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1152 1153#if defined(I586_CPU) || defined(I686_CPU) 1154static void 1155set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq) 1156{ 1157 u_int comultiplier, multiplier; 1158 u_long ef; 1159 1160 if (i586_freq == 0) { 1161 i586_ctr_freq = i586_freq; 1162 return; 1163 } 1164 comultiplier = ((unsigned long long)i586_freq 1165 << I586_CTR_COMULTIPLIER_SHIFT) / i8254_freq; 1166 multiplier = (1000000LL << I586_CTR_MULTIPLIER_SHIFT) / i586_freq; 1167 ef = read_eflags(); 1168 disable_intr(); 1169 i586_ctr_freq = i586_freq; 1170 i586_ctr_comultiplier = comultiplier; 1171 i586_ctr_multiplier = multiplier; 1172 write_eflags(ef); 1173} 1174 1175static int 1176sysctl_machdep_i586_freq SYSCTL_HANDLER_ARGS 1177{ 1178 int error; 1179 u_int freq; 1180 1181 if (cpu_class != CPUCLASS_586 && cpu_class != CPUCLASS_686) 1182 return (EOPNOTSUPP); 1183 freq = i586_ctr_freq; 1184 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1185 if (error == 0 && req->newptr != NULL) 1186 set_i586_ctr_freq(freq, timer_freq); 1187 return (error); 1188} 1189 1190SYSCTL_PROC(_machdep, OID_AUTO, i586_freq, CTLTYPE_INT | CTLFLAG_RW, 1191 0, sizeof(u_int), sysctl_machdep_i586_freq, "I", ""); 1192#endif /* defined(I586_CPU) || defined(I686_CPU) */ 1193 1194 /* Don't bother enabling the statistics clock. */ 1195 if (statclock_disable) 1196 return; 1197 diag = rtcin(RTC_DIAG); 1198 if (diag != 0) 1199 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1200 register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, 1201 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1202 /* unit */ 0); 1203 INTREN(IRQ8); 1204 writertc(RTC_STATUSB, rtc_statusb); 1205#endif 1206} 1207 1208void 1209setstatclockrate(int newhz) 1210{ 1211#ifndef PC98 1212 if (newhz == RTC_PROFRATE) 1213 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1214 else 1215 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1216 writertc(RTC_STATUSA, rtc_statusa); 1217#endif 1218} 1219