pcrtc.c revision 17947
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $Id: clock.c,v 1.2 1996/07/23 07:46:07 asami Exp $ 38 */ 39 40/* 41 * inittodr, settodr and support routines written 42 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 43 * 44 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 45 */ 46 47/* 48 * modified for PC98 49 * $Id: clock.c,v 1.2 1996/07/23 07:46:07 asami Exp $ 50 */ 51 52/* 53 * Primitive clock interrupt routines. 54 */ 55#include "opt_ddb.h" 56#include "opt_clock.h" 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/time.h> 61#include <sys/kernel.h> 62#include <sys/sysctl.h> 63 64#include <machine/clock.h> 65#ifdef CLK_CALIBRATION_LOOP 66#include <machine/cons.h> 67#endif 68#include <machine/cpu.h> 69#include <machine/frame.h> 70 71#ifdef PC98 72#include <sys/syslog.h> 73#include <pc98/pc98/icu.h> 74#include <pc98/pc98/pc98.h> 75#include <pc98/pc98/pc98_device.h> 76#include <pc98/pc98/timerreg.h> 77#else 78#include <i386/isa/icu.h> 79#include <i386/isa/isa.h> 80#include <i386/isa/isa_device.h> 81#include <i386/isa/rtc.h> 82#include <i386/isa/timerreg.h> 83#endif 84 85/* 86 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 87 * can use a simple formula for leap years. 88 */ 89#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 90#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 91 92#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 93 94/* 95 * Time in timer cycles that it takes for microtime() to disable interrupts 96 * and latch the count. microtime() currently uses "cli; outb ..." so it 97 * normally takes less than 2 timer cycles. Add a few for cache misses. 98 * Add a few more to allow for latency in bogus calls to microtime() with 99 * interrupts already disabled. 100 */ 101#define TIMER0_LATCH_COUNT 20 102 103/* 104 * Maximum frequency that we are willing to allow for timer0. Must be 105 * low enough to guarantee that the timer interrupt handler returns 106 * before the next timer interrupt. Must result in a lower TIMER_DIV 107 * value than TIMER0_LATCH_COUNT so that we don't have to worry about 108 * underflow in the calculation of timer0_overflow_threshold. 109 */ 110#define TIMER0_MAX_FREQ 20000 111 112int adjkerntz; /* local offset from GMT in seconds */ 113int disable_rtc_set; /* disable resettodr() if != 0 */ 114int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 115 116u_int idelayed; 117#if defined(I586_CPU) || defined(I686_CPU) 118u_int i586_ctr_bias; 119u_int i586_ctr_comultiplier; 120u_int i586_ctr_freq; 121u_int i586_ctr_multiplier; 122long long i586_last_tick; 123unsigned long i586_avg_tick; 124#endif 125int statclock_disable; 126u_int stat_imask = SWI_CLOCK_MASK; 127#ifdef TIMER_FREQ 128static u_int timer_freq = TIMER_FREQ; 129#else 130#ifdef PC98 131#ifndef AUTO_CLOCK 132#ifndef PC98_8M 133static u_int timer_freq = 2457600; 134#else /* !PC98_8M */ 135static u_int timer_freq = 1996800; 136#endif /* PC98_8M */ 137#else /* AUTO_CLOCK */ 138static u_int timer_freq = 2457600; 139#endif /* AUTO_CLOCK */ 140#else /* IBM-PC */ 141static u_int timer_freq = 1193182; 142#endif /* PC98 */ 143#endif 144int timer0_max_count; 145u_int timer0_overflow_threshold; 146u_int timer0_prescaler_count; 147 148static int beeping = 0; 149static u_int clk_imask = HWI_MASK | SWI_MASK; 150static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 151static u_int hardclock_max_count; 152/* 153 * XXX new_function and timer_func should not handle clockframes, but 154 * timer_func currently needs to hold hardclock to handle the 155 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 156 * to switch between clkintr() and a slightly different timerintr(). 157 */ 158static void (*new_function) __P((struct clockframe *frame)); 159static u_int new_rate; 160#ifndef PC98 161static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 162static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 163#endif 164 165/* Values for timerX_state: */ 166#define RELEASED 0 167#define RELEASE_PENDING 1 168#define ACQUIRED 2 169#define ACQUIRE_PENDING 3 170 171static u_char timer0_state; 172#ifdef PC98 173static u_char timer1_state; 174#endif 175static u_char timer2_state; 176static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 177int rtc_inb __P((void)); 178 179#if defined(I586_CPU) || defined(I686_CPU) 180static void set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq); 181#endif 182 183static void 184clkintr(struct clockframe frame) 185{ 186 timer_func(&frame); 187 switch (timer0_state) { 188 189 case RELEASED: 190 setdelayed(); 191 break; 192 193 case ACQUIRED: 194 if ((timer0_prescaler_count += timer0_max_count) 195 >= hardclock_max_count) { 196 hardclock(&frame); 197 setdelayed(); 198 timer0_prescaler_count -= hardclock_max_count; 199 } 200 break; 201 202 case ACQUIRE_PENDING: 203 setdelayed(); 204 timer0_max_count = TIMER_DIV(new_rate); 205 timer0_overflow_threshold = 206 timer0_max_count - TIMER0_LATCH_COUNT; 207 disable_intr(); 208 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 209 outb(TIMER_CNTR0, timer0_max_count & 0xff); 210 outb(TIMER_CNTR0, timer0_max_count >> 8); 211 enable_intr(); 212 timer0_prescaler_count = 0; 213 timer_func = new_function; 214 timer0_state = ACQUIRED; 215 break; 216 217 case RELEASE_PENDING: 218 if ((timer0_prescaler_count += timer0_max_count) 219 >= hardclock_max_count) { 220 hardclock(&frame); 221 setdelayed(); 222 timer0_max_count = hardclock_max_count; 223 timer0_overflow_threshold = 224 timer0_max_count - TIMER0_LATCH_COUNT; 225 disable_intr(); 226 outb(TIMER_MODE, 227 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 228 outb(TIMER_CNTR0, timer0_max_count & 0xff); 229 outb(TIMER_CNTR0, timer0_max_count >> 8); 230 enable_intr(); 231 /* 232 * See microtime.s for this magic. 233 */ 234#ifdef PC98 235#ifndef AUTO_CLOCK 236#ifndef PC98_8M 237 time.tv_usec += (6667 * 238 (timer0_prescaler_count - hardclock_max_count)) 239 >> 14; 240#else /* PC98_8M */ 241 time.tv_usec += (16411 * 242 (timer0_prescaler_count - hardclock_max_count)) 243 >> 15; 244#endif /* PC98_8M */ 245#else /* AUTO_CLOCK */ 246 if (pc98_machine_type & M_8M) { 247 /* PC98_8M */ 248 time.tv_usec += (16411 * 249 (timer0_prescaler_count - 250 hardclock_max_count)) >> 15; 251 } else { 252 time.tv_usec += (6667 * 253 (timer0_prescaler_count - 254 hardclock_max_count)) >> 14; 255 } 256#endif /* AUTO_CLOCK */ 257#else /* IBM-PC */ 258 time.tv_usec += (27465 * 259 (timer0_prescaler_count - hardclock_max_count)) 260 >> 15; 261#endif /* PC98 */ 262 if (time.tv_usec >= 1000000) 263 time.tv_usec -= 1000000; 264 timer0_prescaler_count = 0; 265 timer_func = hardclock; 266 timer0_state = RELEASED; 267 } 268 break; 269 } 270} 271 272/* 273 * The acquire and release functions must be called at ipl >= splclock(). 274 */ 275int 276acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 277{ 278 static int old_rate; 279 280 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 281 return (-1); 282 switch (timer0_state) { 283 284 case RELEASED: 285 timer0_state = ACQUIRE_PENDING; 286 break; 287 288 case RELEASE_PENDING: 289 if (rate != old_rate) 290 return (-1); 291 /* 292 * The timer has been released recently, but is being 293 * re-acquired before the release completed. In this 294 * case, we simply reclaim it as if it had not been 295 * released at all. 296 */ 297 timer0_state = ACQUIRED; 298 break; 299 300 default: 301 return (-1); /* busy */ 302 } 303 new_function = function; 304 old_rate = new_rate = rate; 305 return (0); 306} 307 308#ifdef PC98 309int 310acquire_timer1(int mode) 311{ 312 313 if (timer1_state != RELEASED) 314 return (-1); 315 timer1_state = ACQUIRED; 316 317 /* 318 * This access to the timer registers is as atomic as possible 319 * because it is a single instruction. We could do better if we 320 * knew the rate. Use of splclock() limits glitches to 10-100us, 321 * and this is probably good enough for timer2, so we aren't as 322 * careful with it as with timer0. 323 */ 324 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 325 326 return (0); 327} 328#endif 329 330int 331acquire_timer2(int mode) 332{ 333 334 if (timer2_state != RELEASED) 335 return (-1); 336 timer2_state = ACQUIRED; 337 338 /* 339 * This access to the timer registers is as atomic as possible 340 * because it is a single instruction. We could do better if we 341 * knew the rate. Use of splclock() limits glitches to 10-100us, 342 * and this is probably good enough for timer2, so we aren't as 343 * careful with it as with timer0. 344 */ 345 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 346 347 return (0); 348} 349 350int 351release_timer0() 352{ 353 switch (timer0_state) { 354 355 case ACQUIRED: 356 timer0_state = RELEASE_PENDING; 357 break; 358 359 case ACQUIRE_PENDING: 360 /* Nothing happened yet, release quickly. */ 361 timer0_state = RELEASED; 362 break; 363 364 default: 365 return (-1); 366 } 367 return (0); 368} 369 370#ifdef PC98 371int 372release_timer1() 373{ 374 375 if (timer1_state != ACQUIRED) 376 return (-1); 377 timer1_state = RELEASED; 378 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 379 return (0); 380} 381#endif 382 383int 384release_timer2() 385{ 386 387 if (timer2_state != ACQUIRED) 388 return (-1); 389 timer2_state = RELEASED; 390 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 391 return (0); 392} 393 394#ifndef PC98 395/* 396 * This routine receives statistical clock interrupts from the RTC. 397 * As explained above, these occur at 128 interrupts per second. 398 * When profiling, we receive interrupts at a rate of 1024 Hz. 399 * 400 * This does not actually add as much overhead as it sounds, because 401 * when the statistical clock is active, the hardclock driver no longer 402 * needs to keep (inaccurate) statistics on its own. This decouples 403 * statistics gathering from scheduling interrupts. 404 * 405 * The RTC chip requires that we read status register C (RTC_INTR) 406 * to acknowledge an interrupt, before it will generate the next one. 407 */ 408static void 409rtcintr(struct clockframe frame) 410{ 411 u_char stat; 412 stat = rtcin(RTC_INTR); 413 if(stat & RTCIR_PERIOD) { 414 statclock(&frame); 415 } 416} 417 418#ifdef DDB 419static void 420DDB_printrtc(void) 421{ 422 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 423 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 424 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 425 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 426} 427#endif 428#endif /* for PC98 */ 429 430static int 431getit(void) 432{ 433 u_long ef; 434 int high, low; 435 436 ef = read_eflags(); 437 disable_intr(); 438 439 /* Select timer0 and latch counter value. */ 440 outb(TIMER_MODE, TIMER_SEL0); 441 442 low = inb(TIMER_CNTR0); 443 high = inb(TIMER_CNTR0); 444 445 write_eflags(ef); 446 return ((high << 8) | low); 447} 448 449/* 450 * Wait "n" microseconds. 451 * Relies on timer 1 counting down from (timer_freq / hz) 452 * Note: timer had better have been programmed before this is first used! 453 */ 454void 455DELAY(int n) 456{ 457 int prev_tick, tick, ticks_left, sec, usec; 458 459#ifdef DELAYDEBUG 460 int getit_calls = 1; 461 int n1; 462 static int state = 0; 463 464 if (state == 0) { 465 state = 1; 466 for (n1 = 1; n1 <= 10000000; n1 *= 10) 467 DELAY(n1); 468 state = 2; 469 } 470 if (state == 1) 471 printf("DELAY(%d)...", n); 472#endif 473 /* 474 * Read the counter first, so that the rest of the setup overhead is 475 * counted. Guess the initial overhead is 20 usec (on most systems it 476 * takes about 1.5 usec for each of the i/o's in getit(). The loop 477 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 478 * multiplications and divisions to scale the count take a while). 479 */ 480 prev_tick = getit(); 481 n -= 20; 482 /* 483 * Calculate (n * (timer_freq / 1e6)) without using floating point 484 * Calculate (n * (TIMER_FREQ / 1e6)) without using floating point 485 * and without any avoidable overflows. 486 */ 487 sec = n / 1000000; 488 usec = n - sec * 1000000; 489 ticks_left = sec * timer_freq 490 + usec * (timer_freq / 1000000) 491 + usec * ((timer_freq % 1000000) / 1000) / 1000 492 + usec * (timer_freq % 1000) / 1000000; 493 if (n < 0) 494 ticks_left = 0; /* XXX timer_freq is unsigned */ 495 496 while (ticks_left > 0) { 497 tick = getit(); 498#ifdef DELAYDEBUG 499 ++getit_calls; 500#endif 501 if (tick > prev_tick) 502 ticks_left -= prev_tick - (tick - timer0_max_count); 503 else 504 ticks_left -= prev_tick - tick; 505 prev_tick = tick; 506 } 507#ifdef DELAYDEBUG 508 if (state == 1) 509 printf(" %d calls to getit() at %d usec each\n", 510 getit_calls, (n + 5) / getit_calls); 511#endif 512} 513 514static void 515sysbeepstop(void *chan) 516{ 517#ifdef PC98 /* PC98 */ 518 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 519 release_timer1(); 520#else 521 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 522 release_timer2(); 523#endif 524 beeping = 0; 525} 526 527int 528sysbeep(int pitch, int period) 529{ 530 int x = splclock(); 531 532#ifdef PC98 533 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 534 if (!beeping) { 535 /* Something else owns it. */ 536 splx(x); 537 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 538 } 539 disable_intr(); 540 outb(0x3fdb, pitch); 541 outb(0x3fdb, (pitch>>8)); 542 enable_intr(); 543 if (!beeping) { 544 /* enable counter1 output to speaker */ 545 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 546 beeping = period; 547 timeout(sysbeepstop, (void *)NULL, period); 548 } 549#else 550 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 551 if (!beeping) { 552 /* Something else owns it. */ 553 splx(x); 554 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 555 } 556 disable_intr(); 557 outb(TIMER_CNTR2, pitch); 558 outb(TIMER_CNTR2, (pitch>>8)); 559 enable_intr(); 560 if (!beeping) { 561 /* enable counter2 output to speaker */ 562 outb(IO_PPI, inb(IO_PPI) | 3); 563 beeping = period; 564 timeout(sysbeepstop, (void *)NULL, period); 565 } 566#endif 567 splx(x); 568 return (0); 569} 570 571#ifndef PC98 572/* 573 * RTC support routines 574 */ 575 576int 577rtcin(reg) 578 int reg; 579{ 580 u_char val; 581 582 outb(IO_RTC, reg); 583 inb(0x84); 584 val = inb(IO_RTC + 1); 585 inb(0x84); 586 return (val); 587} 588 589static __inline void 590writertc(u_char reg, u_char val) 591{ 592 outb(IO_RTC, reg); 593 outb(IO_RTC + 1, val); 594} 595 596static __inline int 597readrtc(int port) 598{ 599 return(bcd2bin(rtcin(port))); 600} 601#endif 602 603#ifdef PC98 604unsigned int delaycount; 605#define FIRST_GUESS 0x2000 606static void findcpuspeed(void) 607{ 608 int i; 609 int remainder; 610 611 /* Put counter in count down mode */ 612 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 613 outb(TIMER_CNTR0, 0xff); 614 outb(TIMER_CNTR0, 0xff); 615 for (i = FIRST_GUESS; i; i--) 616 ; 617 remainder = getit(); 618 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 619} 620#endif 621 622#ifndef PC98 623static u_int 624calibrate_clocks(void) 625{ 626 u_int count, prev_count, tot_count; 627 int sec, start_sec, timeout; 628 629 printf("Calibrating clock(s) relative to mc146818A clock...\n"); 630 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 631 goto fail; 632 timeout = 100000000; 633 634 /* Read the mc146818A seconds counter. */ 635 for (;;) { 636 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 637 sec = rtcin(RTC_SEC); 638 break; 639 } 640 if (--timeout == 0) 641 goto fail; 642 } 643 644 /* Wait for the mC146818A seconds counter to change. */ 645 start_sec = sec; 646 for (;;) { 647 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 648 sec = rtcin(RTC_SEC); 649 if (sec != start_sec) 650 break; 651 } 652 if (--timeout == 0) 653 goto fail; 654 } 655 656 /* Start keeping track of the i8254 counter. */ 657 prev_count = getit(); 658 if (prev_count == 0 || prev_count > timer0_max_count) 659 goto fail; 660 tot_count = 0; 661 662#if defined(I586_CPU) || defined(I686_CPU) 663 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) 664 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 665#endif 666 667 /* 668 * Wait for the mc146818A seconds counter to change. Read the i8254 669 * counter for each iteration since this is convenient and only 670 * costs a few usec of inaccuracy. The timing of the final reads 671 * of the counters almost matches the timing of the initial reads, 672 * so the main cause of inaccuracy is the varying latency from 673 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 674 * rtcin(RTC_SEC) that returns a changed seconds count. The 675 * maximum inaccuracy from this cause is < 10 usec on 486's. 676 */ 677 start_sec = sec; 678 for (;;) { 679 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 680 sec = rtcin(RTC_SEC); 681 count = getit(); 682 if (count == 0 || count > timer0_max_count) 683 goto fail; 684 if (count > prev_count) 685 tot_count += prev_count - (count - timer0_max_count); 686 else 687 tot_count += prev_count - count; 688 prev_count = count; 689 if (sec != start_sec) 690 break; 691 if (--timeout == 0) 692 goto fail; 693 } 694 695#if defined(I586_CPU) || defined(I686_CPU) 696 /* 697 * Read the cpu cycle counter. The timing considerations are 698 * similar to those for the i8254 clock. 699 */ 700 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) { 701 set_i586_ctr_freq((u_int)rdtsc(), tot_count); 702 printf("i586 clock: %u Hz, ", i586_ctr_freq); 703 } 704#endif 705 706 printf("i8254 clock: %u Hz\n", tot_count); 707 return (tot_count); 708 709fail: 710 printf("failed, using default i8254 clock of %u Hz\n", timer_freq); 711 return (timer_freq); 712} 713#endif /* !PC98 */ 714 715static void 716set_timer_freq(u_int freq, int intr_freq) 717{ 718 u_long ef; 719 720 ef = read_eflags(); 721 disable_intr(); 722 timer_freq = freq; 723 timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 724 timer0_overflow_threshold = timer0_max_count - TIMER0_LATCH_COUNT; 725 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 726 outb(TIMER_CNTR0, timer0_max_count & 0xff); 727 outb(TIMER_CNTR0, timer0_max_count >> 8); 728 write_eflags(ef); 729} 730 731/* 732 * Initialize 8253 timer 0 early so that it can be used in DELAY(). 733 * XXX initialization of other timers is unintentionally left blank. 734 */ 735void 736startrtclock() 737{ 738 u_int delta, freq; 739 740#ifdef PC98 741 findcpuspeed(); 742#ifndef AUTO_CLOCK 743 if (pc98_machine_type & M_8M) { 744#ifndef PC98_8M 745 log(LOG_EMERG, 746 "you must reconfig a kernel with \"PC98_8M\" option.\n"); 747#endif 748 } else { 749#ifdef PC98_8M 750 log(LOG_EMERG, 751 "You must reconfig a kernel without \"PC98_8M\" option.\n"); 752#endif 753 } 754#else /* AUTO_CLOCK */ 755 if (pc98_machine_type & M_8M) 756 timer_freq = 1996800L; /* 1.9968 MHz */ 757 else 758 timer_freq = 2457600L; /* 2.4576 MHz */ 759#endif /* AUTO_CLOCK */ 760#endif /* PC98 */ 761 762#ifndef PC98 763 writertc(RTC_STATUSA, rtc_statusa); 764 writertc(RTC_STATUSB, RTCSB_24HR); 765#endif 766 767#ifndef PC98 768 set_timer_freq(timer_freq, hz); 769 freq = calibrate_clocks(); 770#ifdef CLK_CALIBRATION_LOOP 771 if (bootverbose) { 772 printf( 773 "Press a key on the console to abort clock calibration\n"); 774 while (!cncheckc()) 775 calibrate_clocks(); 776 } 777#endif 778 779 /* 780 * Use the calibrated i8254 frequency if it seems reasonable. 781 * Otherwise use the default, and don't use the calibrated i586 782 * frequency. 783 */ 784 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 785 if (delta < timer_freq / 100) { 786#ifndef CLK_USE_I8254_CALIBRATION 787 if (bootverbose) 788 printf( 789"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 790 freq = timer_freq; 791#endif 792 timer_freq = freq; 793 } else { 794 printf("%d Hz differs from default of %d Hz by more than 1%%\n", 795 freq, timer_freq); 796#if defined(I586_CPU) || defined(I686_CPU) 797 i586_ctr_freq = 0; 798#endif 799 } 800#endif 801 802 set_timer_freq(timer_freq, hz); 803 804#if defined(I586_CPU) || defined(I686_CPU) 805#ifndef CLK_USE_I586_CALIBRATION 806 if (i586_ctr_freq != 0) { 807 if (bootverbose) 808 printf( 809"CLK_USE_I586_CALIBRATION not specified - using old calibration method\n"); 810 i586_ctr_freq = 0; 811 } 812#endif 813 if (i586_ctr_freq == 0 && 814 (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686)) { 815 /* 816 * Calibration of the i586 clock relative to the mc146818A 817 * clock failed. Do a less accurate calibration relative 818 * to the i8254 clock. 819 */ 820 wrmsr(0x10, 0LL); /* XXX */ 821 DELAY(1000000); 822 set_i586_ctr_freq((u_int)rdtsc(), timer_freq); 823#ifdef CLK_USE_I586_CALIBRATION 824 printf("i586 clock: %u Hz\n", i586_ctr_freq); 825#endif 826 } 827#endif 828} 829 830#ifdef PC98 831void 832rtc_serialcombit(int i) 833{ 834 outb(IO_RTC, ((i&0x01)<<5)|0x07); 835 DELAY(1); 836 outb(IO_RTC, ((i&0x01)<<5)|0x17); 837 DELAY(1); 838 outb(IO_RTC, ((i&0x01)<<5)|0x07); 839 DELAY(1); 840} 841 842void 843rtc_serialcom(int i) 844{ 845 rtc_serialcombit(i&0x01); 846 rtc_serialcombit((i&0x02)>>1); 847 rtc_serialcombit((i&0x04)>>2); 848 rtc_serialcombit((i&0x08)>>3); 849 outb(IO_RTC, 0x07); 850 DELAY(1); 851 outb(IO_RTC, 0x0f); 852 DELAY(1); 853 outb(IO_RTC, 0x07); 854 DELAY(1); 855} 856 857void 858rtc_outb(int val) 859{ 860 int s; 861 int sa = 0; 862 863 for (s=0;s<8;s++) { 864 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 865 outb(IO_RTC, sa); /* set DI & CLK 0 */ 866 DELAY(1); 867 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 868 DELAY(1); 869 } 870 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 871} 872 873int 874rtc_inb(void) 875{ 876 int s; 877 int sa = 0; 878 879 for (s=0;s<8;s++) { 880 sa |= ((inb(0x33) & 0x01) << s); 881 outb(IO_RTC, 0x17); /* CLK 1 */ 882 DELAY(1); 883 outb(IO_RTC, 0x07); /* CLK 0 */ 884 DELAY(2); 885 } 886 return sa; 887} 888#endif /* PC-98 */ 889 890/* 891 * Initialize the time of day register, based on the time base which is, e.g. 892 * from a filesystem. 893 */ 894void 895inittodr(time_t base) 896{ 897 unsigned long sec, days; 898 int yd; 899 int year, month; 900 int y, m, s; 901#ifdef PC98 902 int second, min, hour; 903#endif 904 905 s = splclock(); 906 time.tv_sec = base; 907 time.tv_usec = 0; 908 splx(s); 909 910#ifdef PC98 911 rtc_serialcom(0x03); /* Time Read */ 912 rtc_serialcom(0x01); /* Register shift command. */ 913 DELAY(20); 914 915 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 916 min = bcd2bin(rtc_inb() & 0xff); /* min */ 917 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 918 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 919 920 month = (rtc_inb() >> 4) & 0x0f; /* month */ 921 for (m = 1; m < month; m++) 922 days += daysinmonth[m-1]; 923 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 924 /* 2000 year problem */ 925 if (year < 1995) 926 year += 100; 927 if (year < 1970) 928 goto wrong_time; 929 for (y = 1970; y < year; y++) 930 days += DAYSPERYEAR + LEAPYEAR(y); 931 if ((month > 2) && LEAPYEAR(year)) 932 days ++; 933 sec = ((( days * 24 + 934 hour) * 60 + 935 min) * 60 + 936 second); 937 /* sec now contains the number of seconds, since Jan 1 1970, 938 in the local time zone */ 939#else /* IBM-PC */ 940 /* Look if we have a RTC present and the time is valid */ 941 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 942 goto wrong_time; 943 944 /* wait for time update to complete */ 945 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 946 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 947 948 days = 0; 949#ifdef USE_RTC_CENTURY 950 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 951#else 952 year = readrtc(RTC_YEAR) + 1900; 953 if (year < 1970) 954 year += 100; 955#endif 956 if (year < 1970) 957 goto wrong_time; 958 month = readrtc(RTC_MONTH); 959 for (m = 1; m < month; m++) 960 days += daysinmonth[m-1]; 961 if ((month > 2) && LEAPYEAR(year)) 962 days ++; 963 days += readrtc(RTC_DAY) - 1; 964 yd = days; 965 for (y = 1970; y < year; y++) 966 days += DAYSPERYEAR + LEAPYEAR(y); 967 sec = ((( days * 24 + 968 readrtc(RTC_HRS)) * 60 + 969 readrtc(RTC_MIN)) * 60 + 970 readrtc(RTC_SEC)); 971 /* sec now contains the number of seconds, since Jan 1 1970, 972 in the local time zone */ 973#endif 974 975 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 976 977 s = splclock(); 978 time.tv_sec = sec; 979 splx(s); 980 return; 981 982wrong_time: 983 printf("Invalid time in real time clock.\n"); 984 printf("Check and reset the date immediately!\n"); 985} 986 987/* 988 * Write system time back to RTC 989 */ 990void 991resettodr() 992{ 993 unsigned long tm; 994 int y, m, s; 995#ifdef PC98 996 int wd; 997#endif 998 999 if (disable_rtc_set) 1000 return; 1001 1002 s = splclock(); 1003 tm = time.tv_sec; 1004 splx(s); 1005 1006#ifdef PC98 1007 rtc_serialcom(0x01); /* Register shift command. */ 1008 1009 /* Calculate local time to put in RTC */ 1010 1011 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1012 1013 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1014 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1015 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1016 1017 /* We have now the days since 01-01-1970 in tm */ 1018 wd = (tm+4)%7; 1019 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1020 tm >= m; 1021 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1022 tm -= m; 1023 1024 /* Now we have the years in y and the day-of-the-year in tm */ 1025 for (m = 0; ; m++) { 1026 int ml; 1027 1028 ml = daysinmonth[m]; 1029 if (m == 1 && LEAPYEAR(y)) 1030 ml++; 1031 if (tm < ml) 1032 break; 1033 tm -= ml; 1034 } 1035 1036 m++; 1037 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1038 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1039 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1040 1041 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1042 rtc_serialcom(0x00); /* Register hold command. */ 1043#else 1044 /* Disable RTC updates and interrupts. */ 1045 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1046 1047 /* Calculate local time to put in RTC */ 1048 1049 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1050 1051 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1052 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1053 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1054 1055 /* We have now the days since 01-01-1970 in tm */ 1056 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1057 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1058 tm >= m; 1059 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1060 tm -= m; 1061 1062 /* Now we have the years in y and the day-of-the-year in tm */ 1063 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1064#ifdef USE_RTC_CENTURY 1065 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1066#endif 1067 for (m = 0; ; m++) { 1068 int ml; 1069 1070 ml = daysinmonth[m]; 1071 if (m == 1 && LEAPYEAR(y)) 1072 ml++; 1073 if (tm < ml) 1074 break; 1075 tm -= ml; 1076 } 1077 1078 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1079 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1080 1081 /* Reenable RTC updates and interrupts. */ 1082 writertc(RTC_STATUSB, rtc_statusb); 1083#endif 1084} 1085 1086/* 1087 * Start both clocks running. 1088 */ 1089void 1090cpu_initclocks() 1091{ 1092#ifndef PC98 1093 int diag; 1094 1095 if (statclock_disable) { 1096 /* 1097 * The stat interrupt mask is different without the 1098 * statistics clock. Also, don't set the interrupt 1099 * flag which would normally cause the RTC to generate 1100 * interrupts. 1101 */ 1102 stat_imask = HWI_MASK | SWI_MASK; 1103 rtc_statusb = RTCSB_24HR; 1104 } else { 1105 /* Setting stathz to nonzero early helps avoid races. */ 1106 stathz = RTC_NOPROFRATE; 1107 profhz = RTC_PROFRATE; 1108 } 1109#endif 1110 1111 /* Finish initializing 8253 timer 0. */ 1112 register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, 1113 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1114 /* unit */ 0); 1115 INTREN(IRQ0); 1116#if defined(I586_CPU) || defined(I686_CPU) 1117 /* 1118 * Finish setting up anti-jitter measures. 1119 */ 1120 if (i586_ctr_freq != 0) { 1121 i586_last_tick = rdtsc(); 1122 i586_ctr_bias = i586_last_tick; 1123 } 1124#endif 1125 1126#ifndef PC98 1127 /* Initialize RTC. */ 1128 writertc(RTC_STATUSA, rtc_statusa); 1129 writertc(RTC_STATUSB, RTCSB_24HR); 1130 1131static int 1132sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1133{ 1134 int error; 1135 u_int freq; 1136 1137 /* 1138 * Use `i8254' instead of `timer' in external names because `timer' 1139 * is is too generic. Should use it everywhere. 1140 */ 1141 freq = timer_freq; 1142 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1143 if (error == 0 && req->newptr != NULL) { 1144 if (timer0_state != 0) 1145 return (EBUSY); /* too much trouble to handle */ 1146 set_timer_freq(freq, hz); 1147#if defined(I586_CPU) || defined(I686_CPU) 1148 set_i586_ctr_freq(i586_ctr_freq, timer_freq); 1149#endif 1150 } 1151 return (error); 1152} 1153 1154SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1155 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1156 1157#if defined(I586_CPU) || defined(I686_CPU) 1158static void 1159set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq) 1160{ 1161 u_int comultiplier, multiplier; 1162 u_long ef; 1163 1164 if (i586_freq == 0) { 1165 i586_ctr_freq = i586_freq; 1166 return; 1167 } 1168 comultiplier = ((unsigned long long)i586_freq 1169 << I586_CTR_COMULTIPLIER_SHIFT) / i8254_freq; 1170 multiplier = (1000000LL << I586_CTR_MULTIPLIER_SHIFT) / i586_freq; 1171 ef = read_eflags(); 1172 disable_intr(); 1173 i586_ctr_freq = i586_freq; 1174 i586_ctr_comultiplier = comultiplier; 1175 i586_ctr_multiplier = multiplier; 1176 write_eflags(ef); 1177} 1178 1179static int 1180sysctl_machdep_i586_freq SYSCTL_HANDLER_ARGS 1181{ 1182 int error; 1183 u_int freq; 1184 1185 if (cpu_class != CPUCLASS_586 && cpu_class != CPUCLASS_686) 1186 return (EOPNOTSUPP); 1187 freq = i586_ctr_freq; 1188 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1189 if (error == 0 && req->newptr != NULL) 1190 set_i586_ctr_freq(freq, timer_freq); 1191 return (error); 1192} 1193 1194SYSCTL_PROC(_machdep, OID_AUTO, i586_freq, CTLTYPE_INT | CTLFLAG_RW, 1195 0, sizeof(u_int), sysctl_machdep_i586_freq, "I", ""); 1196#endif /* defined(I586_CPU) || defined(I686_CPU) */ 1197 1198 /* Don't bother enabling the statistics clock. */ 1199 if (statclock_disable) 1200 return; 1201 diag = rtcin(RTC_DIAG); 1202 if (diag != 0) 1203 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1204 register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, 1205 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1206 /* unit */ 0); 1207 INTREN(IRQ8); 1208 writertc(RTC_STATUSB, rtc_statusb); 1209#endif 1210} 1211 1212void 1213setstatclockrate(int newhz) 1214{ 1215#ifndef PC98 1216 if (newhz == RTC_PROFRATE) 1217 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1218 else 1219 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1220 writertc(RTC_STATUSA, rtc_statusa); 1221#endif 1222} 1223