pcrtc.c revision 110371
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $FreeBSD: head/sys/pc98/cbus/pcrtc.c 110371 2003-02-05 09:33:57Z phk $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51/* 52 * modified for PC98 by Kakefuda 53 */ 54 55#include "opt_clock.h" 56#include "opt_isa.h" 57#include "opt_mca.h" 58 59#include <sys/param.h> 60#include <sys/stdint.h> 61#include <sys/systm.h> 62#include <sys/bus.h> 63#include <sys/lock.h> 64#include <sys/mutex.h> 65#include <sys/proc.h> 66#include <sys/time.h> 67#include <sys/timetc.h> 68#include <sys/kernel.h> 69#include <sys/sysctl.h> 70#include <sys/cons.h> 71#include <sys/power.h> 72 73#include <machine/clock.h> 74#include <machine/cputypes.h> 75#include <machine/frame.h> 76#include <machine/limits.h> 77#include <machine/md_var.h> 78#include <machine/psl.h> 79#ifdef APIC_IO 80#include <machine/segments.h> 81#endif 82#if defined(SMP) || defined(APIC_IO) 83#include <machine/smp.h> 84#endif /* SMP || APIC_IO */ 85#include <machine/specialreg.h> 86 87#include <i386/isa/icu.h> 88#ifdef PC98 89#include <pc98/pc98/pc98.h> 90#include <pc98/pc98/pc98_machdep.h> 91#include <i386/isa/isa_device.h> 92#else 93#include <i386/isa/isa.h> 94#include <isa/rtc.h> 95#endif 96#ifdef DEV_ISA 97#include <isa/isavar.h> 98#endif 99#include <i386/isa/timerreg.h> 100 101#include <i386/isa/intr_machdep.h> 102 103#ifdef DEV_MCA 104#include <i386/isa/mca_machdep.h> 105#endif 106 107#ifdef APIC_IO 108#include <i386/isa/intr_machdep.h> 109/* The interrupt triggered by the 8254 (timer) chip */ 110int apic_8254_intr; 111static u_long read_intr_count(int vec); 112static void setup_8254_mixed_mode(void); 113#endif 114 115/* 116 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 117 * can use a simple formula for leap years. 118 */ 119#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 120#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 121 122#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 123 124/* 125 * Time in timer cycles that it takes for microtime() to disable interrupts 126 * and latch the count. microtime() currently uses "cli; outb ..." so it 127 * normally takes less than 2 timer cycles. Add a few for cache misses. 128 * Add a few more to allow for latency in bogus calls to microtime() with 129 * interrupts already disabled. 130 */ 131#define TIMER0_LATCH_COUNT 20 132 133/* 134 * Maximum frequency that we are willing to allow for timer0. Must be 135 * low enough to guarantee that the timer interrupt handler returns 136 * before the next timer interrupt. 137 */ 138#define TIMER0_MAX_FREQ 20000 139 140int adjkerntz; /* local offset from GMT in seconds */ 141int clkintr_pending; 142int disable_rtc_set; /* disable resettodr() if != 0 */ 143int pscnt = 1; 144int psdiv = 1; 145int statclock_disable; 146#ifndef TIMER_FREQ 147#ifdef PC98 148#define TIMER_FREQ 2457600 149#else /* IBM-PC */ 150#define TIMER_FREQ 1193182 151#endif /* PC98 */ 152#endif 153u_int timer_freq = TIMER_FREQ; 154int timer0_max_count; 155uint64_t tsc_freq; 156int tsc_is_broken; 157u_int tsc_present; 158int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 159struct mtx clock_lock; 160 161static int beeping = 0; 162static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 163static u_int hardclock_max_count; 164static u_int32_t i8254_lastcount; 165static u_int32_t i8254_offset; 166static int i8254_ticked; 167/* 168 * XXX new_function and timer_func should not handle clockframes, but 169 * timer_func currently needs to hold hardclock to handle the 170 * timer0_state == 0 case. We should use inthand_add()/inthand_remove() 171 * to switch between clkintr() and a slightly different timerintr(). 172 */ 173static void (*new_function)(struct clockframe *frame); 174static u_int new_rate; 175#ifndef PC98 176static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 177static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 178#endif 179static u_int timer0_prescaler_count; 180 181/* Values for timerX_state: */ 182#define RELEASED 0 183#define RELEASE_PENDING 1 184#define ACQUIRED 2 185#define ACQUIRE_PENDING 3 186 187static u_char timer0_state; 188#ifdef PC98 189static u_char timer1_state; 190#endif 191static u_char timer2_state; 192static void (*timer_func)(struct clockframe *frame) = hardclock; 193#ifdef PC98 194static void rtc_serialcombit(int); 195static void rtc_serialcom(int); 196static int rtc_inb(void); 197static void rtc_outb(int); 198#endif 199 200static unsigned i8254_get_timecount(struct timecounter *tc); 201static unsigned tsc_get_timecount(struct timecounter *tc); 202static void set_timer_freq(u_int freq, int intr_freq); 203 204static struct timecounter tsc_timecounter = { 205 tsc_get_timecount, /* get_timecount */ 206 0, /* no poll_pps */ 207 ~0u, /* counter_mask */ 208 0, /* frequency */ 209 "TSC" /* name */ 210}; 211 212static struct timecounter i8254_timecounter = { 213 i8254_get_timecount, /* get_timecount */ 214 0, /* no poll_pps */ 215 ~0u, /* counter_mask */ 216 0, /* frequency */ 217 "i8254" /* name */ 218}; 219 220static void 221clkintr(struct clockframe frame) 222{ 223 224 if (timecounter->tc_get_timecount == i8254_get_timecount) { 225 mtx_lock_spin(&clock_lock); 226 if (i8254_ticked) 227 i8254_ticked = 0; 228 else { 229 i8254_offset += timer0_max_count; 230 i8254_lastcount = 0; 231 } 232 clkintr_pending = 0; 233 mtx_unlock_spin(&clock_lock); 234 } 235 timer_func(&frame); 236#ifdef SMP 237 if (timer_func == hardclock) 238 forward_hardclock(); 239#endif 240 switch (timer0_state) { 241 242 case RELEASED: 243 break; 244 245 case ACQUIRED: 246 if ((timer0_prescaler_count += timer0_max_count) 247 >= hardclock_max_count) { 248 timer0_prescaler_count -= hardclock_max_count; 249 hardclock(&frame); 250#ifdef SMP 251 forward_hardclock(); 252#endif 253 } 254 break; 255 256 case ACQUIRE_PENDING: 257 mtx_lock_spin(&clock_lock); 258 i8254_offset = i8254_get_timecount(NULL); 259 i8254_lastcount = 0; 260 timer0_max_count = TIMER_DIV(new_rate); 261 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 262 outb(TIMER_CNTR0, timer0_max_count & 0xff); 263 outb(TIMER_CNTR0, timer0_max_count >> 8); 264 mtx_unlock_spin(&clock_lock); 265 timer_func = new_function; 266 timer0_state = ACQUIRED; 267 break; 268 269 case RELEASE_PENDING: 270 if ((timer0_prescaler_count += timer0_max_count) 271 >= hardclock_max_count) { 272 mtx_lock_spin(&clock_lock); 273 i8254_offset = i8254_get_timecount(NULL); 274 i8254_lastcount = 0; 275 timer0_max_count = hardclock_max_count; 276 outb(TIMER_MODE, 277 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 278 outb(TIMER_CNTR0, timer0_max_count & 0xff); 279 outb(TIMER_CNTR0, timer0_max_count >> 8); 280 mtx_unlock_spin(&clock_lock); 281 timer0_prescaler_count = 0; 282 timer_func = hardclock; 283 timer0_state = RELEASED; 284 hardclock(&frame); 285#ifdef SMP 286 forward_hardclock(); 287#endif 288 } 289 break; 290 } 291#ifdef DEV_MCA 292 /* Reset clock interrupt by asserting bit 7 of port 0x61 */ 293 if (MCA_system) 294 outb(0x61, inb(0x61) | 0x80); 295#endif 296} 297 298/* 299 * The acquire and release functions must be called at ipl >= splclock(). 300 */ 301int 302acquire_timer0(int rate, void (*function)(struct clockframe *frame)) 303{ 304 static int old_rate; 305 306 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 307 return (-1); 308 switch (timer0_state) { 309 310 case RELEASED: 311 timer0_state = ACQUIRE_PENDING; 312 break; 313 314 case RELEASE_PENDING: 315 if (rate != old_rate) 316 return (-1); 317 /* 318 * The timer has been released recently, but is being 319 * re-acquired before the release completed. In this 320 * case, we simply reclaim it as if it had not been 321 * released at all. 322 */ 323 timer0_state = ACQUIRED; 324 break; 325 326 default: 327 return (-1); /* busy */ 328 } 329 new_function = function; 330 old_rate = new_rate = rate; 331 return (0); 332} 333 334#ifdef PC98 335int 336acquire_timer1(int mode) 337{ 338 339 if (timer1_state != RELEASED) 340 return (-1); 341 timer1_state = ACQUIRED; 342 343 /* 344 * This access to the timer registers is as atomic as possible 345 * because it is a single instruction. We could do better if we 346 * knew the rate. Use of splclock() limits glitches to 10-100us, 347 * and this is probably good enough for timer2, so we aren't as 348 * careful with it as with timer0. 349 */ 350 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 351 352 return (0); 353} 354#endif 355 356int 357acquire_timer2(int mode) 358{ 359 360 if (timer2_state != RELEASED) 361 return (-1); 362 timer2_state = ACQUIRED; 363 364 /* 365 * This access to the timer registers is as atomic as possible 366 * because it is a single instruction. We could do better if we 367 * knew the rate. Use of splclock() limits glitches to 10-100us, 368 * and this is probably good enough for timer2, so we aren't as 369 * careful with it as with timer0. 370 */ 371 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 372 373 return (0); 374} 375 376int 377release_timer0() 378{ 379 switch (timer0_state) { 380 381 case ACQUIRED: 382 timer0_state = RELEASE_PENDING; 383 break; 384 385 case ACQUIRE_PENDING: 386 /* Nothing happened yet, release quickly. */ 387 timer0_state = RELEASED; 388 break; 389 390 default: 391 return (-1); 392 } 393 return (0); 394} 395 396#ifdef PC98 397int 398release_timer1() 399{ 400 401 if (timer1_state != ACQUIRED) 402 return (-1); 403 timer1_state = RELEASED; 404 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 405 return (0); 406} 407#endif 408 409int 410release_timer2() 411{ 412 413 if (timer2_state != ACQUIRED) 414 return (-1); 415 timer2_state = RELEASED; 416 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 417 return (0); 418} 419 420#ifndef PC98 421/* 422 * This routine receives statistical clock interrupts from the RTC. 423 * As explained above, these occur at 128 interrupts per second. 424 * When profiling, we receive interrupts at a rate of 1024 Hz. 425 * 426 * This does not actually add as much overhead as it sounds, because 427 * when the statistical clock is active, the hardclock driver no longer 428 * needs to keep (inaccurate) statistics on its own. This decouples 429 * statistics gathering from scheduling interrupts. 430 * 431 * The RTC chip requires that we read status register C (RTC_INTR) 432 * to acknowledge an interrupt, before it will generate the next one. 433 * Under high interrupt load, rtcintr() can be indefinitely delayed and 434 * the clock can tick immediately after the read from RTC_INTR. In this 435 * case, the mc146818A interrupt signal will not drop for long enough 436 * to register with the 8259 PIC. If an interrupt is missed, the stat 437 * clock will halt, considerably degrading system performance. This is 438 * why we use 'while' rather than a more straightforward 'if' below. 439 * Stat clock ticks can still be lost, causing minor loss of accuracy 440 * in the statistics, but the stat clock will no longer stop. 441 */ 442static void 443rtcintr(struct clockframe frame) 444{ 445 while (rtcin(RTC_INTR) & RTCIR_PERIOD) { 446 if (profprocs != 0) { 447 if (--pscnt == 0) 448 pscnt = psdiv; 449 profclock(&frame); 450 } 451 if (pscnt == psdiv) 452 statclock(&frame); 453#ifdef SMP 454 forward_statclock(); 455#endif 456 } 457} 458 459#include "opt_ddb.h" 460#ifdef DDB 461#include <ddb/ddb.h> 462 463DB_SHOW_COMMAND(rtc, rtc) 464{ 465 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 466 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 467 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 468 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 469} 470#endif /* DDB */ 471#endif /* for PC98 */ 472 473static int 474getit(void) 475{ 476 int high, low; 477 478 mtx_lock_spin(&clock_lock); 479 480 /* Select timer0 and latch counter value. */ 481 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 482 483 low = inb(TIMER_CNTR0); 484 high = inb(TIMER_CNTR0); 485 486 mtx_unlock_spin(&clock_lock); 487 return ((high << 8) | low); 488} 489 490/* 491 * Wait "n" microseconds. 492 * Relies on timer 1 counting down from (timer_freq / hz) 493 * Note: timer had better have been programmed before this is first used! 494 */ 495void 496DELAY(int n) 497{ 498 int delta, prev_tick, tick, ticks_left; 499 500#ifdef DELAYDEBUG 501 int getit_calls = 1; 502 int n1; 503 static int state = 0; 504 505 if (state == 0) { 506 state = 1; 507 for (n1 = 1; n1 <= 10000000; n1 *= 10) 508 DELAY(n1); 509 state = 2; 510 } 511 if (state == 1) 512 printf("DELAY(%d)...", n); 513#endif 514 /* 515 * Guard against the timer being uninitialized if we are called 516 * early for console i/o. 517 */ 518 if (timer0_max_count == 0) 519 set_timer_freq(timer_freq, hz); 520 521 /* 522 * Read the counter first, so that the rest of the setup overhead is 523 * counted. Guess the initial overhead is 20 usec (on most systems it 524 * takes about 1.5 usec for each of the i/o's in getit(). The loop 525 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 526 * multiplications and divisions to scale the count take a while). 527 */ 528 prev_tick = getit(); 529 n -= 0; /* XXX actually guess no initial overhead */ 530 /* 531 * Calculate (n * (timer_freq / 1e6)) without using floating point 532 * and without any avoidable overflows. 533 */ 534 if (n <= 0) 535 ticks_left = 0; 536 else if (n < 256) 537 /* 538 * Use fixed point to avoid a slow division by 1000000. 539 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 540 * 2^15 is the first power of 2 that gives exact results 541 * for n between 0 and 256. 542 */ 543 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 544 else 545 /* 546 * Don't bother using fixed point, although gcc-2.7.2 547 * generates particularly poor code for the long long 548 * division, since even the slow way will complete long 549 * before the delay is up (unless we're interrupted). 550 */ 551 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 552 / 1000000; 553 554 while (ticks_left > 0) { 555 tick = getit(); 556#ifdef DELAYDEBUG 557 ++getit_calls; 558#endif 559 delta = prev_tick - tick; 560 prev_tick = tick; 561 if (delta < 0) { 562 delta += timer0_max_count; 563 /* 564 * Guard against timer0_max_count being wrong. 565 * This shouldn't happen in normal operation, 566 * but it may happen if set_timer_freq() is 567 * traced. 568 */ 569 if (delta < 0) 570 delta = 0; 571 } 572 ticks_left -= delta; 573 } 574#ifdef DELAYDEBUG 575 if (state == 1) 576 printf(" %d calls to getit() at %d usec each\n", 577 getit_calls, (n + 5) / getit_calls); 578#endif 579} 580 581static void 582sysbeepstop(void *chan) 583{ 584#ifdef PC98 /* PC98 */ 585 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 586 release_timer1(); 587#else 588 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 589 release_timer2(); 590#endif 591 beeping = 0; 592} 593 594int 595sysbeep(int pitch, int period) 596{ 597 int x = splclock(); 598 599#ifdef PC98 600 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 601 if (!beeping) { 602 /* Something else owns it. */ 603 splx(x); 604 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 605 } 606 disable_intr(); 607 outb(0x3fdb, pitch); 608 outb(0x3fdb, (pitch>>8)); 609 enable_intr(); 610 if (!beeping) { 611 /* enable counter1 output to speaker */ 612 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 613 beeping = period; 614 timeout(sysbeepstop, (void *)NULL, period); 615 } 616#else 617 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 618 if (!beeping) { 619 /* Something else owns it. */ 620 splx(x); 621 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 622 } 623 mtx_lock_spin(&clock_lock); 624 outb(TIMER_CNTR2, pitch); 625 outb(TIMER_CNTR2, (pitch>>8)); 626 mtx_unlock_spin(&clock_lock); 627 if (!beeping) { 628 /* enable counter2 output to speaker */ 629 outb(IO_PPI, inb(IO_PPI) | 3); 630 beeping = period; 631 timeout(sysbeepstop, (void *)NULL, period); 632 } 633#endif 634 splx(x); 635 return (0); 636} 637 638#ifndef PC98 639/* 640 * RTC support routines 641 */ 642 643int 644rtcin(reg) 645 int reg; 646{ 647 int s; 648 u_char val; 649 650 s = splhigh(); 651 outb(IO_RTC, reg); 652 inb(0x84); 653 val = inb(IO_RTC + 1); 654 inb(0x84); 655 splx(s); 656 return (val); 657} 658 659static __inline void 660writertc(u_char reg, u_char val) 661{ 662 int s; 663 664 s = splhigh(); 665 inb(0x84); 666 outb(IO_RTC, reg); 667 inb(0x84); 668 outb(IO_RTC + 1, val); 669 inb(0x84); /* XXX work around wrong order in rtcin() */ 670 splx(s); 671} 672 673static __inline int 674readrtc(int port) 675{ 676 return(bcd2bin(rtcin(port))); 677} 678#endif 679 680#ifdef PC98 681unsigned int delaycount; 682#define FIRST_GUESS 0x2000 683static void findcpuspeed(void) 684{ 685 int i; 686 int remainder; 687 688 /* Put counter in count down mode */ 689 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 690 outb(TIMER_CNTR0, 0xff); 691 outb(TIMER_CNTR0, 0xff); 692 for (i = FIRST_GUESS; i; i--) 693 ; 694 remainder = getit(); 695 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 696} 697#endif 698 699#ifdef PC98 700static u_int 701calibrate_clocks(void) 702{ 703 int timeout; 704 u_int count, prev_count, tot_count; 705 u_short sec, start_sec; 706 707 if (bootverbose) 708 printf("Calibrating clock(s) ... "); 709 /* Check ARTIC. */ 710 if (!(PC98_SYSTEM_PARAMETER(0x458) & 0x80) && 711 !(PC98_SYSTEM_PARAMETER(0x45b) & 0x04)) 712 goto fail; 713 timeout = 100000000; 714 715 /* Read the ARTIC. */ 716 sec = inw(0x5e); 717 718 /* Wait for the ARTIC to changes. */ 719 start_sec = sec; 720 for (;;) { 721 sec = inw(0x5e); 722 if (sec != start_sec) 723 break; 724 if (--timeout == 0) 725 goto fail; 726 } 727 prev_count = getit(); 728 if (prev_count == 0 || prev_count > timer0_max_count) 729 goto fail; 730 tot_count = 0; 731 732 if (tsc_present) 733 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 734 start_sec = sec; 735 for (;;) { 736 sec = inw(0x5e); 737 count = getit(); 738 if (count == 0 || count > timer0_max_count) 739 goto fail; 740 if (count > prev_count) 741 tot_count += prev_count - (count - timer0_max_count); 742 else 743 tot_count += prev_count - count; 744 prev_count = count; 745 if ((sec == start_sec + 1200) || 746 (sec < start_sec && 747 (u_int)sec + 0x10000 == (u_int)start_sec + 1200)) 748 break; 749 if (--timeout == 0) 750 goto fail; 751 } 752 /* 753 * Read the cpu cycle counter. The timing considerations are 754 * similar to those for the i8254 clock. 755 */ 756 if (tsc_present) 757 tsc_freq = rdtsc(); 758 759 if (bootverbose) { 760 if (tsc_present) 761 printf("TSC clock: %ju Hz, ", (intmax_t)tsc_freq); 762 printf("i8254 clock: %u Hz\n", tot_count); 763 } 764 return (tot_count); 765 766fail: 767 if (bootverbose) 768 printf("failed, using default i8254 clock of %u Hz\n", 769 timer_freq); 770 return (timer_freq); 771} 772#else 773static u_int 774calibrate_clocks(void) 775{ 776 u_int64_t old_tsc; 777 u_int count, prev_count, tot_count; 778 int sec, start_sec, timeout; 779 780 if (bootverbose) 781 printf("Calibrating clock(s) ... "); 782 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 783 goto fail; 784 timeout = 100000000; 785 786 /* Read the mc146818A seconds counter. */ 787 for (;;) { 788 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 789 sec = rtcin(RTC_SEC); 790 break; 791 } 792 if (--timeout == 0) 793 goto fail; 794 } 795 796 /* Wait for the mC146818A seconds counter to change. */ 797 start_sec = sec; 798 for (;;) { 799 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 800 sec = rtcin(RTC_SEC); 801 if (sec != start_sec) 802 break; 803 } 804 if (--timeout == 0) 805 goto fail; 806 } 807 808 /* Start keeping track of the i8254 counter. */ 809 prev_count = getit(); 810 if (prev_count == 0 || prev_count > timer0_max_count) 811 goto fail; 812 tot_count = 0; 813 814 if (tsc_present) 815 old_tsc = rdtsc(); 816 else 817 old_tsc = 0; /* shut up gcc */ 818 819 /* 820 * Wait for the mc146818A seconds counter to change. Read the i8254 821 * counter for each iteration since this is convenient and only 822 * costs a few usec of inaccuracy. The timing of the final reads 823 * of the counters almost matches the timing of the initial reads, 824 * so the main cause of inaccuracy is the varying latency from 825 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 826 * rtcin(RTC_SEC) that returns a changed seconds count. The 827 * maximum inaccuracy from this cause is < 10 usec on 486's. 828 */ 829 start_sec = sec; 830 for (;;) { 831 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 832 sec = rtcin(RTC_SEC); 833 count = getit(); 834 if (count == 0 || count > timer0_max_count) 835 goto fail; 836 if (count > prev_count) 837 tot_count += prev_count - (count - timer0_max_count); 838 else 839 tot_count += prev_count - count; 840 prev_count = count; 841 if (sec != start_sec) 842 break; 843 if (--timeout == 0) 844 goto fail; 845 } 846 847 /* 848 * Read the cpu cycle counter. The timing considerations are 849 * similar to those for the i8254 clock. 850 */ 851 if (tsc_present) 852 tsc_freq = rdtsc() - old_tsc; 853 854 if (bootverbose) { 855 if (tsc_present) 856 printf("TSC clock: %ju Hz, ", (intmax_t)tsc_freq); 857 printf("i8254 clock: %u Hz\n", tot_count); 858 } 859 return (tot_count); 860 861fail: 862 if (bootverbose) 863 printf("failed, using default i8254 clock of %u Hz\n", 864 timer_freq); 865 return (timer_freq); 866} 867#endif /* !PC98 */ 868 869static void 870set_timer_freq(u_int freq, int intr_freq) 871{ 872 int new_timer0_max_count; 873 874 mtx_lock_spin(&clock_lock); 875 timer_freq = freq; 876 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 877 if (new_timer0_max_count != timer0_max_count) { 878 timer0_max_count = new_timer0_max_count; 879 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 880 outb(TIMER_CNTR0, timer0_max_count & 0xff); 881 outb(TIMER_CNTR0, timer0_max_count >> 8); 882 } 883 mtx_unlock_spin(&clock_lock); 884} 885 886static void 887i8254_restore(void) 888{ 889 890 mtx_lock_spin(&clock_lock); 891 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 892 outb(TIMER_CNTR0, timer0_max_count & 0xff); 893 outb(TIMER_CNTR0, timer0_max_count >> 8); 894 mtx_unlock_spin(&clock_lock); 895} 896 897#ifndef PC98 898static void 899rtc_restore(void) 900{ 901 902 /* Restore all of the RTC's "status" (actually, control) registers. */ 903 /* XXX locking is needed for RTC access. */ 904 writertc(RTC_STATUSB, RTCSB_24HR); 905 writertc(RTC_STATUSA, rtc_statusa); 906 writertc(RTC_STATUSB, rtc_statusb); 907} 908#endif 909 910/* 911 * Restore all the timers non-atomically (XXX: should be atomically). 912 * 913 * This function is called from pmtimer_resume() to restore all the timers. 914 * This should not be necessary, but there are broken laptops that do not 915 * restore all the timers on resume. 916 */ 917void 918timer_restore(void) 919{ 920 921 i8254_restore(); /* restore timer_freq and hz */ 922#ifndef PC98 923 rtc_restore(); /* reenable RTC interrupts */ 924#endif 925} 926 927/* 928 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 929 * XXX initialization of other timers is unintentionally left blank. 930 */ 931void 932startrtclock() 933{ 934 u_int delta, freq; 935 936#ifdef PC98 937 findcpuspeed(); 938 if (pc98_machine_type & M_8M) 939 timer_freq = 1996800L; /* 1.9968 MHz */ 940 else 941 timer_freq = 2457600L; /* 2.4576 MHz */ 942#endif /* PC98 */ 943 944 if (cpu_feature & CPUID_TSC) 945 tsc_present = 1; 946 else 947 tsc_present = 0; 948 949#ifndef PC98 950 writertc(RTC_STATUSA, rtc_statusa); 951 writertc(RTC_STATUSB, RTCSB_24HR); 952#endif 953 954 set_timer_freq(timer_freq, hz); 955 freq = calibrate_clocks(); 956#ifdef CLK_CALIBRATION_LOOP 957 if (bootverbose) { 958 printf( 959 "Press a key on the console to abort clock calibration\n"); 960 while (cncheckc() == -1) 961 calibrate_clocks(); 962 } 963#endif 964 965 /* 966 * Use the calibrated i8254 frequency if it seems reasonable. 967 * Otherwise use the default, and don't use the calibrated i586 968 * frequency. 969 */ 970 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 971 if (delta < timer_freq / 100) { 972#ifndef CLK_USE_I8254_CALIBRATION 973 if (bootverbose) 974 printf( 975"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 976 freq = timer_freq; 977#endif 978 timer_freq = freq; 979 } else { 980 if (bootverbose) 981 printf( 982 "%d Hz differs from default of %d Hz by more than 1%%\n", 983 freq, timer_freq); 984 tsc_freq = 0; 985 } 986 987 set_timer_freq(timer_freq, hz); 988 i8254_timecounter.tc_frequency = timer_freq; 989 tc_init(&i8254_timecounter); 990 991#ifndef CLK_USE_TSC_CALIBRATION 992 if (tsc_freq != 0) { 993 if (bootverbose) 994 printf( 995"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 996 tsc_freq = 0; 997 } 998#endif 999 if (tsc_present && tsc_freq == 0) { 1000 /* 1001 * Calibration of the i586 clock relative to the mc146818A 1002 * clock failed. Do a less accurate calibration relative 1003 * to the i8254 clock. 1004 */ 1005 u_int64_t old_tsc = rdtsc(); 1006 1007 DELAY(1000000); 1008 tsc_freq = rdtsc() - old_tsc; 1009#ifdef CLK_USE_TSC_CALIBRATION 1010 if (bootverbose) 1011 printf("TSC clock: %ju Hz (Method B)\n", 1012 (intmax_t)tsc_freq); 1013#endif 1014 } 1015 1016#if !defined(SMP) 1017 /* 1018 * We can not use the TSC in SMP mode, until we figure out a 1019 * cheap (impossible), reliable and precise (yeah right!) way 1020 * to synchronize the TSCs of all the CPUs. 1021 * Curse Intel for leaving the counter out of the I/O APIC. 1022 */ 1023 1024 /* 1025 * We can not use the TSC if we support APM. Precise timekeeping 1026 * on an APM'ed machine is at best a fools pursuit, since 1027 * any and all of the time spent in various SMM code can't 1028 * be reliably accounted for. Reading the RTC is your only 1029 * source of reliable time info. The i8254 looses too of course 1030 * but we need to have some kind of time... 1031 * We don't know at this point whether APM is going to be used 1032 * or not, nor when it might be activated. Play it safe. 1033 */ 1034 if (power_pm_get_type() == POWER_PM_TYPE_APM) { 1035 if (bootverbose) 1036 printf("TSC initialization skipped: APM enabled.\n"); 1037 return; 1038 } 1039 1040 if (tsc_present && tsc_freq != 0 && !tsc_is_broken) { 1041 tsc_timecounter.tc_frequency = tsc_freq; 1042 tc_init(&tsc_timecounter); 1043 } 1044 1045#endif /* !defined(SMP) */ 1046} 1047 1048#ifdef PC98 1049static void 1050rtc_serialcombit(int i) 1051{ 1052 outb(IO_RTC, ((i&0x01)<<5)|0x07); 1053 DELAY(1); 1054 outb(IO_RTC, ((i&0x01)<<5)|0x17); 1055 DELAY(1); 1056 outb(IO_RTC, ((i&0x01)<<5)|0x07); 1057 DELAY(1); 1058} 1059 1060static void 1061rtc_serialcom(int i) 1062{ 1063 rtc_serialcombit(i&0x01); 1064 rtc_serialcombit((i&0x02)>>1); 1065 rtc_serialcombit((i&0x04)>>2); 1066 rtc_serialcombit((i&0x08)>>3); 1067 outb(IO_RTC, 0x07); 1068 DELAY(1); 1069 outb(IO_RTC, 0x0f); 1070 DELAY(1); 1071 outb(IO_RTC, 0x07); 1072 DELAY(1); 1073} 1074 1075static void 1076rtc_outb(int val) 1077{ 1078 int s; 1079 int sa = 0; 1080 1081 for (s=0;s<8;s++) { 1082 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 1083 outb(IO_RTC, sa); /* set DI & CLK 0 */ 1084 DELAY(1); 1085 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 1086 DELAY(1); 1087 } 1088 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 1089} 1090 1091static int 1092rtc_inb(void) 1093{ 1094 int s; 1095 int sa = 0; 1096 1097 for (s=0;s<8;s++) { 1098 sa |= ((inb(0x33) & 0x01) << s); 1099 outb(IO_RTC, 0x17); /* CLK 1 */ 1100 DELAY(1); 1101 outb(IO_RTC, 0x07); /* CLK 0 */ 1102 DELAY(2); 1103 } 1104 return sa; 1105} 1106#endif /* PC-98 */ 1107 1108/* 1109 * Initialize the time of day register, based on the time base which is, e.g. 1110 * from a filesystem. 1111 */ 1112void 1113inittodr(time_t base) 1114{ 1115 unsigned long sec, days; 1116 int year, month; 1117 int y, m, s; 1118 struct timespec ts; 1119#ifdef PC98 1120 int second, min, hour; 1121#endif 1122 1123 if (base) { 1124 s = splclock(); 1125 ts.tv_sec = base; 1126 ts.tv_nsec = 0; 1127 tc_setclock(&ts); 1128 splx(s); 1129 } 1130 1131#ifdef PC98 1132 rtc_serialcom(0x03); /* Time Read */ 1133 rtc_serialcom(0x01); /* Register shift command. */ 1134 DELAY(20); 1135 1136 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 1137 min = bcd2bin(rtc_inb() & 0xff); /* min */ 1138 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 1139 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 1140 1141 month = (rtc_inb() >> 4) & 0x0f; /* month */ 1142 for (m = 1; m < month; m++) 1143 days += daysinmonth[m-1]; 1144 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 1145 /* 2000 year problem */ 1146 if (year < 1995) 1147 year += 100; 1148 if (year < 1970) 1149 goto wrong_time; 1150 for (y = 1970; y < year; y++) 1151 days += DAYSPERYEAR + LEAPYEAR(y); 1152 if ((month > 2) && LEAPYEAR(year)) 1153 days ++; 1154 sec = ((( days * 24 + 1155 hour) * 60 + 1156 min) * 60 + 1157 second); 1158 /* sec now contains the number of seconds, since Jan 1 1970, 1159 in the local time zone */ 1160 1161 s = splhigh(); 1162#else /* IBM-PC */ 1163 /* Look if we have a RTC present and the time is valid */ 1164 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 1165 goto wrong_time; 1166 1167 /* wait for time update to complete */ 1168 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 1169 s = splhigh(); 1170 while (rtcin(RTC_STATUSA) & RTCSA_TUP) { 1171 splx(s); 1172 s = splhigh(); 1173 } 1174 1175 days = 0; 1176#ifdef USE_RTC_CENTURY 1177 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 1178#else 1179 year = readrtc(RTC_YEAR) + 1900; 1180 if (year < 1970) 1181 year += 100; 1182#endif 1183 if (year < 1970) { 1184 splx(s); 1185 goto wrong_time; 1186 } 1187 month = readrtc(RTC_MONTH); 1188 for (m = 1; m < month; m++) 1189 days += daysinmonth[m-1]; 1190 if ((month > 2) && LEAPYEAR(year)) 1191 days ++; 1192 days += readrtc(RTC_DAY) - 1; 1193 for (y = 1970; y < year; y++) 1194 days += DAYSPERYEAR + LEAPYEAR(y); 1195 sec = ((( days * 24 + 1196 readrtc(RTC_HRS)) * 60 + 1197 readrtc(RTC_MIN)) * 60 + 1198 readrtc(RTC_SEC)); 1199 /* sec now contains the number of seconds, since Jan 1 1970, 1200 in the local time zone */ 1201#endif 1202 1203 sec += tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1204 1205 y = time_second - sec; 1206 if (y <= -2 || y >= 2) { 1207 /* badly off, adjust it */ 1208 ts.tv_sec = sec; 1209 ts.tv_nsec = 0; 1210 tc_setclock(&ts); 1211 } 1212 splx(s); 1213 return; 1214 1215wrong_time: 1216 printf("Invalid time in real time clock.\n"); 1217 printf("Check and reset the date immediately!\n"); 1218} 1219 1220/* 1221 * Write system time back to RTC 1222 */ 1223void 1224resettodr() 1225{ 1226 unsigned long tm; 1227 int y, m, s; 1228#ifdef PC98 1229 int wd; 1230#endif 1231 1232 if (disable_rtc_set) 1233 return; 1234 1235 s = splclock(); 1236 tm = time_second; 1237 splx(s); 1238 1239#ifdef PC98 1240 rtc_serialcom(0x01); /* Register shift command. */ 1241 1242 /* Calculate local time to put in RTC */ 1243 1244 tm -= tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1245 1246 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1247 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1248 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1249 1250 /* We have now the days since 01-01-1970 in tm */ 1251 wd = (tm + 4) % 7 + 1); /* Write back Weekday */ 1252 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1253 tm >= m; 1254 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1255 tm -= m; 1256 1257 /* Now we have the years in y and the day-of-the-year in tm */ 1258 for (m = 0; ; m++) { 1259 int ml; 1260 1261 ml = daysinmonth[m]; 1262 if (m == 1 && LEAPYEAR(y)) 1263 ml++; 1264 if (tm < ml) 1265 break; 1266 tm -= ml; 1267 } 1268 1269 m++; 1270 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1271 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1272 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1273 1274 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1275 rtc_serialcom(0x00); /* Register hold command. */ 1276#else 1277 /* Disable RTC updates and interrupts. */ 1278 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1279 1280 /* Calculate local time to put in RTC */ 1281 1282 tm -= tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1283 1284 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1285 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1286 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1287 1288 /* We have now the days since 01-01-1970 in tm */ 1289 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1290 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1291 tm >= m; 1292 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1293 tm -= m; 1294 1295 /* Now we have the years in y and the day-of-the-year in tm */ 1296 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1297#ifdef USE_RTC_CENTURY 1298 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1299#endif 1300 for (m = 0; ; m++) { 1301 int ml; 1302 1303 ml = daysinmonth[m]; 1304 if (m == 1 && LEAPYEAR(y)) 1305 ml++; 1306 if (tm < ml) 1307 break; 1308 tm -= ml; 1309 } 1310 1311 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1312 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1313 1314 /* Reenable RTC updates and interrupts. */ 1315 writertc(RTC_STATUSB, rtc_statusb); 1316#endif /* PC98 */ 1317} 1318 1319 1320/* 1321 * Start both clocks running. 1322 */ 1323void 1324cpu_initclocks() 1325{ 1326#ifndef PC98 1327 int diag; 1328#endif 1329#ifdef APIC_IO 1330 int apic_8254_trial; 1331 void *clkdesc; 1332#endif /* APIC_IO */ 1333 register_t crit; 1334 1335#ifndef PC98 1336 if (statclock_disable) { 1337 /* 1338 * The stat interrupt mask is different without the 1339 * statistics clock. Also, don't set the interrupt 1340 * flag which would normally cause the RTC to generate 1341 * interrupts. 1342 */ 1343 rtc_statusb = RTCSB_24HR; 1344 } else { 1345 /* Setting stathz to nonzero early helps avoid races. */ 1346 stathz = RTC_NOPROFRATE; 1347 profhz = RTC_PROFRATE; 1348 } 1349#endif 1350 1351 /* Finish initializing 8253 timer 0. */ 1352#ifdef APIC_IO 1353 1354 apic_8254_intr = isa_apic_irq(0); 1355 apic_8254_trial = 0; 1356 if (apic_8254_intr >= 0 ) { 1357 if (apic_int_type(0, 0) == 3) 1358 apic_8254_trial = 1; 1359 } else { 1360 /* look for ExtInt on pin 0 */ 1361 if (apic_int_type(0, 0) == 3) { 1362 apic_8254_intr = apic_irq(0, 0); 1363 setup_8254_mixed_mode(); 1364 } else 1365 panic("APIC_IO: Cannot route 8254 interrupt to CPU"); 1366 } 1367 1368 inthand_add("clk", apic_8254_intr, (driver_intr_t *)clkintr, NULL, 1369 INTR_TYPE_CLK | INTR_FAST, &clkdesc); 1370 crit = intr_disable(); 1371 mtx_lock_spin(&icu_lock); 1372 INTREN(1 << apic_8254_intr); 1373 mtx_unlock_spin(&icu_lock); 1374 intr_restore(crit); 1375 1376#else /* APIC_IO */ 1377 1378 /* 1379 * XXX Check the priority of this interrupt handler. I 1380 * couldn't find anything suitable in the BSD/OS code (grog, 1381 * 19 July 2000). 1382 */ 1383 inthand_add("clk", 0, (driver_intr_t *)clkintr, NULL, 1384 INTR_TYPE_CLK | INTR_FAST, NULL); 1385 crit = intr_disable(); 1386 mtx_lock_spin(&icu_lock); 1387 INTREN(IRQ0); 1388 mtx_unlock_spin(&icu_lock); 1389 intr_restore(crit); 1390 1391#endif /* APIC_IO */ 1392 1393#ifndef PC98 1394 /* Initialize RTC. */ 1395 writertc(RTC_STATUSA, rtc_statusa); 1396 writertc(RTC_STATUSB, RTCSB_24HR); 1397 1398 /* Don't bother enabling the statistics clock. */ 1399 if (statclock_disable) 1400 return; 1401 diag = rtcin(RTC_DIAG); 1402 if (diag != 0) 1403 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1404#endif /* !PC98 */ 1405 1406#ifndef PC98 1407#ifdef APIC_IO 1408 if (isa_apic_irq(8) != 8) 1409 panic("APIC RTC != 8"); 1410#endif /* APIC_IO */ 1411 1412 inthand_add("rtc", 8, (driver_intr_t *)rtcintr, NULL, 1413 INTR_TYPE_CLK | INTR_FAST, NULL); 1414 1415 crit = intr_disable(); 1416 mtx_lock_spin(&icu_lock); 1417#ifdef APIC_IO 1418 INTREN(APIC_IRQ8); 1419#else 1420 INTREN(IRQ8); 1421#endif /* APIC_IO */ 1422 mtx_unlock_spin(&icu_lock); 1423 intr_restore(crit); 1424 1425 writertc(RTC_STATUSB, rtc_statusb); 1426#endif /* PC98 */ 1427 1428#ifdef APIC_IO 1429 if (apic_8254_trial) { 1430 1431 printf("APIC_IO: Testing 8254 interrupt delivery\n"); 1432 while (read_intr_count(8) < 6) 1433 ; /* nothing */ 1434 if (read_intr_count(apic_8254_intr) < 3) { 1435 /* 1436 * The MP table is broken. 1437 * The 8254 was not connected to the specified pin 1438 * on the IO APIC. 1439 * Workaround: Limited variant of mixed mode. 1440 */ 1441 1442 crit = intr_disable(); 1443 mtx_lock_spin(&icu_lock); 1444 INTRDIS(1 << apic_8254_intr); 1445 mtx_unlock_spin(&icu_lock); 1446 intr_restore(crit); 1447 inthand_remove(clkdesc); 1448 printf("APIC_IO: Broken MP table detected: " 1449 "8254 is not connected to " 1450 "IOAPIC #%d intpin %d\n", 1451 int_to_apicintpin[apic_8254_intr].ioapic, 1452 int_to_apicintpin[apic_8254_intr].int_pin); 1453 /* 1454 * Revoke current ISA IRQ 0 assignment and 1455 * configure a fallback interrupt routing from 1456 * the 8254 Timer via the 8259 PIC to the 1457 * an ExtInt interrupt line on IOAPIC #0 intpin 0. 1458 * We reuse the low level interrupt handler number. 1459 */ 1460 if (apic_irq(0, 0) < 0) { 1461 revoke_apic_irq(apic_8254_intr); 1462 assign_apic_irq(0, 0, apic_8254_intr); 1463 } 1464 apic_8254_intr = apic_irq(0, 0); 1465 setup_8254_mixed_mode(); 1466 inthand_add("clk", apic_8254_intr, 1467 (driver_intr_t *)clkintr, NULL, 1468 INTR_TYPE_CLK | INTR_FAST, NULL); 1469 crit = intr_disable(); 1470 mtx_lock_spin(&icu_lock); 1471 INTREN(1 << apic_8254_intr); 1472 mtx_unlock_spin(&icu_lock); 1473 intr_restore(crit); 1474 } 1475 1476 } 1477 if (apic_int_type(0, 0) != 3 || 1478 int_to_apicintpin[apic_8254_intr].ioapic != 0 || 1479 int_to_apicintpin[apic_8254_intr].int_pin != 0) 1480 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n", 1481 int_to_apicintpin[apic_8254_intr].ioapic, 1482 int_to_apicintpin[apic_8254_intr].int_pin); 1483 else 1484 printf("APIC_IO: " 1485 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n"); 1486#endif 1487 1488} 1489 1490#ifdef APIC_IO 1491static u_long 1492read_intr_count(int vec) 1493{ 1494 u_long *up; 1495 up = intr_countp[vec]; 1496 if (up) 1497 return *up; 1498 return 0UL; 1499} 1500 1501static void 1502setup_8254_mixed_mode() 1503{ 1504 /* 1505 * Allow 8254 timer to INTerrupt 8259: 1506 * re-initialize master 8259: 1507 * reset; prog 4 bytes, single ICU, edge triggered 1508 */ 1509 outb(IO_ICU1, 0x13); 1510#ifdef PC98 1511 outb(IO_ICU1 + 2, NRSVIDT); /* start vector (unused) */ 1512 outb(IO_ICU1 + 2, 0x00); /* ignore slave */ 1513 outb(IO_ICU1 + 2, 0x03); /* auto EOI, 8086 */ 1514 outb(IO_ICU1 + 2, 0xfe); /* unmask INT0 */ 1515#else 1516 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */ 1517 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1518 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1519 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1520#endif 1521 1522 /* program IO APIC for type 3 INT on INT0 */ 1523 if (ext_int_setup(0, 0) < 0) 1524 panic("8254 redirect via APIC pin0 impossible!"); 1525} 1526#endif 1527 1528void 1529cpu_startprofclock(void) 1530{ 1531#ifndef PC98 1532 if (newhz == RTC_PROFRATE) 1533 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1534 else 1535 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1536 writertc(RTC_STATUSA, rtc_statusa); 1537#endif 1538} 1539 1540void 1541cpu_stopprofclock(void) 1542{ 1543} 1544 1545static int 1546sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS) 1547{ 1548 int error; 1549 u_int freq; 1550 1551 /* 1552 * Use `i8254' instead of `timer' in external names because `timer' 1553 * is is too generic. Should use it everywhere. 1554 */ 1555 freq = timer_freq; 1556 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 1557 if (error == 0 && req->newptr != NULL) { 1558 if (timer0_state != RELEASED) 1559 return (EBUSY); /* too much trouble to handle */ 1560 set_timer_freq(freq, hz); 1561 i8254_timecounter.tc_frequency = freq; 1562 } 1563 return (error); 1564} 1565 1566SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1567 0, sizeof(u_int), sysctl_machdep_i8254_freq, "IU", ""); 1568 1569static int 1570sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS) 1571{ 1572 int error; 1573 uint64_t freq; 1574 1575 if (tsc_timecounter.tc_frequency == 0) 1576 return (EOPNOTSUPP); 1577 freq = tsc_freq; 1578 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 1579 if (error == 0 && req->newptr != NULL) { 1580 tsc_freq = freq; 1581 tsc_timecounter.tc_frequency = tsc_freq; 1582 } 1583 return (error); 1584} 1585 1586SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_QUAD | CTLFLAG_RW, 1587 0, sizeof(u_int), sysctl_machdep_tsc_freq, "IU", ""); 1588 1589static unsigned 1590i8254_get_timecount(struct timecounter *tc) 1591{ 1592 u_int count; 1593 u_int high, low; 1594 u_int eflags; 1595 1596 eflags = read_eflags(); 1597 mtx_lock_spin(&clock_lock); 1598 1599 /* Select timer0 and latch counter value. */ 1600 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 1601 1602 low = inb(TIMER_CNTR0); 1603 high = inb(TIMER_CNTR0); 1604 count = timer0_max_count - ((high << 8) | low); 1605 if (count < i8254_lastcount || 1606 (!i8254_ticked && (clkintr_pending || 1607 ((count < 20 || (!(eflags & PSL_I) && count < timer0_max_count / 2u)) && 1608#ifdef APIC_IO 1609#define lapic_irr1 ((volatile u_int *)&lapic)[0x210 / 4] /* XXX XXX */ 1610 /* XXX this assumes that apic_8254_intr is < 24. */ 1611 (lapic_irr1 & (1 << apic_8254_intr)))) 1612#else 1613 (inb(IO_ICU1) & 1))) 1614#endif 1615 )) { 1616 i8254_ticked = 1; 1617 i8254_offset += timer0_max_count; 1618 } 1619 i8254_lastcount = count; 1620 count += i8254_offset; 1621 mtx_unlock_spin(&clock_lock); 1622 return (count); 1623} 1624 1625static unsigned 1626tsc_get_timecount(struct timecounter *tc) 1627{ 1628 return (rdtsc()); 1629} 1630 1631#ifdef DEV_ISA 1632/* 1633 * Attach to the ISA PnP descriptors for the timer and realtime clock. 1634 */ 1635static struct isa_pnp_id attimer_ids[] = { 1636 { 0x0001d041 /* PNP0100 */, "AT timer" }, 1637 { 0x000bd041 /* PNP0B00 */, "AT realtime clock" }, 1638 { 0 } 1639}; 1640 1641static int 1642attimer_probe(device_t dev) 1643{ 1644 int result; 1645 1646 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids)) <= 0) 1647 device_quiet(dev); 1648 return(result); 1649} 1650 1651static int 1652attimer_attach(device_t dev) 1653{ 1654 return(0); 1655} 1656 1657static device_method_t attimer_methods[] = { 1658 /* Device interface */ 1659 DEVMETHOD(device_probe, attimer_probe), 1660 DEVMETHOD(device_attach, attimer_attach), 1661 DEVMETHOD(device_detach, bus_generic_detach), 1662 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1663 DEVMETHOD(device_suspend, bus_generic_suspend), /* XXX stop statclock? */ 1664 DEVMETHOD(device_resume, bus_generic_resume), /* XXX restart statclock? */ 1665 { 0, 0 } 1666}; 1667 1668static driver_t attimer_driver = { 1669 "attimer", 1670 attimer_methods, 1671 1, /* no softc */ 1672}; 1673 1674static devclass_t attimer_devclass; 1675 1676DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0); 1677#ifndef PC98 1678DRIVER_MODULE(attimer, acpi, attimer_driver, attimer_devclass, 0, 0); 1679#endif 1680#endif /* DEV_ISA */ 1681