pcrtc.c revision 110048
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $FreeBSD: head/sys/pc98/cbus/pcrtc.c 110048 2003-01-29 18:08:26Z phk $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51/* 52 * modified for PC98 by Kakefuda 53 */ 54 55#include "opt_clock.h" 56#include "opt_isa.h" 57#include "opt_mca.h" 58 59#include <sys/param.h> 60#include <sys/stdint.h> 61#include <sys/systm.h> 62#include <sys/bus.h> 63#include <sys/lock.h> 64#include <sys/mutex.h> 65#include <sys/proc.h> 66#include <sys/time.h> 67#include <sys/timetc.h> 68#include <sys/kernel.h> 69#include <sys/sysctl.h> 70#include <sys/cons.h> 71#include <sys/power.h> 72 73#include <machine/clock.h> 74#include <machine/cputypes.h> 75#include <machine/frame.h> 76#include <machine/limits.h> 77#include <machine/md_var.h> 78#include <machine/psl.h> 79#ifdef APIC_IO 80#include <machine/segments.h> 81#endif 82#if defined(SMP) || defined(APIC_IO) 83#include <machine/smp.h> 84#endif /* SMP || APIC_IO */ 85#include <machine/specialreg.h> 86 87#include <i386/isa/icu.h> 88#ifdef PC98 89#include <pc98/pc98/pc98.h> 90#include <pc98/pc98/pc98_machdep.h> 91#include <i386/isa/isa_device.h> 92#else 93#include <i386/isa/isa.h> 94#include <isa/rtc.h> 95#endif 96#ifdef DEV_ISA 97#include <isa/isavar.h> 98#endif 99#include <i386/isa/timerreg.h> 100 101#include <i386/isa/intr_machdep.h> 102 103#ifdef DEV_MCA 104#include <i386/isa/mca_machdep.h> 105#endif 106 107#ifdef APIC_IO 108#include <i386/isa/intr_machdep.h> 109/* The interrupt triggered by the 8254 (timer) chip */ 110int apic_8254_intr; 111static u_long read_intr_count(int vec); 112static void setup_8254_mixed_mode(void); 113#endif 114 115/* 116 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 117 * can use a simple formula for leap years. 118 */ 119#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 120#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 121 122#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 123 124/* 125 * Time in timer cycles that it takes for microtime() to disable interrupts 126 * and latch the count. microtime() currently uses "cli; outb ..." so it 127 * normally takes less than 2 timer cycles. Add a few for cache misses. 128 * Add a few more to allow for latency in bogus calls to microtime() with 129 * interrupts already disabled. 130 */ 131#define TIMER0_LATCH_COUNT 20 132 133/* 134 * Maximum frequency that we are willing to allow for timer0. Must be 135 * low enough to guarantee that the timer interrupt handler returns 136 * before the next timer interrupt. 137 */ 138#define TIMER0_MAX_FREQ 20000 139 140int adjkerntz; /* local offset from GMT in seconds */ 141int clkintr_pending; 142int disable_rtc_set; /* disable resettodr() if != 0 */ 143int statclock_disable; 144#ifndef TIMER_FREQ 145#ifdef PC98 146#define TIMER_FREQ 2457600 147#else /* IBM-PC */ 148#define TIMER_FREQ 1193182 149#endif /* PC98 */ 150#endif 151u_int timer_freq = TIMER_FREQ; 152int timer0_max_count; 153uint64_t tsc_freq; 154int tsc_is_broken; 155u_int tsc_present; 156int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 157struct mtx clock_lock; 158 159static int beeping = 0; 160static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 161static u_int hardclock_max_count; 162static u_int32_t i8254_lastcount; 163static u_int32_t i8254_offset; 164static int i8254_ticked; 165/* 166 * XXX new_function and timer_func should not handle clockframes, but 167 * timer_func currently needs to hold hardclock to handle the 168 * timer0_state == 0 case. We should use inthand_add()/inthand_remove() 169 * to switch between clkintr() and a slightly different timerintr(). 170 */ 171static void (*new_function)(struct clockframe *frame); 172static u_int new_rate; 173#ifndef PC98 174static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 175static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 176#endif 177static u_int timer0_prescaler_count; 178 179/* Values for timerX_state: */ 180#define RELEASED 0 181#define RELEASE_PENDING 1 182#define ACQUIRED 2 183#define ACQUIRE_PENDING 3 184 185static u_char timer0_state; 186#ifdef PC98 187static u_char timer1_state; 188#endif 189static u_char timer2_state; 190static void (*timer_func)(struct clockframe *frame) = hardclock; 191#ifdef PC98 192static void rtc_serialcombit(int); 193static void rtc_serialcom(int); 194static int rtc_inb(void); 195static void rtc_outb(int); 196#endif 197 198static unsigned i8254_get_timecount(struct timecounter *tc); 199static unsigned tsc_get_timecount(struct timecounter *tc); 200static void set_timer_freq(u_int freq, int intr_freq); 201 202static struct timecounter tsc_timecounter = { 203 tsc_get_timecount, /* get_timecount */ 204 0, /* no poll_pps */ 205 ~0u, /* counter_mask */ 206 0, /* frequency */ 207 "TSC" /* name */ 208}; 209 210static struct timecounter i8254_timecounter = { 211 i8254_get_timecount, /* get_timecount */ 212 0, /* no poll_pps */ 213 ~0u, /* counter_mask */ 214 0, /* frequency */ 215 "i8254" /* name */ 216}; 217 218static void 219clkintr(struct clockframe frame) 220{ 221 222 if (timecounter->tc_get_timecount == i8254_get_timecount) { 223 mtx_lock_spin(&clock_lock); 224 if (i8254_ticked) 225 i8254_ticked = 0; 226 else { 227 i8254_offset += timer0_max_count; 228 i8254_lastcount = 0; 229 } 230 clkintr_pending = 0; 231 mtx_unlock_spin(&clock_lock); 232 } 233 timer_func(&frame); 234#ifdef SMP 235 if (timer_func == hardclock) 236 forward_hardclock(); 237#endif 238 switch (timer0_state) { 239 240 case RELEASED: 241 break; 242 243 case ACQUIRED: 244 if ((timer0_prescaler_count += timer0_max_count) 245 >= hardclock_max_count) { 246 timer0_prescaler_count -= hardclock_max_count; 247 hardclock(&frame); 248#ifdef SMP 249 forward_hardclock(); 250#endif 251 } 252 break; 253 254 case ACQUIRE_PENDING: 255 mtx_lock_spin(&clock_lock); 256 i8254_offset = i8254_get_timecount(NULL); 257 i8254_lastcount = 0; 258 timer0_max_count = TIMER_DIV(new_rate); 259 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 260 outb(TIMER_CNTR0, timer0_max_count & 0xff); 261 outb(TIMER_CNTR0, timer0_max_count >> 8); 262 mtx_unlock_spin(&clock_lock); 263 timer_func = new_function; 264 timer0_state = ACQUIRED; 265 break; 266 267 case RELEASE_PENDING: 268 if ((timer0_prescaler_count += timer0_max_count) 269 >= hardclock_max_count) { 270 mtx_lock_spin(&clock_lock); 271 i8254_offset = i8254_get_timecount(NULL); 272 i8254_lastcount = 0; 273 timer0_max_count = hardclock_max_count; 274 outb(TIMER_MODE, 275 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 276 outb(TIMER_CNTR0, timer0_max_count & 0xff); 277 outb(TIMER_CNTR0, timer0_max_count >> 8); 278 mtx_unlock_spin(&clock_lock); 279 timer0_prescaler_count = 0; 280 timer_func = hardclock; 281 timer0_state = RELEASED; 282 hardclock(&frame); 283#ifdef SMP 284 forward_hardclock(); 285#endif 286 } 287 break; 288 } 289#ifdef DEV_MCA 290 /* Reset clock interrupt by asserting bit 7 of port 0x61 */ 291 if (MCA_system) 292 outb(0x61, inb(0x61) | 0x80); 293#endif 294} 295 296/* 297 * The acquire and release functions must be called at ipl >= splclock(). 298 */ 299int 300acquire_timer0(int rate, void (*function)(struct clockframe *frame)) 301{ 302 static int old_rate; 303 304 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 305 return (-1); 306 switch (timer0_state) { 307 308 case RELEASED: 309 timer0_state = ACQUIRE_PENDING; 310 break; 311 312 case RELEASE_PENDING: 313 if (rate != old_rate) 314 return (-1); 315 /* 316 * The timer has been released recently, but is being 317 * re-acquired before the release completed. In this 318 * case, we simply reclaim it as if it had not been 319 * released at all. 320 */ 321 timer0_state = ACQUIRED; 322 break; 323 324 default: 325 return (-1); /* busy */ 326 } 327 new_function = function; 328 old_rate = new_rate = rate; 329 return (0); 330} 331 332#ifdef PC98 333int 334acquire_timer1(int mode) 335{ 336 337 if (timer1_state != RELEASED) 338 return (-1); 339 timer1_state = ACQUIRED; 340 341 /* 342 * This access to the timer registers is as atomic as possible 343 * because it is a single instruction. We could do better if we 344 * knew the rate. Use of splclock() limits glitches to 10-100us, 345 * and this is probably good enough for timer2, so we aren't as 346 * careful with it as with timer0. 347 */ 348 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 349 350 return (0); 351} 352#endif 353 354int 355acquire_timer2(int mode) 356{ 357 358 if (timer2_state != RELEASED) 359 return (-1); 360 timer2_state = ACQUIRED; 361 362 /* 363 * This access to the timer registers is as atomic as possible 364 * because it is a single instruction. We could do better if we 365 * knew the rate. Use of splclock() limits glitches to 10-100us, 366 * and this is probably good enough for timer2, so we aren't as 367 * careful with it as with timer0. 368 */ 369 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 370 371 return (0); 372} 373 374int 375release_timer0() 376{ 377 switch (timer0_state) { 378 379 case ACQUIRED: 380 timer0_state = RELEASE_PENDING; 381 break; 382 383 case ACQUIRE_PENDING: 384 /* Nothing happened yet, release quickly. */ 385 timer0_state = RELEASED; 386 break; 387 388 default: 389 return (-1); 390 } 391 return (0); 392} 393 394#ifdef PC98 395int 396release_timer1() 397{ 398 399 if (timer1_state != ACQUIRED) 400 return (-1); 401 timer1_state = RELEASED; 402 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 403 return (0); 404} 405#endif 406 407int 408release_timer2() 409{ 410 411 if (timer2_state != ACQUIRED) 412 return (-1); 413 timer2_state = RELEASED; 414 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 415 return (0); 416} 417 418#ifndef PC98 419/* 420 * This routine receives statistical clock interrupts from the RTC. 421 * As explained above, these occur at 128 interrupts per second. 422 * When profiling, we receive interrupts at a rate of 1024 Hz. 423 * 424 * This does not actually add as much overhead as it sounds, because 425 * when the statistical clock is active, the hardclock driver no longer 426 * needs to keep (inaccurate) statistics on its own. This decouples 427 * statistics gathering from scheduling interrupts. 428 * 429 * The RTC chip requires that we read status register C (RTC_INTR) 430 * to acknowledge an interrupt, before it will generate the next one. 431 * Under high interrupt load, rtcintr() can be indefinitely delayed and 432 * the clock can tick immediately after the read from RTC_INTR. In this 433 * case, the mc146818A interrupt signal will not drop for long enough 434 * to register with the 8259 PIC. If an interrupt is missed, the stat 435 * clock will halt, considerably degrading system performance. This is 436 * why we use 'while' rather than a more straightforward 'if' below. 437 * Stat clock ticks can still be lost, causing minor loss of accuracy 438 * in the statistics, but the stat clock will no longer stop. 439 */ 440static void 441rtcintr(struct clockframe frame) 442{ 443 while (rtcin(RTC_INTR) & RTCIR_PERIOD) { 444 statclock(&frame); 445#ifdef SMP 446 forward_statclock(); 447#endif 448 } 449} 450 451#include "opt_ddb.h" 452#ifdef DDB 453#include <ddb/ddb.h> 454 455DB_SHOW_COMMAND(rtc, rtc) 456{ 457 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 458 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 459 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 460 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 461} 462#endif /* DDB */ 463#endif /* for PC98 */ 464 465static int 466getit(void) 467{ 468 int high, low; 469 470 mtx_lock_spin(&clock_lock); 471 472 /* Select timer0 and latch counter value. */ 473 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 474 475 low = inb(TIMER_CNTR0); 476 high = inb(TIMER_CNTR0); 477 478 mtx_unlock_spin(&clock_lock); 479 return ((high << 8) | low); 480} 481 482/* 483 * Wait "n" microseconds. 484 * Relies on timer 1 counting down from (timer_freq / hz) 485 * Note: timer had better have been programmed before this is first used! 486 */ 487void 488DELAY(int n) 489{ 490 int delta, prev_tick, tick, ticks_left; 491 492#ifdef DELAYDEBUG 493 int getit_calls = 1; 494 int n1; 495 static int state = 0; 496 497 if (state == 0) { 498 state = 1; 499 for (n1 = 1; n1 <= 10000000; n1 *= 10) 500 DELAY(n1); 501 state = 2; 502 } 503 if (state == 1) 504 printf("DELAY(%d)...", n); 505#endif 506 /* 507 * Guard against the timer being uninitialized if we are called 508 * early for console i/o. 509 */ 510 if (timer0_max_count == 0) 511 set_timer_freq(timer_freq, hz); 512 513 /* 514 * Read the counter first, so that the rest of the setup overhead is 515 * counted. Guess the initial overhead is 20 usec (on most systems it 516 * takes about 1.5 usec for each of the i/o's in getit(). The loop 517 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 518 * multiplications and divisions to scale the count take a while). 519 */ 520 prev_tick = getit(); 521 n -= 0; /* XXX actually guess no initial overhead */ 522 /* 523 * Calculate (n * (timer_freq / 1e6)) without using floating point 524 * and without any avoidable overflows. 525 */ 526 if (n <= 0) 527 ticks_left = 0; 528 else if (n < 256) 529 /* 530 * Use fixed point to avoid a slow division by 1000000. 531 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 532 * 2^15 is the first power of 2 that gives exact results 533 * for n between 0 and 256. 534 */ 535 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 536 else 537 /* 538 * Don't bother using fixed point, although gcc-2.7.2 539 * generates particularly poor code for the long long 540 * division, since even the slow way will complete long 541 * before the delay is up (unless we're interrupted). 542 */ 543 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 544 / 1000000; 545 546 while (ticks_left > 0) { 547 tick = getit(); 548#ifdef DELAYDEBUG 549 ++getit_calls; 550#endif 551 delta = prev_tick - tick; 552 prev_tick = tick; 553 if (delta < 0) { 554 delta += timer0_max_count; 555 /* 556 * Guard against timer0_max_count being wrong. 557 * This shouldn't happen in normal operation, 558 * but it may happen if set_timer_freq() is 559 * traced. 560 */ 561 if (delta < 0) 562 delta = 0; 563 } 564 ticks_left -= delta; 565 } 566#ifdef DELAYDEBUG 567 if (state == 1) 568 printf(" %d calls to getit() at %d usec each\n", 569 getit_calls, (n + 5) / getit_calls); 570#endif 571} 572 573static void 574sysbeepstop(void *chan) 575{ 576#ifdef PC98 /* PC98 */ 577 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 578 release_timer1(); 579#else 580 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 581 release_timer2(); 582#endif 583 beeping = 0; 584} 585 586int 587sysbeep(int pitch, int period) 588{ 589 int x = splclock(); 590 591#ifdef PC98 592 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 593 if (!beeping) { 594 /* Something else owns it. */ 595 splx(x); 596 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 597 } 598 disable_intr(); 599 outb(0x3fdb, pitch); 600 outb(0x3fdb, (pitch>>8)); 601 enable_intr(); 602 if (!beeping) { 603 /* enable counter1 output to speaker */ 604 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 605 beeping = period; 606 timeout(sysbeepstop, (void *)NULL, period); 607 } 608#else 609 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 610 if (!beeping) { 611 /* Something else owns it. */ 612 splx(x); 613 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 614 } 615 mtx_lock_spin(&clock_lock); 616 outb(TIMER_CNTR2, pitch); 617 outb(TIMER_CNTR2, (pitch>>8)); 618 mtx_unlock_spin(&clock_lock); 619 if (!beeping) { 620 /* enable counter2 output to speaker */ 621 outb(IO_PPI, inb(IO_PPI) | 3); 622 beeping = period; 623 timeout(sysbeepstop, (void *)NULL, period); 624 } 625#endif 626 splx(x); 627 return (0); 628} 629 630#ifndef PC98 631/* 632 * RTC support routines 633 */ 634 635int 636rtcin(reg) 637 int reg; 638{ 639 int s; 640 u_char val; 641 642 s = splhigh(); 643 outb(IO_RTC, reg); 644 inb(0x84); 645 val = inb(IO_RTC + 1); 646 inb(0x84); 647 splx(s); 648 return (val); 649} 650 651static __inline void 652writertc(u_char reg, u_char val) 653{ 654 int s; 655 656 s = splhigh(); 657 inb(0x84); 658 outb(IO_RTC, reg); 659 inb(0x84); 660 outb(IO_RTC + 1, val); 661 inb(0x84); /* XXX work around wrong order in rtcin() */ 662 splx(s); 663} 664 665static __inline int 666readrtc(int port) 667{ 668 return(bcd2bin(rtcin(port))); 669} 670#endif 671 672#ifdef PC98 673unsigned int delaycount; 674#define FIRST_GUESS 0x2000 675static void findcpuspeed(void) 676{ 677 int i; 678 int remainder; 679 680 /* Put counter in count down mode */ 681 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 682 outb(TIMER_CNTR0, 0xff); 683 outb(TIMER_CNTR0, 0xff); 684 for (i = FIRST_GUESS; i; i--) 685 ; 686 remainder = getit(); 687 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 688} 689#endif 690 691#ifdef PC98 692static u_int 693calibrate_clocks(void) 694{ 695 int timeout; 696 u_int count, prev_count, tot_count; 697 u_short sec, start_sec; 698 699 if (bootverbose) 700 printf("Calibrating clock(s) ... "); 701 /* Check ARTIC. */ 702 if (!(PC98_SYSTEM_PARAMETER(0x458) & 0x80) && 703 !(PC98_SYSTEM_PARAMETER(0x45b) & 0x04)) 704 goto fail; 705 timeout = 100000000; 706 707 /* Read the ARTIC. */ 708 sec = inw(0x5e); 709 710 /* Wait for the ARTIC to changes. */ 711 start_sec = sec; 712 for (;;) { 713 sec = inw(0x5e); 714 if (sec != start_sec) 715 break; 716 if (--timeout == 0) 717 goto fail; 718 } 719 prev_count = getit(); 720 if (prev_count == 0 || prev_count > timer0_max_count) 721 goto fail; 722 tot_count = 0; 723 724 if (tsc_present) 725 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 726 start_sec = sec; 727 for (;;) { 728 sec = inw(0x5e); 729 count = getit(); 730 if (count == 0 || count > timer0_max_count) 731 goto fail; 732 if (count > prev_count) 733 tot_count += prev_count - (count - timer0_max_count); 734 else 735 tot_count += prev_count - count; 736 prev_count = count; 737 if ((sec == start_sec + 1200) || 738 (sec < start_sec && 739 (u_int)sec + 0x10000 == (u_int)start_sec + 1200)) 740 break; 741 if (--timeout == 0) 742 goto fail; 743 } 744 /* 745 * Read the cpu cycle counter. The timing considerations are 746 * similar to those for the i8254 clock. 747 */ 748 if (tsc_present) 749 tsc_freq = rdtsc(); 750 751 if (bootverbose) { 752 if (tsc_present) 753 printf("TSC clock: %ju Hz, ", (intmax_t)tsc_freq); 754 printf("i8254 clock: %u Hz\n", tot_count); 755 } 756 return (tot_count); 757 758fail: 759 if (bootverbose) 760 printf("failed, using default i8254 clock of %u Hz\n", 761 timer_freq); 762 return (timer_freq); 763} 764#else 765static u_int 766calibrate_clocks(void) 767{ 768 u_int64_t old_tsc; 769 u_int count, prev_count, tot_count; 770 int sec, start_sec, timeout; 771 772 if (bootverbose) 773 printf("Calibrating clock(s) ... "); 774 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 775 goto fail; 776 timeout = 100000000; 777 778 /* Read the mc146818A seconds counter. */ 779 for (;;) { 780 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 781 sec = rtcin(RTC_SEC); 782 break; 783 } 784 if (--timeout == 0) 785 goto fail; 786 } 787 788 /* Wait for the mC146818A seconds counter to change. */ 789 start_sec = sec; 790 for (;;) { 791 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 792 sec = rtcin(RTC_SEC); 793 if (sec != start_sec) 794 break; 795 } 796 if (--timeout == 0) 797 goto fail; 798 } 799 800 /* Start keeping track of the i8254 counter. */ 801 prev_count = getit(); 802 if (prev_count == 0 || prev_count > timer0_max_count) 803 goto fail; 804 tot_count = 0; 805 806 if (tsc_present) 807 old_tsc = rdtsc(); 808 else 809 old_tsc = 0; /* shut up gcc */ 810 811 /* 812 * Wait for the mc146818A seconds counter to change. Read the i8254 813 * counter for each iteration since this is convenient and only 814 * costs a few usec of inaccuracy. The timing of the final reads 815 * of the counters almost matches the timing of the initial reads, 816 * so the main cause of inaccuracy is the varying latency from 817 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 818 * rtcin(RTC_SEC) that returns a changed seconds count. The 819 * maximum inaccuracy from this cause is < 10 usec on 486's. 820 */ 821 start_sec = sec; 822 for (;;) { 823 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 824 sec = rtcin(RTC_SEC); 825 count = getit(); 826 if (count == 0 || count > timer0_max_count) 827 goto fail; 828 if (count > prev_count) 829 tot_count += prev_count - (count - timer0_max_count); 830 else 831 tot_count += prev_count - count; 832 prev_count = count; 833 if (sec != start_sec) 834 break; 835 if (--timeout == 0) 836 goto fail; 837 } 838 839 /* 840 * Read the cpu cycle counter. The timing considerations are 841 * similar to those for the i8254 clock. 842 */ 843 if (tsc_present) 844 tsc_freq = rdtsc() - old_tsc; 845 846 if (bootverbose) { 847 if (tsc_present) 848 printf("TSC clock: %u Hz, ", tsc_freq); 849 printf("i8254 clock: %u Hz\n", tot_count); 850 } 851 return (tot_count); 852 853fail: 854 if (bootverbose) 855 printf("failed, using default i8254 clock of %u Hz\n", 856 timer_freq); 857 return (timer_freq); 858} 859#endif /* !PC98 */ 860 861static void 862set_timer_freq(u_int freq, int intr_freq) 863{ 864 int new_timer0_max_count; 865 866 mtx_lock_spin(&clock_lock); 867 timer_freq = freq; 868 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 869 if (new_timer0_max_count != timer0_max_count) { 870 timer0_max_count = new_timer0_max_count; 871 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 872 outb(TIMER_CNTR0, timer0_max_count & 0xff); 873 outb(TIMER_CNTR0, timer0_max_count >> 8); 874 } 875 mtx_unlock_spin(&clock_lock); 876} 877 878static void 879i8254_restore(void) 880{ 881 882 mtx_lock_spin(&clock_lock); 883 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 884 outb(TIMER_CNTR0, timer0_max_count & 0xff); 885 outb(TIMER_CNTR0, timer0_max_count >> 8); 886 mtx_unlock_spin(&clock_lock); 887} 888 889#ifndef PC98 890static void 891rtc_restore(void) 892{ 893 894 /* Restore all of the RTC's "status" (actually, control) registers. */ 895 /* XXX locking is needed for RTC access. */ 896 writertc(RTC_STATUSB, RTCSB_24HR); 897 writertc(RTC_STATUSA, rtc_statusa); 898 writertc(RTC_STATUSB, rtc_statusb); 899} 900#endif 901 902/* 903 * Restore all the timers non-atomically (XXX: should be atomically). 904 * 905 * This function is called from pmtimer_resume() to restore all the timers. 906 * This should not be necessary, but there are broken laptops that do not 907 * restore all the timers on resume. 908 */ 909void 910timer_restore(void) 911{ 912 913 i8254_restore(); /* restore timer_freq and hz */ 914#ifndef PC98 915 rtc_restore(); /* reenable RTC interrupts */ 916#endif 917} 918 919/* 920 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 921 * XXX initialization of other timers is unintentionally left blank. 922 */ 923void 924startrtclock() 925{ 926 u_int delta, freq; 927 928#ifdef PC98 929 findcpuspeed(); 930 if (pc98_machine_type & M_8M) 931 timer_freq = 1996800L; /* 1.9968 MHz */ 932 else 933 timer_freq = 2457600L; /* 2.4576 MHz */ 934#endif /* PC98 */ 935 936 if (cpu_feature & CPUID_TSC) 937 tsc_present = 1; 938 else 939 tsc_present = 0; 940 941#ifndef PC98 942 writertc(RTC_STATUSA, rtc_statusa); 943 writertc(RTC_STATUSB, RTCSB_24HR); 944#endif 945 946 set_timer_freq(timer_freq, hz); 947 freq = calibrate_clocks(); 948#ifdef CLK_CALIBRATION_LOOP 949 if (bootverbose) { 950 printf( 951 "Press a key on the console to abort clock calibration\n"); 952 while (cncheckc() == -1) 953 calibrate_clocks(); 954 } 955#endif 956 957 /* 958 * Use the calibrated i8254 frequency if it seems reasonable. 959 * Otherwise use the default, and don't use the calibrated i586 960 * frequency. 961 */ 962 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 963 if (delta < timer_freq / 100) { 964#ifndef CLK_USE_I8254_CALIBRATION 965 if (bootverbose) 966 printf( 967"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 968 freq = timer_freq; 969#endif 970 timer_freq = freq; 971 } else { 972 if (bootverbose) 973 printf( 974 "%d Hz differs from default of %d Hz by more than 1%%\n", 975 freq, timer_freq); 976 tsc_freq = 0; 977 } 978 979 set_timer_freq(timer_freq, hz); 980 i8254_timecounter.tc_frequency = timer_freq; 981 tc_init(&i8254_timecounter); 982 983#ifndef CLK_USE_TSC_CALIBRATION 984 if (tsc_freq != 0) { 985 if (bootverbose) 986 printf( 987"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 988 tsc_freq = 0; 989 } 990#endif 991 if (tsc_present && tsc_freq == 0) { 992 /* 993 * Calibration of the i586 clock relative to the mc146818A 994 * clock failed. Do a less accurate calibration relative 995 * to the i8254 clock. 996 */ 997 u_int64_t old_tsc = rdtsc(); 998 999 DELAY(1000000); 1000 tsc_freq = rdtsc() - old_tsc; 1001#ifdef CLK_USE_TSC_CALIBRATION 1002 if (bootverbose) 1003 printf("TSC clock: %u Hz (Method B)\n", tsc_freq); 1004#endif 1005 } 1006 1007#if !defined(SMP) 1008 /* 1009 * We can not use the TSC in SMP mode, until we figure out a 1010 * cheap (impossible), reliable and precise (yeah right!) way 1011 * to synchronize the TSCs of all the CPUs. 1012 * Curse Intel for leaving the counter out of the I/O APIC. 1013 */ 1014 1015 /* 1016 * We can not use the TSC if we support APM. Precise timekeeping 1017 * on an APM'ed machine is at best a fools pursuit, since 1018 * any and all of the time spent in various SMM code can't 1019 * be reliably accounted for. Reading the RTC is your only 1020 * source of reliable time info. The i8254 looses too of course 1021 * but we need to have some kind of time... 1022 * We don't know at this point whether APM is going to be used 1023 * or not, nor when it might be activated. Play it safe. 1024 */ 1025 if (power_pm_get_type() == POWER_PM_TYPE_APM) { 1026 if (bootverbose) 1027 printf("TSC initialization skipped: APM enabled.\n"); 1028 return; 1029 } 1030 1031 if (tsc_present && tsc_freq != 0 && !tsc_is_broken) { 1032 tsc_timecounter.tc_frequency = tsc_freq; 1033 tc_init(&tsc_timecounter); 1034 } 1035 1036#endif /* !defined(SMP) */ 1037} 1038 1039#ifdef PC98 1040static void 1041rtc_serialcombit(int i) 1042{ 1043 outb(IO_RTC, ((i&0x01)<<5)|0x07); 1044 DELAY(1); 1045 outb(IO_RTC, ((i&0x01)<<5)|0x17); 1046 DELAY(1); 1047 outb(IO_RTC, ((i&0x01)<<5)|0x07); 1048 DELAY(1); 1049} 1050 1051static void 1052rtc_serialcom(int i) 1053{ 1054 rtc_serialcombit(i&0x01); 1055 rtc_serialcombit((i&0x02)>>1); 1056 rtc_serialcombit((i&0x04)>>2); 1057 rtc_serialcombit((i&0x08)>>3); 1058 outb(IO_RTC, 0x07); 1059 DELAY(1); 1060 outb(IO_RTC, 0x0f); 1061 DELAY(1); 1062 outb(IO_RTC, 0x07); 1063 DELAY(1); 1064} 1065 1066static void 1067rtc_outb(int val) 1068{ 1069 int s; 1070 int sa = 0; 1071 1072 for (s=0;s<8;s++) { 1073 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 1074 outb(IO_RTC, sa); /* set DI & CLK 0 */ 1075 DELAY(1); 1076 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 1077 DELAY(1); 1078 } 1079 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 1080} 1081 1082static int 1083rtc_inb(void) 1084{ 1085 int s; 1086 int sa = 0; 1087 1088 for (s=0;s<8;s++) { 1089 sa |= ((inb(0x33) & 0x01) << s); 1090 outb(IO_RTC, 0x17); /* CLK 1 */ 1091 DELAY(1); 1092 outb(IO_RTC, 0x07); /* CLK 0 */ 1093 DELAY(2); 1094 } 1095 return sa; 1096} 1097#endif /* PC-98 */ 1098 1099/* 1100 * Initialize the time of day register, based on the time base which is, e.g. 1101 * from a filesystem. 1102 */ 1103void 1104inittodr(time_t base) 1105{ 1106 unsigned long sec, days; 1107 int year, month; 1108 int y, m, s; 1109 struct timespec ts; 1110#ifdef PC98 1111 int second, min, hour; 1112#endif 1113 1114 if (base) { 1115 s = splclock(); 1116 ts.tv_sec = base; 1117 ts.tv_nsec = 0; 1118 tc_setclock(&ts); 1119 splx(s); 1120 } 1121 1122#ifdef PC98 1123 rtc_serialcom(0x03); /* Time Read */ 1124 rtc_serialcom(0x01); /* Register shift command. */ 1125 DELAY(20); 1126 1127 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 1128 min = bcd2bin(rtc_inb() & 0xff); /* min */ 1129 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 1130 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 1131 1132 month = (rtc_inb() >> 4) & 0x0f; /* month */ 1133 for (m = 1; m < month; m++) 1134 days += daysinmonth[m-1]; 1135 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 1136 /* 2000 year problem */ 1137 if (year < 1995) 1138 year += 100; 1139 if (year < 1970) 1140 goto wrong_time; 1141 for (y = 1970; y < year; y++) 1142 days += DAYSPERYEAR + LEAPYEAR(y); 1143 if ((month > 2) && LEAPYEAR(year)) 1144 days ++; 1145 sec = ((( days * 24 + 1146 hour) * 60 + 1147 min) * 60 + 1148 second); 1149 /* sec now contains the number of seconds, since Jan 1 1970, 1150 in the local time zone */ 1151 1152 s = splhigh(); 1153#else /* IBM-PC */ 1154 /* Look if we have a RTC present and the time is valid */ 1155 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 1156 goto wrong_time; 1157 1158 /* wait for time update to complete */ 1159 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 1160 s = splhigh(); 1161 while (rtcin(RTC_STATUSA) & RTCSA_TUP) { 1162 splx(s); 1163 s = splhigh(); 1164 } 1165 1166 days = 0; 1167#ifdef USE_RTC_CENTURY 1168 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 1169#else 1170 year = readrtc(RTC_YEAR) + 1900; 1171 if (year < 1970) 1172 year += 100; 1173#endif 1174 if (year < 1970) { 1175 splx(s); 1176 goto wrong_time; 1177 } 1178 month = readrtc(RTC_MONTH); 1179 for (m = 1; m < month; m++) 1180 days += daysinmonth[m-1]; 1181 if ((month > 2) && LEAPYEAR(year)) 1182 days ++; 1183 days += readrtc(RTC_DAY) - 1; 1184 for (y = 1970; y < year; y++) 1185 days += DAYSPERYEAR + LEAPYEAR(y); 1186 sec = ((( days * 24 + 1187 readrtc(RTC_HRS)) * 60 + 1188 readrtc(RTC_MIN)) * 60 + 1189 readrtc(RTC_SEC)); 1190 /* sec now contains the number of seconds, since Jan 1 1970, 1191 in the local time zone */ 1192#endif 1193 1194 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1195 1196 y = time_second - sec; 1197 if (y <= -2 || y >= 2) { 1198 /* badly off, adjust it */ 1199 ts.tv_sec = sec; 1200 ts.tv_nsec = 0; 1201 tc_setclock(&ts); 1202 } 1203 splx(s); 1204 return; 1205 1206wrong_time: 1207 printf("Invalid time in real time clock.\n"); 1208 printf("Check and reset the date immediately!\n"); 1209} 1210 1211/* 1212 * Write system time back to RTC 1213 */ 1214void 1215resettodr() 1216{ 1217 unsigned long tm; 1218 int y, m, s; 1219#ifdef PC98 1220 int wd; 1221#endif 1222 1223 if (disable_rtc_set) 1224 return; 1225 1226 s = splclock(); 1227 tm = time_second; 1228 splx(s); 1229 1230#ifdef PC98 1231 rtc_serialcom(0x01); /* Register shift command. */ 1232 1233 /* Calculate local time to put in RTC */ 1234 1235 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1236 1237 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1238 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1239 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1240 1241 /* We have now the days since 01-01-1970 in tm */ 1242 wd = (tm+4)%7; 1243 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1244 tm >= m; 1245 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1246 tm -= m; 1247 1248 /* Now we have the years in y and the day-of-the-year in tm */ 1249 for (m = 0; ; m++) { 1250 int ml; 1251 1252 ml = daysinmonth[m]; 1253 if (m == 1 && LEAPYEAR(y)) 1254 ml++; 1255 if (tm < ml) 1256 break; 1257 tm -= ml; 1258 } 1259 1260 m++; 1261 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1262 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1263 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1264 1265 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1266 rtc_serialcom(0x00); /* Register hold command. */ 1267#else 1268 /* Disable RTC updates and interrupts. */ 1269 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1270 1271 /* Calculate local time to put in RTC */ 1272 1273 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1274 1275 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1276 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1277 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1278 1279 /* We have now the days since 01-01-1970 in tm */ 1280 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1281 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1282 tm >= m; 1283 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1284 tm -= m; 1285 1286 /* Now we have the years in y and the day-of-the-year in tm */ 1287 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1288#ifdef USE_RTC_CENTURY 1289 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1290#endif 1291 for (m = 0; ; m++) { 1292 int ml; 1293 1294 ml = daysinmonth[m]; 1295 if (m == 1 && LEAPYEAR(y)) 1296 ml++; 1297 if (tm < ml) 1298 break; 1299 tm -= ml; 1300 } 1301 1302 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1303 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1304 1305 /* Reenable RTC updates and interrupts. */ 1306 writertc(RTC_STATUSB, rtc_statusb); 1307#endif /* PC98 */ 1308} 1309 1310 1311/* 1312 * Start both clocks running. 1313 */ 1314void 1315cpu_initclocks() 1316{ 1317#ifndef PC98 1318 int diag; 1319#endif 1320#ifdef APIC_IO 1321 int apic_8254_trial; 1322 void *clkdesc; 1323#endif /* APIC_IO */ 1324 register_t crit; 1325 1326#ifndef PC98 1327 if (statclock_disable) { 1328 /* 1329 * The stat interrupt mask is different without the 1330 * statistics clock. Also, don't set the interrupt 1331 * flag which would normally cause the RTC to generate 1332 * interrupts. 1333 */ 1334 rtc_statusb = RTCSB_24HR; 1335 } else { 1336 /* Setting stathz to nonzero early helps avoid races. */ 1337 stathz = RTC_NOPROFRATE; 1338 profhz = RTC_PROFRATE; 1339 } 1340#endif 1341 1342 /* Finish initializing 8253 timer 0. */ 1343#ifdef APIC_IO 1344 1345 apic_8254_intr = isa_apic_irq(0); 1346 apic_8254_trial = 0; 1347 if (apic_8254_intr >= 0 ) { 1348 if (apic_int_type(0, 0) == 3) 1349 apic_8254_trial = 1; 1350 } else { 1351 /* look for ExtInt on pin 0 */ 1352 if (apic_int_type(0, 0) == 3) { 1353 apic_8254_intr = apic_irq(0, 0); 1354 setup_8254_mixed_mode(); 1355 } else 1356 panic("APIC_IO: Cannot route 8254 interrupt to CPU"); 1357 } 1358 1359 inthand_add("clk", apic_8254_intr, (driver_intr_t *)clkintr, NULL, 1360 INTR_TYPE_CLK | INTR_FAST, &clkdesc); 1361 crit = intr_disable(); 1362 mtx_lock_spin(&icu_lock); 1363 INTREN(1 << apic_8254_intr); 1364 mtx_unlock_spin(&icu_lock); 1365 intr_restore(crit); 1366 1367#else /* APIC_IO */ 1368 1369 /* 1370 * XXX Check the priority of this interrupt handler. I 1371 * couldn't find anything suitable in the BSD/OS code (grog, 1372 * 19 July 2000). 1373 */ 1374 inthand_add("clk", 0, (driver_intr_t *)clkintr, NULL, 1375 INTR_TYPE_CLK | INTR_FAST, NULL); 1376 crit = intr_disable(); 1377 mtx_lock_spin(&icu_lock); 1378 INTREN(IRQ0); 1379 mtx_unlock_spin(&icu_lock); 1380 intr_restore(crit); 1381 1382#endif /* APIC_IO */ 1383 1384#ifndef PC98 1385 /* Initialize RTC. */ 1386 writertc(RTC_STATUSA, rtc_statusa); 1387 writertc(RTC_STATUSB, RTCSB_24HR); 1388 1389 /* Don't bother enabling the statistics clock. */ 1390 if (statclock_disable) 1391 return; 1392 diag = rtcin(RTC_DIAG); 1393 if (diag != 0) 1394 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1395#endif /* !PC98 */ 1396 1397#ifndef PC98 1398#ifdef APIC_IO 1399 if (isa_apic_irq(8) != 8) 1400 panic("APIC RTC != 8"); 1401#endif /* APIC_IO */ 1402 1403 inthand_add("rtc", 8, (driver_intr_t *)rtcintr, NULL, 1404 INTR_TYPE_CLK | INTR_FAST, NULL); 1405 1406 crit = intr_disable(); 1407 mtx_lock_spin(&icu_lock); 1408#ifdef APIC_IO 1409 INTREN(APIC_IRQ8); 1410#else 1411 INTREN(IRQ8); 1412#endif /* APIC_IO */ 1413 mtx_unlock_spin(&icu_lock); 1414 intr_restore(crit); 1415 1416 writertc(RTC_STATUSB, rtc_statusb); 1417#endif /* PC98 */ 1418 1419#ifdef APIC_IO 1420 if (apic_8254_trial) { 1421 1422 printf("APIC_IO: Testing 8254 interrupt delivery\n"); 1423 while (read_intr_count(8) < 6) 1424 ; /* nothing */ 1425 if (read_intr_count(apic_8254_intr) < 3) { 1426 /* 1427 * The MP table is broken. 1428 * The 8254 was not connected to the specified pin 1429 * on the IO APIC. 1430 * Workaround: Limited variant of mixed mode. 1431 */ 1432 1433 crit = intr_disable(); 1434 mtx_lock_spin(&icu_lock); 1435 INTRDIS(1 << apic_8254_intr); 1436 mtx_unlock_spin(&icu_lock); 1437 intr_restore(crit); 1438 inthand_remove(clkdesc); 1439 printf("APIC_IO: Broken MP table detected: " 1440 "8254 is not connected to " 1441 "IOAPIC #%d intpin %d\n", 1442 int_to_apicintpin[apic_8254_intr].ioapic, 1443 int_to_apicintpin[apic_8254_intr].int_pin); 1444 /* 1445 * Revoke current ISA IRQ 0 assignment and 1446 * configure a fallback interrupt routing from 1447 * the 8254 Timer via the 8259 PIC to the 1448 * an ExtInt interrupt line on IOAPIC #0 intpin 0. 1449 * We reuse the low level interrupt handler number. 1450 */ 1451 if (apic_irq(0, 0) < 0) { 1452 revoke_apic_irq(apic_8254_intr); 1453 assign_apic_irq(0, 0, apic_8254_intr); 1454 } 1455 apic_8254_intr = apic_irq(0, 0); 1456 setup_8254_mixed_mode(); 1457 inthand_add("clk", apic_8254_intr, 1458 (driver_intr_t *)clkintr, NULL, 1459 INTR_TYPE_CLK | INTR_FAST, NULL); 1460 crit = intr_disable(); 1461 mtx_lock_spin(&icu_lock); 1462 INTREN(1 << apic_8254_intr); 1463 mtx_unlock_spin(&icu_lock); 1464 intr_restore(crit); 1465 } 1466 1467 } 1468 if (apic_int_type(0, 0) != 3 || 1469 int_to_apicintpin[apic_8254_intr].ioapic != 0 || 1470 int_to_apicintpin[apic_8254_intr].int_pin != 0) 1471 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n", 1472 int_to_apicintpin[apic_8254_intr].ioapic, 1473 int_to_apicintpin[apic_8254_intr].int_pin); 1474 else 1475 printf("APIC_IO: " 1476 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n"); 1477#endif 1478 1479} 1480 1481#ifdef APIC_IO 1482static u_long 1483read_intr_count(int vec) 1484{ 1485 u_long *up; 1486 up = intr_countp[vec]; 1487 if (up) 1488 return *up; 1489 return 0UL; 1490} 1491 1492static void 1493setup_8254_mixed_mode() 1494{ 1495 /* 1496 * Allow 8254 timer to INTerrupt 8259: 1497 * re-initialize master 8259: 1498 * reset; prog 4 bytes, single ICU, edge triggered 1499 */ 1500 outb(IO_ICU1, 0x13); 1501#ifdef PC98 1502 outb(IO_ICU1 + 2, NRSVIDT); /* start vector (unused) */ 1503 outb(IO_ICU1 + 2, 0x00); /* ignore slave */ 1504 outb(IO_ICU1 + 2, 0x03); /* auto EOI, 8086 */ 1505 outb(IO_ICU1 + 2, 0xfe); /* unmask INT0 */ 1506#else 1507 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */ 1508 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1509 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1510 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1511#endif 1512 1513 /* program IO APIC for type 3 INT on INT0 */ 1514 if (ext_int_setup(0, 0) < 0) 1515 panic("8254 redirect via APIC pin0 impossible!"); 1516} 1517#endif 1518 1519void 1520setstatclockrate(int newhz) 1521{ 1522#ifndef PC98 1523 if (newhz == RTC_PROFRATE) 1524 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1525 else 1526 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1527 writertc(RTC_STATUSA, rtc_statusa); 1528#endif 1529} 1530 1531static int 1532sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS) 1533{ 1534 int error; 1535 u_int freq; 1536 1537 /* 1538 * Use `i8254' instead of `timer' in external names because `timer' 1539 * is is too generic. Should use it everywhere. 1540 */ 1541 freq = timer_freq; 1542 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 1543 if (error == 0 && req->newptr != NULL) { 1544 if (timer0_state != RELEASED) 1545 return (EBUSY); /* too much trouble to handle */ 1546 set_timer_freq(freq, hz); 1547 i8254_timecounter.tc_frequency = freq; 1548 } 1549 return (error); 1550} 1551 1552SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1553 0, sizeof(u_int), sysctl_machdep_i8254_freq, "IU", ""); 1554 1555static int 1556sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS) 1557{ 1558 int error; 1559 u_int freq; 1560 1561 if (tsc_timecounter.tc_frequency == 0) 1562 return (EOPNOTSUPP); 1563 freq = tsc_freq; 1564 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 1565 if (error == 0 && req->newptr != NULL) { 1566 tsc_freq = freq; 1567 tsc_timecounter.tc_frequency = tsc_freq; 1568 } 1569 return (error); 1570} 1571 1572SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW, 1573 0, sizeof(u_int), sysctl_machdep_tsc_freq, "IU", ""); 1574 1575static unsigned 1576i8254_get_timecount(struct timecounter *tc) 1577{ 1578 u_int count; 1579 u_int high, low; 1580 u_int eflags; 1581 1582 eflags = read_eflags(); 1583 mtx_lock_spin(&clock_lock); 1584 1585 /* Select timer0 and latch counter value. */ 1586 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 1587 1588 low = inb(TIMER_CNTR0); 1589 high = inb(TIMER_CNTR0); 1590 count = timer0_max_count - ((high << 8) | low); 1591 if (count < i8254_lastcount || 1592 (!i8254_ticked && (clkintr_pending || 1593 ((count < 20 || (!(eflags & PSL_I) && count < timer0_max_count / 2u)) && 1594#ifdef APIC_IO 1595#define lapic_irr1 ((volatile u_int *)&lapic)[0x210 / 4] /* XXX XXX */ 1596 /* XXX this assumes that apic_8254_intr is < 24. */ 1597 (lapic_irr1 & (1 << apic_8254_intr)))) 1598#else 1599 (inb(IO_ICU1) & 1))) 1600#endif 1601 )) { 1602 i8254_ticked = 1; 1603 i8254_offset += timer0_max_count; 1604 } 1605 i8254_lastcount = count; 1606 count += i8254_offset; 1607 mtx_unlock_spin(&clock_lock); 1608 return (count); 1609} 1610 1611static unsigned 1612tsc_get_timecount(struct timecounter *tc) 1613{ 1614 return (rdtsc()); 1615} 1616 1617#ifdef DEV_ISA 1618/* 1619 * Attach to the ISA PnP descriptors for the timer and realtime clock. 1620 */ 1621static struct isa_pnp_id attimer_ids[] = { 1622 { 0x0001d041 /* PNP0100 */, "AT timer" }, 1623 { 0x000bd041 /* PNP0B00 */, "AT realtime clock" }, 1624 { 0 } 1625}; 1626 1627static int 1628attimer_probe(device_t dev) 1629{ 1630 int result; 1631 1632 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids)) <= 0) 1633 device_quiet(dev); 1634 return(result); 1635} 1636 1637static int 1638attimer_attach(device_t dev) 1639{ 1640 return(0); 1641} 1642 1643static device_method_t attimer_methods[] = { 1644 /* Device interface */ 1645 DEVMETHOD(device_probe, attimer_probe), 1646 DEVMETHOD(device_attach, attimer_attach), 1647 DEVMETHOD(device_detach, bus_generic_detach), 1648 DEVMETHOD(device_shutdown, bus_generic_shutdown), 1649 DEVMETHOD(device_suspend, bus_generic_suspend), /* XXX stop statclock? */ 1650 DEVMETHOD(device_resume, bus_generic_resume), /* XXX restart statclock? */ 1651 { 0, 0 } 1652}; 1653 1654static driver_t attimer_driver = { 1655 "attimer", 1656 attimer_methods, 1657 1, /* no softc */ 1658}; 1659 1660static devclass_t attimer_devclass; 1661 1662DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0); 1663#ifndef PC98 1664DRIVER_MODULE(attimer, acpi, attimer_driver, attimer_devclass, 0, 0); 1665#endif 1666#endif /* DEV_ISA */ 1667