1195333Simp/*- 2195333Simp * Copyright (c) 2007 Bruce M. Simpson. 3195333Simp * All rights reserved. 4195333Simp * 5195333Simp * Redistribution and use in source and binary forms, with or without 6195333Simp * modification, are permitted provided that the following conditions 7195333Simp * are met: 8195333Simp * 1. Redistributions of source code must retain the above copyright 9195333Simp * notice, this list of conditions and the following disclaimer. 10195333Simp * 2. Redistributions in binary form must reproduce the above copyright 11195333Simp * notice, this list of conditions and the following disclaimer in the 12195333Simp * documentation and/or other materials provided with the distribution. 13195333Simp * 14195333Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15195333Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16195333Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17195333Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18195333Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19195333Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20195333Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21195333Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22195333Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23195333Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24195333Simp * SUCH DAMAGE. 25195333Simp */ 26195333Simp 27195333Simp#include <sys/cdefs.h> 28195333Simp__FBSDID("$FreeBSD: releng/10.3/sys/mips/sibyte/sb_machdep.c 247297 2013-02-26 01:00:11Z attilio $"); 29195333Simp 30195333Simp#include "opt_ddb.h" 31195333Simp#include "opt_kdb.h" 32195333Simp 33195333Simp#include <sys/param.h> 34195333Simp#include <sys/conf.h> 35195333Simp#include <sys/kernel.h> 36195333Simp#include <sys/systm.h> 37195333Simp#include <sys/imgact.h> 38195333Simp#include <sys/bio.h> 39195333Simp#include <sys/buf.h> 40195333Simp#include <sys/bus.h> 41195333Simp#include <sys/cpu.h> 42195333Simp#include <sys/cons.h> 43195333Simp#include <sys/exec.h> 44195333Simp#include <sys/ucontext.h> 45195333Simp#include <sys/proc.h> 46195333Simp#include <sys/kdb.h> 47195333Simp#include <sys/ptrace.h> 48195333Simp#include <sys/reboot.h> 49195333Simp#include <sys/signalvar.h> 50195333Simp#include <sys/sysent.h> 51195333Simp#include <sys/sysproto.h> 52195333Simp#include <sys/user.h> 53205364Sneel#include <sys/timetc.h> 54195333Simp 55195333Simp#include <vm/vm.h> 56195333Simp#include <vm/vm_object.h> 57195333Simp#include <vm/vm_page.h> 58195333Simp 59195333Simp#include <machine/cache.h> 60195333Simp#include <machine/clock.h> 61195333Simp#include <machine/cpu.h> 62195333Simp#include <machine/cpuinfo.h> 63195333Simp#include <machine/cpufunc.h> 64195333Simp#include <machine/cpuregs.h> 65195333Simp#include <machine/hwfunc.h> 66195333Simp#include <machine/intr_machdep.h> 67195333Simp#include <machine/locore.h> 68195333Simp#include <machine/md_var.h> 69195333Simp#include <machine/pte.h> 70195333Simp#include <machine/sigframe.h> 71195333Simp#include <machine/trap.h> 72195333Simp#include <machine/vmparam.h> 73195333Simp 74203697Sneel#ifdef SMP 75208253Sneel#include <sys/smp.h> 76203697Sneel#include <machine/smp.h> 77203697Sneel#endif 78203697Sneel 79195333Simp#ifdef CFE 80195333Simp#include <dev/cfe/cfe_api.h> 81195333Simp#endif 82195333Simp 83195333Simp#include "sb_scd.h" 84195333Simp 85195333Simp#ifdef DDB 86195333Simp#ifndef KDB 87195333Simp#error KDB must be enabled in order for DDB to work! 88195333Simp#endif 89195333Simp#endif 90195333Simp 91195333Simp#ifdef CFE_ENV 92195333Simpextern void cfe_env_init(void); 93195333Simp#endif 94195333Simp 95195333Simpextern int *edata; 96195333Simpextern int *end; 97195333Simp 98203000Sneelextern char MipsTLBMiss[], MipsTLBMissEnd[]; 99203000Sneel 100198669Srrsvoid 101198669Srrsplatform_cpu_init() 102198669Srrs{ 103198669Srrs /* Nothing special */ 104198669Srrs} 105198669Srrs 106195333Simpstatic void 107203510Sneelsb_intr_init(int cpuid) 108203510Sneel{ 109203510Sneel int intrnum, intsrc; 110203510Sneel 111203510Sneel /* 112203510Sneel * Disable all sources to the interrupt mapper and setup the mapping 113203510Sneel * between an interrupt source and the mips hard interrupt number. 114203510Sneel */ 115203510Sneel for (intsrc = 0; intsrc < NUM_INTSRC; ++intsrc) { 116203510Sneel intrnum = sb_route_intsrc(intsrc); 117203510Sneel sb_disable_intsrc(cpuid, intsrc); 118203510Sneel sb_write_intmap(cpuid, intsrc, intrnum); 119203697Sneel#ifdef SMP 120203697Sneel /* 121203697Sneel * Set up the mailbox interrupt mapping. 122203697Sneel * 123203697Sneel * The mailbox interrupt is "special" in that it is not shared 124203697Sneel * with any other interrupt source. 125203697Sneel */ 126203697Sneel if (intsrc == INTSRC_MAILBOX3) { 127203697Sneel intrnum = platform_ipi_intrnum(); 128203697Sneel sb_write_intmap(cpuid, INTSRC_MAILBOX3, intrnum); 129203697Sneel sb_enable_intsrc(cpuid, INTSRC_MAILBOX3); 130203697Sneel } 131203697Sneel#endif 132203510Sneel } 133203510Sneel} 134203510Sneel 135203510Sneelstatic void 136195333Simpmips_init(void) 137195333Simp{ 138216318Sgonzo int i, j, cfe_mem_idx, tmp; 139195333Simp uint64_t maxmem; 140195333Simp 141195333Simp#ifdef CFE_ENV 142195333Simp cfe_env_init(); 143195333Simp#endif 144195333Simp 145195333Simp TUNABLE_INT_FETCH("boothowto", &boothowto); 146195333Simp 147195333Simp if (boothowto & RB_VERBOSE) 148195333Simp bootverbose++; 149195333Simp 150195333Simp#ifdef MAXMEM 151195333Simp tmp = MAXMEM; 152195333Simp#else 153195333Simp tmp = 0; 154195333Simp#endif 155195333Simp TUNABLE_INT_FETCH("hw.physmem", &tmp); 156195333Simp maxmem = (uint64_t)tmp * 1024; 157195333Simp 158207131Sjmallett /* 159207131Sjmallett * XXX 160207131Sjmallett * If we used vm_paddr_t consistently in pmap, etc., we could 161207131Sjmallett * use 64-bit page numbers on !n64 systems, too, like i386 162207131Sjmallett * does with PAE. 163207131Sjmallett */ 164207131Sjmallett#if !defined(__mips_n64) 165207131Sjmallett if (maxmem == 0 || maxmem > 0xffffffff) 166207131Sjmallett maxmem = 0xffffffff; 167207131Sjmallett#endif 168207131Sjmallett 169195333Simp#ifdef CFE 170195333Simp /* 171195333Simp * Query DRAM memory map from CFE. 172195333Simp */ 173195333Simp physmem = 0; 174195333Simp cfe_mem_idx = 0; 175195333Simp for (i = 0; i < 10; i += 2) { 176195333Simp int result; 177195333Simp uint64_t addr, len, type; 178195333Simp 179195333Simp result = cfe_enummem(cfe_mem_idx++, 0, &addr, &len, &type); 180195333Simp if (result < 0) { 181195333Simp phys_avail[i] = phys_avail[i + 1] = 0; 182195333Simp break; 183195333Simp } 184195333Simp 185195333Simp KASSERT(type == CFE_MI_AVAILABLE, 186195333Simp ("CFE DRAM region is not available?")); 187195333Simp 188195333Simp if (bootverbose) 189210910Sneel printf("cfe_enummem: 0x%016jx/%ju.\n", addr, len); 190195333Simp 191195333Simp if (maxmem != 0) { 192195333Simp if (addr >= maxmem) { 193210910Sneel printf("Ignoring %ju bytes of memory at 0x%jx " 194195333Simp "that is above maxmem %dMB\n", 195195333Simp len, addr, 196195333Simp (int)(maxmem / (1024 * 1024))); 197195333Simp continue; 198195333Simp } 199195333Simp 200195333Simp if (addr + len > maxmem) { 201210910Sneel printf("Ignoring %ju bytes of memory " 202195333Simp "that is above maxmem %dMB\n", 203195333Simp (addr + len) - maxmem, 204195333Simp (int)(maxmem / (1024 * 1024))); 205195333Simp len = maxmem - addr; 206195333Simp } 207195333Simp } 208195333Simp 209195333Simp phys_avail[i] = addr; 210195333Simp if (i == 0 && addr == 0) { 211195333Simp /* 212195333Simp * If this is the first physical memory segment probed 213195333Simp * from CFE, omit the region at the start of physical 214195333Simp * memory where the kernel has been loaded. 215195333Simp */ 216202954Sgonzo phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end); 217195333Simp } 218195333Simp phys_avail[i + 1] = addr + len; 219195333Simp physmem += len; 220195333Simp } 221195333Simp 222195333Simp realmem = btoc(physmem); 223195333Simp#endif 224195333Simp 225216320Sgonzo for (j = 0; j < i; j++) 226216318Sgonzo dump_avail[j] = phys_avail[j]; 227216318Sgonzo 228195333Simp physmem = realmem; 229195333Simp 230195333Simp init_param1(); 231195333Simp init_param2(physmem); 232195333Simp mips_cpu_init(); 233203000Sneel 234203000Sneel /* 235204689Sneel * Sibyte has a L1 data cache coherent with DMA. This includes 236204689Sneel * on-chip network interfaces as well as PCI/HyperTransport bus 237204689Sneel * masters. 238204689Sneel */ 239204689Sneel cpuinfo.cache_coherent_dma = TRUE; 240204689Sneel 241204689Sneel /* 242203000Sneel * XXX 243203000Sneel * The kernel is running in 32-bit mode but the CFE is running in 244203000Sneel * 64-bit mode. So the SR_KX bit in the status register is turned 245203000Sneel * on by the CFE every time we call into it - for e.g. CFE_CONSOLE. 246203000Sneel * 247203000Sneel * This means that if get a TLB miss for any address above 0xc0000000 248203000Sneel * and the SR_KX bit is set then we will end up in the XTLB exception 249203000Sneel * vector. 250203000Sneel * 251203000Sneel * For now work around this by copying the TLB exception handling 252203000Sneel * code to the XTLB exception vector. 253203000Sneel */ 254203000Sneel { 255232615Sjmallett bcopy(MipsTLBMiss, (void *)MIPS_XTLB_MISS_EXC_VEC, 256203000Sneel MipsTLBMissEnd - MipsTLBMiss); 257203000Sneel 258203000Sneel mips_icache_sync_all(); 259203000Sneel mips_dcache_wbinv_all(); 260203000Sneel } 261203000Sneel 262195333Simp pmap_bootstrap(); 263195333Simp mips_proc0_init(); 264195333Simp mutex_init(); 265195333Simp 266195333Simp kdb_init(); 267195333Simp#ifdef KDB 268195333Simp if (boothowto & RB_KDB) 269195333Simp kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 270195333Simp#endif 271195333Simp} 272195333Simp 273195333Simpvoid 274195333Simpplatform_reset(void) 275195333Simp{ 276195333Simp 277195333Simp /* 278195333Simp * XXX SMP 279195333Simp * XXX flush data caches 280195333Simp */ 281195333Simp sb_system_reset(); 282195333Simp} 283195333Simp 284202864Sneelstatic void 285202864Sneelkseg0_map_coherent(void) 286202864Sneel{ 287202864Sneel uint32_t config; 288202864Sneel const int CFG_K0_COHERENT = 5; 289202864Sneel 290202864Sneel config = mips_rd_config(); 291232615Sjmallett config &= ~MIPS_CONFIG_K0_MASK; 292202864Sneel config |= CFG_K0_COHERENT; 293202864Sneel mips_wr_config(config); 294202864Sneel} 295202864Sneel 296203697Sneel#ifdef SMP 297195333Simpvoid 298203697Sneelplatform_ipi_send(int cpuid) 299203697Sneel{ 300203697Sneel KASSERT(cpuid == 0 || cpuid == 1, 301203697Sneel ("platform_ipi_send: invalid cpuid %d", cpuid)); 302203697Sneel 303203697Sneel sb_set_mailbox(cpuid, 1ULL); 304203697Sneel} 305203697Sneel 306203697Sneelvoid 307203697Sneelplatform_ipi_clear(void) 308203697Sneel{ 309203697Sneel int cpuid; 310203697Sneel 311203697Sneel cpuid = PCPU_GET(cpuid); 312203697Sneel sb_clear_mailbox(cpuid, 1ULL); 313203697Sneel} 314203697Sneel 315203697Sneelint 316203697Sneelplatform_ipi_intrnum(void) 317203697Sneel{ 318203697Sneel 319203697Sneel return (4); 320203697Sneel} 321203697Sneel 322208249Srrsstruct cpu_group * 323208249Srrsplatform_smp_topo(void) 324208249Srrs{ 325208253Sneel 326208249Srrs return (smp_topo_none()); 327208249Srrs} 328208249Srrs 329203697Sneelvoid 330203697Sneelplatform_init_ap(int cpuid) 331203697Sneel{ 332208249Srrs int ipi_int_mask, clock_int_mask; 333203697Sneel 334203697Sneel KASSERT(cpuid == 1, ("AP has an invalid cpu id %d", cpuid)); 335203697Sneel 336203697Sneel /* 337203697Sneel * Make sure that kseg0 is mapped cacheable-coherent 338203697Sneel */ 339203697Sneel kseg0_map_coherent(); 340203697Sneel 341203697Sneel sb_intr_init(cpuid); 342208249Srrs 343208249Srrs /* 344208249Srrs * Unmask the clock and ipi interrupts. 345208249Srrs */ 346208249Srrs clock_int_mask = hard_int_mask(5); 347208249Srrs ipi_int_mask = hard_int_mask(platform_ipi_intrnum()); 348212632Sneel set_intr_mask(ipi_int_mask | clock_int_mask); 349203697Sneel} 350203697Sneel 351203697Sneelint 352203697Sneelplatform_start_ap(int cpuid) 353203697Sneel{ 354203697Sneel#ifdef CFE 355203697Sneel int error; 356203697Sneel 357203697Sneel if ((error = cfe_cpu_start(cpuid, mpentry, 0, 0, 0))) { 358203697Sneel printf("cfe_cpu_start error: %d\n", error); 359203697Sneel return (-1); 360203697Sneel } else { 361203697Sneel return (0); 362203697Sneel } 363203697Sneel#else 364203697Sneel return (-1); 365203697Sneel#endif /* CFE */ 366203697Sneel} 367203697Sneel#endif /* SMP */ 368203697Sneel 369205364Sneelstatic u_int 370205364Sneelsb_get_timecount(struct timecounter *tc) 371205364Sneel{ 372205364Sneel 373205364Sneel return ((u_int)sb_zbbus_cycle_count()); 374205364Sneel} 375205364Sneel 376205364Sneelstatic void 377205364Sneelsb_timecounter_init(void) 378205364Sneel{ 379205364Sneel static struct timecounter sb_timecounter = { 380205364Sneel sb_get_timecount, 381205364Sneel NULL, 382205364Sneel ~0u, 383205364Sneel 0, 384205364Sneel "sibyte_zbbus_counter", 385205364Sneel 2000 386205364Sneel }; 387205364Sneel 388205364Sneel /* 389205364Sneel * The ZBbus cycle counter runs at half the cpu frequency. 390205364Sneel */ 391205364Sneel sb_timecounter.tc_frequency = sb_cpu_speed() / 2; 392205364Sneel platform_timecounter = &sb_timecounter; 393205364Sneel} 394205364Sneel 395203697Sneelvoid 396201631Sneelplatform_start(__register_t a0, __register_t a1, __register_t a2, 397201631Sneel __register_t a3) 398195333Simp{ 399202864Sneel /* 400202864Sneel * Make sure that kseg0 is mapped cacheable-coherent 401202864Sneel */ 402202864Sneel kseg0_map_coherent(); 403202864Sneel 404195333Simp /* clear the BSS and SBSS segments */ 405195333Simp memset(&edata, 0, (vm_offset_t)&end - (vm_offset_t)&edata); 406202954Sgonzo mips_postboot_fixup(); 407195333Simp 408203510Sneel sb_intr_init(0); 409205364Sneel sb_timecounter_init(); 410203510Sneel 411201845Simp /* Initialize pcpu stuff */ 412201881Simp mips_pcpu0_init(); 413201845Simp 414195333Simp#ifdef CFE 415195333Simp /* 416195333Simp * Initialize CFE firmware trampolines before 417195333Simp * we initialize the low-level console. 418201631Sneel * 419201631Sneel * CFE passes the following values in registers: 420201631Sneel * a0: firmware handle 421201631Sneel * a2: firmware entry point 422201631Sneel * a3: entry point seal 423195333Simp */ 424201631Sneel if (a3 == CFE_EPTSEAL) 425201631Sneel cfe_init(a0, a2); 426195333Simp#endif 427195333Simp cninit(); 428195333Simp 429195333Simp mips_init(); 430195333Simp 431195333Simp mips_timer_init_params(sb_cpu_speed(), 0); 432195333Simp} 433