rt305x_gpio.h revision 256281
148411Swes/*- 248411Swes * Copyright (c) 2010 Aleksandr Rybalko. 348411Swes * All rights reserved. 448411Swes * 548411Swes * Redistribution and use in source and binary forms, with or without 648411Swes * modification, are permitted provided that the following conditions 748411Swes * are met: 848411Swes * 1. Redistributions of source code must retain the above copyright 948411Swes * notice, this list of conditions and the following disclaimer. 1048411Swes * 2. Redistributions in binary form must reproduce the above copyright 1148411Swes * notice, this list of conditions and the following disclaimer in the 1248411Swes * documentation and/or other materials provided with the distribution. 1348411Swes * 1448411Swes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1548411Swes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1648411Swes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1748411Swes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1848411Swes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1948411Swes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2048411Swes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2148411Swes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2248411Swes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2348411Swes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2448411Swes * SUCH DAMAGE. 2550476Speter * 2648411Swes * $FreeBSD: stable/10/sys/mips/rt305x/rt305x_gpio.h 220297 2011-04-03 14:39:55Z adrian $ 2748411Swes */ 2848411Swes#ifndef _RT305X_GPIO_H_ 2948411Swes#define _RT305X_GPIO_H_ 3048411Swes 3148411Swes#define NGPIO 52 3248421Smpp 3359460Sphantom#define RGMII_GPIO_MODE_MASK (0x0fffULL<<40) 3459460Sphantom#define SDRAM_GPIO_MODE_MASK (0xffffULL<<24) 3548411Swes#define MDIO_GPIO_MODE_MASK (0x0003ULL<<22) 3684306Sru#define JTAG_GPIO_MODE_MASK (0x001fULL<<17) 3748411Swes#define UARTL_GPIO_MODE_MASK (0x0003ULL<<15) 3855039Sbde#define UARTF_GPIO_MODE_MASK (0x00ffULL<<7) 3948411Swes#define SPI_GPIO_MODE_MASK (0x000fULL<<3) 4048411Swes#define I2C_GPIO_MODE_MASK (0x0003ULL<<1) 4148411Swes 42108028Sru#define GPIO23_00_INT 0x00 /* Programmed I/O Int Status */ 4348411Swes#define GPIO23_00_EDGE 0x04 /* Programmed I/O Edge Status */ 4461988Schris#define GPIO23_00_RENA 0x08 /* Programmed I/O Int on Rising */ 4548411Swes#define GPIO23_00_FENA 0x0C /* Programmed I/O Int on Falling */ 4648411Swes#define GPIO23_00_DATA 0x20 /* Programmed I/O Data */ 4748411Swes#define GPIO23_00_DIR 0x24 /* Programmed I/O Direction */ 48131504Sru#define GPIO23_00_POL 0x28 /* Programmed I/O Pin Polarity */ 49131504Sru#define GPIO23_00_SET 0x2C /* Set PIO Data Bit */ 5079754Sdd#define GPIO23_00_RESET 0x30 /* Clear PIO Data bit */ 51131504Sru#define GPIO23_00_TOG 0x34 /* Toggle PIO Data bit */ 52131504Sru 5348411Swes#define GPIO39_24_INT 0x38 5448411Swes#define GPIO39_24_EDGE 0x3c 5548411Swes#define GPIO39_24_RENA 0x40 5648411Swes#define GPIO39_24_FENA 0x44 57162657Svd#define GPIO39_24_DATA 0x48 5848411Swes#define GPIO39_24_DIR 0x4c 5948411Swes#define GPIO39_24_POL 0x50 6048411Swes#define GPIO39_24_SET 0x54 6148411Swes#define GPIO39_24_RESET 0x58 6248411Swes#define GPIO39_24_TOG 0x5c 6348411Swes 6448411Swes#define GPIO51_40_INT 0x60 6548411Swes#define GPIO51_40_EDGE 0x64 6648411Swes#define GPIO51_40_RENA 0x68 6748411Swes#define GPIO51_40_FENA 0x6C 68108028Sru#define GPIO51_40_DATA 0x70 6948411Swes#define GPIO51_40_DIR 0x74 7048411Swes#define GPIO51_40_POL 0x78 71108087Sru#define GPIO51_40_SET 0x7C 7261988Schris#define GPIO51_40_RESET 0x80 73108087Sru#define GPIO51_40_TOG 0x84 7448411Swes 7548411Swes#define GPIO_REG(g, n) \ 7648411Swes ((g<24)?(GPIO23_00_##n):(g<40)?(GPIO39_24_##n):(GPIO51_40_##n)) 7749828Smpp#define GPIO_MASK(g) \ 7849828Smpp ((g<24)?(1<<g):(g<40)?(1<<(g-24)):(1<<(g-40))) 7948411Swes#define GPIO_BIT_SHIFT(g) ((g<24)?(g):(g<40)?(g-24):(g-40)) 8049828Smpp 8148411Swes#define GPIO_READ(r, g, n) \ 8249828Smpp bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) 8348411Swes#define GPIO_WRITE(r, g, n, v) \ 84105864Ssheldonh bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), v) 85105864Ssheldonh#define GPIO_READ_ALL(r, n) \ 8648411Swes (((uint64_t)bus_read_4(r->gpio_mem_res, GPIO23_00_##n)) | \ 87108028Sru (((uint64_t)bus_read_4(r->gpio_mem_res, GPIO39_24_##n)) << 24) |\ 8848411Swes (((uint64_t)bus_read_4(r->gpio_mem_res, GPIO51_40_##n)) << 40)) 89108028Sru#define GPIO_WRITE_ALL(r, n, v) \ 9048411Swes {bus_write_4(r->gpio_mem_res,GPIO23_00_##n, v &0x00ffffff);\ 91109174Stjr bus_write_4(r->gpio_mem_res, GPIO39_24_##n, (v>>24)&0x0000ffff);\ 9248411Swes bus_write_4(r->gpio_mem_res, GPIO51_40_##n, (v>>40)&0x00000fff);} 9348411Swes 9448411Swes 95108028Sru#define GPIO_BIT_CLR(r, g, n) \ 96108028Sru bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), \ 9748411Swes bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) & ~GPIO_MASK(g)) 9849828Smpp#define GPIO_BIT_SET(r, g, n) \ 9948411Swes bus_write_4(r->gpio_mem_res, GPIO_REG(g, n), \ 10048411Swes bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) | GPIO_MASK(g)) 101267774Sbapt 102#define GPIO_BIT_GET(r, g, n) \ 103 ((bus_read_4(r->gpio_mem_res, GPIO_REG(g, n)) >> \ 104 GPIO_BIT_SHIFT(g)) & 1) 105 106#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->gpio_mtx) 107#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->gpio_mtx) 108#define GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->gpio_mtx, MA_OWNED) 109 110#endif /* _RT305X_GPIO_H_ */ 111 112