1233545Sjchandra/*- 2233545Sjchandra * Copyright (c) 2003-2012 Broadcom Corporation 3233545Sjchandra * All Rights Reserved 4233545Sjchandra * 5233545Sjchandra * Redistribution and use in source and binary forms, with or without 6233545Sjchandra * modification, are permitted provided that the following conditions 7233545Sjchandra * are met: 8233545Sjchandra * 9233545Sjchandra * 1. Redistributions of source code must retain the above copyright 10233545Sjchandra * notice, this list of conditions and the following disclaimer. 11233545Sjchandra * 2. Redistributions in binary form must reproduce the above copyright 12233545Sjchandra * notice, this list of conditions and the following disclaimer in 13233545Sjchandra * the documentation and/or other materials provided with the 14233545Sjchandra * distribution. 15233545Sjchandra * 16233545Sjchandra * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR 17233545Sjchandra * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18233545Sjchandra * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19233545Sjchandra * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE 20233545Sjchandra * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21233545Sjchandra * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22233545Sjchandra * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 23233545Sjchandra * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24233545Sjchandra * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 25233545Sjchandra * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 26233545Sjchandra * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27233545Sjchandra * 28233545Sjchandra * $FreeBSD: releng/10.3/sys/mips/nlm/hal/poe.h 233545 2012-03-27 14:05:12Z jchandra $ 29233545Sjchandra */ 30233545Sjchandra 31233545Sjchandra#ifndef __NLM_POE_H__ 32233545Sjchandra#define __NLM_POE_H__ 33233545Sjchandra 34233545Sjchandra/** 35233545Sjchandra* @file_name poe.h 36233545Sjchandra* @author Netlogic Microsystems 37233545Sjchandra* @brief Basic definitions of XLP Packet Order Engine 38233545Sjchandra*/ 39233545Sjchandra 40233545Sjchandra/* POE specific registers */ 41233545Sjchandra#define POE_CL0_ENQ_SPILL_BASE_LO 0x0 42233545Sjchandra#define POE_CL1_ENQ_SPILL_BASE_LO 0x2 43233545Sjchandra#define POE_CL2_ENQ_SPILL_BASE_LO 0x4 44233545Sjchandra#define POE_CL3_ENQ_SPILL_BASE_LO 0x6 45233545Sjchandra#define POE_CL4_ENQ_SPILL_BASE_LO 0x8 46233545Sjchandra#define POE_CL5_ENQ_SPILL_BASE_LO 0xa 47233545Sjchandra#define POE_CL6_ENQ_SPILL_BASE_LO 0xc 48233545Sjchandra#define POE_CL7_ENQ_SPILL_BASE_LO 0xe 49233545Sjchandra#define POE_CL0_ENQ_SPILL_BASE_HI 0x1 50233545Sjchandra#define POE_CL1_ENQ_SPILL_BASE_HI 0x3 51233545Sjchandra#define POE_CL2_ENQ_SPILL_BASE_HI 0x5 52233545Sjchandra#define POE_CL3_ENQ_SPILL_BASE_HI 0x7 53233545Sjchandra#define POE_CL4_ENQ_SPILL_BASE_HI 0x9 54233545Sjchandra#define POE_CL5_ENQ_SPILL_BASE_HI 0xb 55233545Sjchandra#define POE_CL6_ENQ_SPILL_BASE_HI 0xd 56233545Sjchandra#define POE_CL7_ENQ_SPILL_BASE_HI 0xf 57233545Sjchandra#define POE_CL0_DEQ_SPILL_BASE_LO 0x10 58233545Sjchandra#define POE_CL1_DEQ_SPILL_BASE_LO 0x12 59233545Sjchandra#define POE_CL2_DEQ_SPILL_BASE_LO 0x14 60233545Sjchandra#define POE_CL3_DEQ_SPILL_BASE_LO 0x16 61233545Sjchandra#define POE_CL4_DEQ_SPILL_BASE_LO 0x18 62233545Sjchandra#define POE_CL5_DEQ_SPILL_BASE_LO 0x1a 63233545Sjchandra#define POE_CL6_DEQ_SPILL_BASE_LO 0x1c 64233545Sjchandra#define POE_CL7_DEQ_SPILL_BASE_LO 0x1e 65233545Sjchandra#define POE_CL0_DEQ_SPILL_BASE_HI 0x11 66233545Sjchandra#define POE_CL1_DEQ_SPILL_BASE_HI 0x13 67233545Sjchandra#define POE_CL2_DEQ_SPILL_BASE_HI 0x15 68233545Sjchandra#define POE_CL3_DEQ_SPILL_BASE_HI 0x17 69233545Sjchandra#define POE_CL4_DEQ_SPILL_BASE_HI 0x19 70233545Sjchandra#define POE_CL5_DEQ_SPILL_BASE_HI 0x1b 71233545Sjchandra#define POE_CL6_DEQ_SPILL_BASE_HI 0x1d 72233545Sjchandra#define POE_CL7_DEQ_SPILL_BASE_HI 0x1f 73233545Sjchandra#define POE_MSG_STORAGE_BASE_ADDR_LO 0x20 74233545Sjchandra#define POE_MSG_STORAGE_BASE_ADDR_HI 0x21 75233545Sjchandra#define POE_FBP_BASE_ADDR_LO 0x22 76233545Sjchandra#define POE_FBP_BASE_ADDR_HI 0x23 77233545Sjchandra#define POE_CL0_ENQ_SPILL_MAXLINE_LO 0x24 78233545Sjchandra#define POE_CL1_ENQ_SPILL_MAXLINE_LO 0x25 79233545Sjchandra#define POE_CL2_ENQ_SPILL_MAXLINE_LO 0x26 80233545Sjchandra#define POE_CL3_ENQ_SPILL_MAXLINE_LO 0x27 81233545Sjchandra#define POE_CL4_ENQ_SPILL_MAXLINE_LO 0x28 82233545Sjchandra#define POE_CL5_ENQ_SPILL_MAXLINE_LO 0x29 83233545Sjchandra#define POE_CL6_ENQ_SPILL_MAXLINE_LO 0x2a 84233545Sjchandra#define POE_CL7_ENQ_SPILL_MAXLINE_LO 0x2b 85233545Sjchandra#define POE_CL0_ENQ_SPILL_MAXLINE_HI 0x2c 86233545Sjchandra#define POE_CL1_ENQ_SPILL_MAXLINE_HI 0x2d 87233545Sjchandra#define POE_CL2_ENQ_SPILL_MAXLINE_HI 0x2e 88233545Sjchandra#define POE_CL3_ENQ_SPILL_MAXLINE_HI 0x2f 89233545Sjchandra#define POE_CL4_ENQ_SPILL_MAXLINE_HI 0x30 90233545Sjchandra#define POE_CL5_ENQ_SPILL_MAXLINE_HI 0x31 91233545Sjchandra#define POE_CL6_ENQ_SPILL_MAXLINE_HI 0x32 92233545Sjchandra#define POE_CL7_ENQ_SPILL_MAXLINE_HI 0x33 93233545Sjchandra#define POE_MAX_FLOW_MSG0 0x40 94233545Sjchandra#define POE_MAX_FLOW_MSG1 0x41 95233545Sjchandra#define POE_MAX_FLOW_MSG2 0x42 96233545Sjchandra#define POE_MAX_FLOW_MSG3 0x43 97233545Sjchandra#define POE_MAX_FLOW_MSG4 0x44 98233545Sjchandra#define POE_MAX_FLOW_MSG5 0x45 99233545Sjchandra#define POE_MAX_FLOW_MSG6 0x46 100233545Sjchandra#define POE_MAX_FLOW_MSG7 0x47 101233545Sjchandra#define POE_MAX_MSG_CL0 0x48 102233545Sjchandra#define POE_MAX_MSG_CL1 0x49 103233545Sjchandra#define POE_MAX_MSG_CL2 0x4a 104233545Sjchandra#define POE_MAX_MSG_CL3 0x4b 105233545Sjchandra#define POE_MAX_MSG_CL4 0x4c 106233545Sjchandra#define POE_MAX_MSG_CL5 0x4d 107233545Sjchandra#define POE_MAX_MSG_CL6 0x4e 108233545Sjchandra#define POE_MAX_MSG_CL7 0x4f 109233545Sjchandra#define POE_MAX_LOC_BUF_STG_CL0 0x50 110233545Sjchandra#define POE_MAX_LOC_BUF_STG_CL1 0x51 111233545Sjchandra#define POE_MAX_LOC_BUF_STG_CL2 0x52 112233545Sjchandra#define POE_MAX_LOC_BUF_STG_CL3 0x53 113233545Sjchandra#define POE_MAX_LOC_BUF_STG_CL4 0x54 114233545Sjchandra#define POE_MAX_LOC_BUF_STG_CL5 0x55 115233545Sjchandra#define POE_MAX_LOC_BUF_STG_CL6 0x56 116233545Sjchandra#define POE_MAX_LOC_BUF_STG_CL7 0x57 117233545Sjchandra#define POE_ENQ_MSG_COUNT0_SIZE 0x58 118233545Sjchandra#define POE_ENQ_MSG_COUNT1_SIZE 0x59 119233545Sjchandra#define POE_ENQ_MSG_COUNT2_SIZE 0x5a 120233545Sjchandra#define POE_ENQ_MSG_COUNT3_SIZE 0x5b 121233545Sjchandra#define POE_ENQ_MSG_COUNT4_SIZE 0x5c 122233545Sjchandra#define POE_ENQ_MSG_COUNT5_SIZE 0x5d 123233545Sjchandra#define POE_ENQ_MSG_COUNT6_SIZE 0x5e 124233545Sjchandra#define POE_ENQ_MSG_COUNT7_SIZE 0x5f 125233545Sjchandra#define POE_ERR_MSG_DESCRIP_LO0 0x60 126233545Sjchandra#define POE_ERR_MSG_DESCRIP_LO1 0x62 127233545Sjchandra#define POE_ERR_MSG_DESCRIP_LO2 0x64 128233545Sjchandra#define POE_ERR_MSG_DESCRIP_LO3 0x66 129233545Sjchandra#define POE_ERR_MSG_DESCRIP_HI0 0x61 130233545Sjchandra#define POE_ERR_MSG_DESCRIP_HI1 0x63 131233545Sjchandra#define POE_ERR_MSG_DESCRIP_HI2 0x65 132233545Sjchandra#define POE_ERR_MSG_DESCRIP_HI3 0x67 133233545Sjchandra#define POE_OOO_MSG_CNT_LO 0x68 134233545Sjchandra#define POE_IN_ORDER_MSG_CNT_LO 0x69 135233545Sjchandra#define POE_LOC_BUF_STOR_CNT_LO 0x6a 136233545Sjchandra#define POE_EXT_BUF_STOR_CNT_LO 0x6b 137233545Sjchandra#define POE_LOC_BUF_ALLOC_CNT_LO 0x6c 138233545Sjchandra#define POE_EXT_BUF_ALLOC_CNT_LO 0x6d 139233545Sjchandra#define POE_OOO_MSG_CNT_HI 0x6e 140233545Sjchandra#define POE_IN_ORDER_MSG_CNT_HI 0x6f 141233545Sjchandra#define POE_LOC_BUF_STOR_CNT_HI 0x70 142233545Sjchandra#define POE_EXT_BUF_STOR_CNT_HI 0x71 143233545Sjchandra#define POE_LOC_BUF_ALLOC_CNT_HI 0x72 144233545Sjchandra#define POE_EXT_BUF_ALLOC_CNT_HI 0x73 145233545Sjchandra#define POE_MODE_ERR_FLOW_ID 0x74 146233545Sjchandra#define POE_STATISTICS_ENABLE 0x75 147233545Sjchandra#define POE_MAX_SIZE_FLOW 0x76 148233545Sjchandra#define POE_MAX_SIZE 0x77 149233545Sjchandra#define POE_FBP_SP 0x78 150233545Sjchandra#define POE_FBP_SP_EN 0x79 151233545Sjchandra#define POE_LOC_ALLOC_EN 0x7a 152233545Sjchandra#define POE_EXT_ALLOC_EN 0x7b 153233545Sjchandra#define POE_DISTR_0_DROP_CNT 0xc0 154233545Sjchandra#define POE_DISTR_1_DROP_CNT 0xc1 155233545Sjchandra#define POE_DISTR_2_DROP_CNT 0xc2 156233545Sjchandra#define POE_DISTR_3_DROP_CNT 0xc3 157233545Sjchandra#define POE_DISTR_4_DROP_CNT 0xc4 158233545Sjchandra#define POE_DISTR_5_DROP_CNT 0xc5 159233545Sjchandra#define POE_DISTR_6_DROP_CNT 0xc6 160233545Sjchandra#define POE_DISTR_7_DROP_CNT 0xc7 161233545Sjchandra#define POE_DISTR_8_DROP_CNT 0xc8 162233545Sjchandra#define POE_DISTR_9_DROP_CNT 0xc9 163233545Sjchandra#define POE_DISTR_10_DROP_CNT 0xca 164233545Sjchandra#define POE_DISTR_11_DROP_CNT 0xcb 165233545Sjchandra#define POE_DISTR_12_DROP_CNT 0xcc 166233545Sjchandra#define POE_DISTR_13_DROP_CNT 0xcd 167233545Sjchandra#define POE_DISTR_14_DROP_CNT 0xce 168233545Sjchandra#define POE_DISTR_15_DROP_CNT 0xcf 169233545Sjchandra#define POE_CLASS_0_DROP_CNT 0xd0 170233545Sjchandra#define POE_CLASS_1_DROP_CNT 0xd1 171233545Sjchandra#define POE_CLASS_2_DROP_CNT 0xd2 172233545Sjchandra#define POE_CLASS_3_DROP_CNT 0xd3 173233545Sjchandra#define POE_CLASS_4_DROP_CNT 0xd4 174233545Sjchandra#define POE_CLASS_5_DROP_CNT 0xd5 175233545Sjchandra#define POE_CLASS_6_DROP_CNT 0xd6 176233545Sjchandra#define POE_CLASS_7_DROP_CNT 0xd7 177233545Sjchandra#define POE_DISTR_C0_DROP_CNT 0xd8 178233545Sjchandra#define POE_DISTR_C1_DROP_CNT 0xd9 179233545Sjchandra#define POE_DISTR_C2_DROP_CNT 0xda 180233545Sjchandra#define POE_DISTR_C3_DROP_CNT 0xdb 181233545Sjchandra#define POE_DISTR_C4_DROP_CNT 0xdc 182233545Sjchandra#define POE_DISTR_C5_DROP_CNT 0xdd 183233545Sjchandra#define POE_DISTR_C6_DROP_CNT 0xde 184233545Sjchandra#define POE_DISTR_C7_DROP_CNT 0xdf 185233545Sjchandra#define POE_CPU_DROP_CNT 0xe0 186233545Sjchandra#define POE_MAX_FLOW_DROP_CNT 0xe1 187233545Sjchandra#define POE_INTERRUPT_VEC 0x140 188233545Sjchandra#define POE_INTERRUPT_MASK 0x141 189233545Sjchandra#define POE_FATALERR_MASK 0x142 190233545Sjchandra#define POE_IDI_CFG 0x143 191233545Sjchandra#define POE_TIMEOUT_VALUE 0x144 192233545Sjchandra#define POE_CACHE_ALLOC_EN 0x145 193233545Sjchandra#define POE_FBP_ECC_ERR_CNT 0x146 194233545Sjchandra#define POE_MSG_STRG_ECC_ERR_CNT 0x147 195233545Sjchandra#define POE_FID_INFO_ECC_ERR_CNT 0x148 196233545Sjchandra#define POE_MSG_INFO_ECC_ERR_CNT 0x149 197233545Sjchandra#define POE_LL_ECC_ERR_CNT 0x14a 198233545Sjchandra#define POE_SIZE_ECC_ERR_CNT 0x14b 199233545Sjchandra#define POE_FMN_TXCR_ECC_ERR_CNT 0x14c 200233545Sjchandra#define POE_ENQ_INSPIL_ECC_ERR_CNT 0x14d 201233545Sjchandra#define POE_ENQ_OUTSPIL_ECC_ERR_CNT 0x14e 202233545Sjchandra#define POE_DEQ_OUTSPIL_ECC_ERR_CNT 0x14f 203233545Sjchandra#define POE_ENQ_MSG_SENT 0x150 204233545Sjchandra#define POE_ENQ_MSG_CNT 0x151 205233545Sjchandra#define POE_FID_RDATA 0x152 206233545Sjchandra#define POE_FID_WDATA 0x153 207233545Sjchandra#define POE_FID_CMD 0x154 208233545Sjchandra#define POE_FID_ADDR 0x155 209233545Sjchandra#define POE_MSG_INFO_CMD 0x156 210233545Sjchandra#define POE_MSG_INFO_ADDR 0x157 211233545Sjchandra#define POE_MSG_INFO_RDATA 0x158 212233545Sjchandra#define POE_LL_CMD 0x159 213233545Sjchandra#define POE_LL_ADDR 0x15a 214233545Sjchandra#define POE_LL_RDATA 0x15b 215233545Sjchandra#define POE_MSG_STG_CMD 0x15c 216233545Sjchandra#define POE_MSG_STG_ADDR 0x15d 217233545Sjchandra#define POE_MSG_STG_RDATA 0x15e 218233545Sjchandra#define POE_DISTR_THRESHOLD_0 0x1c0 219233545Sjchandra#define POE_DISTR_THRESHOLD_1 0x1c1 220233545Sjchandra#define POE_DISTR_THRESHOLD_2 0x1c2 221233545Sjchandra#define POE_DISTR_THRESHOLD_3 0x1c3 222233545Sjchandra#define POE_DISTR_THRESHOLD_4 0x1c4 223233545Sjchandra#define POE_DISTR_THRESHOLD(i) (0x1c0 + (i)) 224233545Sjchandra#define POE_DISTR_EN 0x1c5 225233545Sjchandra#define POE_ENQ_SPILL_THOLD 0x1c8 226233545Sjchandra#define POE_DEQ_SPILL_THOLD 0x1c9 227233545Sjchandra#define POE_DEQ_SPILL_TIMER 0x1ca 228233545Sjchandra#define POE_DISTR_CLASS_DROP_EN 0x1cb 229233545Sjchandra#define POE_DISTR_VEC_DROP_EN 0x1cc 230233545Sjchandra#define POE_DISTR_DROP_TIMER 0x1cd 231233545Sjchandra#define POE_ERROR_LOG_W0 0x1ce 232233545Sjchandra#define POE_ERROR_LOG_W1 0x1cf 233233545Sjchandra#define POE_ERROR_LOG_W2 0x1d0 234233545Sjchandra#define POE_ERR_INJ_CTRL0 0x1d1 235233545Sjchandra#define POE_TX_TIMER 0x1d4 236233545Sjchandra 237233545Sjchandra#define NUM_DIST_VEC 16 238233545Sjchandra#define NUM_WORDS_PER_DV 16 239233545Sjchandra#define MAX_DV_TBL_ENTRIES (NUM_DIST_VEC * NUM_WORDS_PER_DV) 240233545Sjchandra#define POE_DIST_THRESHOLD_VAL 0xa 241233545Sjchandra 242233545Sjchandra/* 243233545Sjchandra * POE distribution vectors 244233545Sjchandra * 245233545Sjchandra * Each vector is 512 bit with msb indicating vc 512 and lsb indicating vc 0 246233545Sjchandra * 512-bit-vector is specified as 16 32-bit words. 247233545Sjchandra * Left most word has the vc range 511-479 right most word has vc range 31 - 0 248233545Sjchandra * Each word has the MSB select higer vc number and LSB select lower vc num 249233545Sjchandra */ 250233545Sjchandra#define POE_DISTVECT_BASE 0x100 251233545Sjchandra#define POE_DISTVECT(vec) (POE_DISTVECT_BASE + 16 * (vec)) 252233545Sjchandra#define POE_DISTVECT_OFFSET(node,cpu) (4 * (3 - (node)) + (3 - (cpu)/8)) 253233545Sjchandra#define POE_DISTVECT_SHIFT(node,cpu) (((cpu) % 8 ) * 4) 254233545Sjchandra 255233545Sjchandra#if !defined(LOCORE) && !defined(__ASSEMBLY__) 256233545Sjchandra 257233545Sjchandra#define nlm_read_poe_reg(b, r) nlm_read_reg(b, r) 258233545Sjchandra#define nlm_write_poe_reg(b, r, v) nlm_write_reg(b, r, v) 259233545Sjchandra#define nlm_read_poedv_reg(b, r) nlm_read_reg_xkphys(b, r) 260233545Sjchandra#define nlm_write_poedv_reg(b, r, v) nlm_write_reg_xkphys(b, r, v) 261233545Sjchandra#define nlm_get_poe_pcibase(node) \ 262233545Sjchandra nlm_pcicfg_base(XLP_IO_POE_OFFSET(node)) 263233545Sjchandra#define nlm_get_poe_regbase(node) \ 264233545Sjchandra (nlm_get_poe_pcibase(node) + XLP_IO_PCI_HDRSZ) 265233545Sjchandra#define nlm_get_poedv_regbase(node) \ 266233545Sjchandra nlm_xkphys_map_pcibar0(nlm_get_poe_pcibase(node)) 267233545Sjchandra 268233545Sjchandrastatic __inline int 269233545Sjchandranlm_poe_max_flows(uint64_t poe_pcibase) 270233545Sjchandra{ 271233545Sjchandra return (nlm_read_reg(poe_pcibase, XLP_PCI_DEVINFO_REG0)); 272233545Sjchandra} 273233545Sjchandra 274233545Sjchandra/* 275233545Sjchandra * Helper function, calculate the distribution vector 276233545Sjchandra * cm0, cm1, cm2, cm3 : CPU masks for nodes 0..3 277233545Sjchandra * thr_vcmask: destination VCs for a thread 278233545Sjchandra */ 279233545Sjchandrastatic __inline void 280233545Sjchandranlm_calc_poe_distvec(uint32_t cm0, uint32_t cm1, uint32_t cm2, uint32_t cm3, 281233545Sjchandra uint32_t thr_vcmask, uint32_t *distvec) 282233545Sjchandra{ 283233545Sjchandra uint32_t cpumask = 0, val; 284233545Sjchandra int i, cpu, node, startcpu, index; 285233545Sjchandra 286233545Sjchandra thr_vcmask &= 0xf; 287233545Sjchandra for (node = 0; node < XLP_MAX_NODES; node++) { 288233545Sjchandra switch (node) { 289233545Sjchandra case 0: cpumask = cm0; break; 290233545Sjchandra case 1: cpumask = cm1; break; 291233545Sjchandra case 2: cpumask = cm2; break; 292233545Sjchandra case 3: cpumask = cm3; break; 293233545Sjchandra } 294233545Sjchandra 295233545Sjchandra for (i = 0; i < 4; i++) { 296233545Sjchandra val = 0; 297233545Sjchandra startcpu = 31 - i * 8; 298233545Sjchandra for (cpu = startcpu; cpu >= startcpu - 7; cpu--) { 299233545Sjchandra val <<= 4; 300233545Sjchandra if (cpumask & (1U << cpu)) 301233545Sjchandra val |= thr_vcmask; 302233545Sjchandra } 303233545Sjchandra index = POE_DISTVECT_OFFSET(node, startcpu); 304233545Sjchandra distvec[index] = val; 305233545Sjchandra } 306233545Sjchandra } 307233545Sjchandra} 308233545Sjchandra 309233545Sjchandrastatic __inline int 310233545Sjchandranlm_write_poe_distvec(uint64_t poedv_base, int vec, uint32_t *distvec) 311233545Sjchandra{ 312233545Sjchandra uint32_t reg; 313233545Sjchandra int i; 314233545Sjchandra 315233545Sjchandra if (vec < 0 || vec >= NUM_DIST_VEC) 316233545Sjchandra return (-1); 317233545Sjchandra 318233545Sjchandra for (i = 0; i < NUM_WORDS_PER_DV; i++) { 319233545Sjchandra reg = POE_DISTVECT(vec) + i; 320233545Sjchandra nlm_write_poedv_reg(poedv_base, reg, distvec[i]); 321233545Sjchandra } 322233545Sjchandra 323233545Sjchandra return (0); 324233545Sjchandra} 325233545Sjchandra 326233545Sjchandrastatic __inline void 327233545Sjchandranlm_config_poe(uint64_t poe_base, uint64_t poedv_base) 328233545Sjchandra{ 329233545Sjchandra uint32_t zerodv[NUM_WORDS_PER_DV]; 330233545Sjchandra int i; 331233545Sjchandra 332233545Sjchandra /* First disable distribution vector logic */ 333233545Sjchandra nlm_write_poe_reg(poe_base, POE_DISTR_EN, 0); 334233545Sjchandra 335233545Sjchandra memset(zerodv, 0, sizeof(zerodv)); 336233545Sjchandra for (i = 0; i < NUM_DIST_VEC; i++) 337233545Sjchandra nlm_write_poe_distvec(poedv_base, i, zerodv); 338233545Sjchandra 339233545Sjchandra /* set the threshold */ 340233545Sjchandra for (i = 0; i < 5; i++) 341233545Sjchandra nlm_write_poe_reg(poe_base, POE_DISTR_THRESHOLD(i), 342233545Sjchandra POE_DIST_THRESHOLD_VAL); 343233545Sjchandra 344233545Sjchandra nlm_write_poe_reg(poe_base, POE_DISTR_EN, 1); 345233545Sjchandra 346233545Sjchandra /* always enable local message store */ 347233545Sjchandra nlm_write_poe_reg(poe_base, POE_LOC_ALLOC_EN, 1); 348233545Sjchandra 349233545Sjchandra nlm_write_poe_reg(poe_base, POE_TX_TIMER, 0x3); 350233545Sjchandra} 351233545Sjchandra#endif /* !(LOCORE) && !(__ASSEMBLY__) */ 352233545Sjchandra#endif 353