bridge.h revision 296373
1234449Sobrien/*- 268349Sobrien * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3159764Sobrien * reserved. 4234449Sobrien * 5133359Sobrien * Redistribution and use in source and binary forms, with or without 6133359Sobrien * modification, are permitted provided that the following conditions are 7133359Sobrien * met: 868349Sobrien * 9133359Sobrien * 1. Redistributions of source code must retain the above copyright 10133359Sobrien * notice, this list of conditions and the following disclaimer. 11133359Sobrien * 2. Redistributions in binary form must reproduce the above copyright 12133359Sobrien * notice, this list of conditions and the following disclaimer in 1368349Sobrien * the documentation and/or other materials provided with the 14234449Sobrien * distribution. 15234449Sobrien * 16234449Sobrien * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND 17234449Sobrien * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18234449Sobrien * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19234449Sobrien * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE 20234449Sobrien * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21175296Sobrien * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22234449Sobrien * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23139368Sobrien * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24159764Sobrien * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25159764Sobrien * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26159764Sobrien * THE POSSIBILITY OF SUCH DAMAGE. 27159764Sobrien * 28159764Sobrien * NETLOGIC_BSD 29159764Sobrien * $FreeBSD: releng/10.3/sys/mips/nlm/hal/bridge.h 227722 2011-11-19 14:06:15Z jchandra $ 30159764Sobrien */ 31159764Sobrien 32175296Sobrien#ifndef __NLM_HAL_BRIDGE_H__ 33175296Sobrien#define __NLM_HAL_BRIDGE_H__ 34234449Sobrien 35175296Sobrien/** 36175296Sobrien* @file_name mio.h 37234449Sobrien* @author Netlogic Microsystems 38175296Sobrien* @brief Basic definitions of XLP memory and io subsystem 39175296Sobrien*/ 40159764Sobrien 41175296Sobrien/* 42175296Sobrien * BRIDGE specific registers 43175296Sobrien * 44175296Sobrien * These registers start after the PCIe header, which has 0x40 45175296Sobrien * standard entries 46175296Sobrien */ 47175296Sobrien#define BRIDGE_MODE 0x00 48159764Sobrien#define BRIDGE_PCI_CFG_BASE 0x01 49159764Sobrien#define BRIDGE_PCI_CFG_LIMIT 0x02 50175296Sobrien#define BRIDGE_PCIE_CFG_BASE 0x03 51234449Sobrien#define BRIDGE_PCIE_CFG_LIMIT 0x04 52159764Sobrien#define BRIDGE_BUSNUM_BAR0 0x05 53234449Sobrien#define BRIDGE_BUSNUM_BAR1 0x06 54234449Sobrien#define BRIDGE_BUSNUM_BAR2 0x07 55234449Sobrien#define BRIDGE_BUSNUM_BAR3 0x08 56234449Sobrien#define BRIDGE_BUSNUM_BAR4 0x09 57159764Sobrien#define BRIDGE_BUSNUM_BAR5 0x0a 58159764Sobrien#define BRIDGE_BUSNUM_BAR6 0x0b 59159764Sobrien#define BRIDGE_FLASH_BAR0 0x0c 60159764Sobrien#define BRIDGE_FLASH_BAR1 0x0d 61139368Sobrien#define BRIDGE_FLASH_BAR2 0x0e 62159764Sobrien#define BRIDGE_FLASH_BAR3 0x0f 63159764Sobrien#define BRIDGE_FLASH_LIMIT0 0x10 64159764Sobrien#define BRIDGE_FLASH_LIMIT1 0x11 65159764Sobrien#define BRIDGE_FLASH_LIMIT2 0x12 66159764Sobrien#define BRIDGE_FLASH_LIMIT3 0x13 67159764Sobrien 68159764Sobrien#define BRIDGE_DRAM_BAR(i) (0x14 + (i)) 69139368Sobrien#define BRIDGE_DRAM_BAR0 0x14 70159764Sobrien#define BRIDGE_DRAM_BAR1 0x15 71159764Sobrien#define BRIDGE_DRAM_BAR2 0x16 72159764Sobrien#define BRIDGE_DRAM_BAR3 0x17 73159764Sobrien#define BRIDGE_DRAM_BAR4 0x18 74159764Sobrien#define BRIDGE_DRAM_BAR5 0x19 75159764Sobrien#define BRIDGE_DRAM_BAR6 0x1a 76159764Sobrien#define BRIDGE_DRAM_BAR7 0x1b 77139368Sobrien 78159764Sobrien#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i)) 79159764Sobrien#define BRIDGE_DRAM_LIMIT0 0x1c 80159764Sobrien#define BRIDGE_DRAM_LIMIT1 0x1d 81159764Sobrien#define BRIDGE_DRAM_LIMIT2 0x1e 82159764Sobrien#define BRIDGE_DRAM_LIMIT3 0x1f 83159764Sobrien#define BRIDGE_DRAM_LIMIT4 0x20 84139368Sobrien#define BRIDGE_DRAM_LIMIT5 0x21 85159764Sobrien#define BRIDGE_DRAM_LIMIT6 0x22 86159764Sobrien#define BRIDGE_DRAM_LIMIT7 0x23 87159764Sobrien 88159764Sobrien#define BRIDGE_DRAM_NODE_TRANSLN0 0x24 89139368Sobrien#define BRIDGE_DRAM_NODE_TRANSLN1 0x25 90159764Sobrien#define BRIDGE_DRAM_NODE_TRANSLN2 0x26 91159764Sobrien#define BRIDGE_DRAM_NODE_TRANSLN3 0x27 92159764Sobrien#define BRIDGE_DRAM_NODE_TRANSLN4 0x28 93159764Sobrien#define BRIDGE_DRAM_NODE_TRANSLN5 0x29 94159764Sobrien#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a 95159764Sobrien#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b 96159764Sobrien#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c 97159764Sobrien#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d 98159764Sobrien#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e 99139368Sobrien#define BRIDGE_DRAM_CHNL_TRANSLN3 0x2f 100159764Sobrien#define BRIDGE_DRAM_CHNL_TRANSLN4 0x30 101159764Sobrien#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31 102159764Sobrien#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32 103159764Sobrien#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33 104159764Sobrien#define BRIDGE_PCIEMEM_BASE0 0x34 105159764Sobrien#define BRIDGE_PCIEMEM_BASE1 0x35 106159764Sobrien#define BRIDGE_PCIEMEM_BASE2 0x36 107159764Sobrien#define BRIDGE_PCIEMEM_BASE3 0x37 108159764Sobrien#define BRIDGE_PCIEMEM_LIMIT0 0x38 109159764Sobrien#define BRIDGE_PCIEMEM_LIMIT1 0x39 110159764Sobrien#define BRIDGE_PCIEMEM_LIMIT2 0x3a 111159764Sobrien#define BRIDGE_PCIEMEM_LIMIT3 0x3b 112159764Sobrien#define BRIDGE_PCIEIO_BASE0 0x3c 113234449Sobrien#define BRIDGE_PCIEIO_BASE1 0x3d 114159764Sobrien#define BRIDGE_PCIEIO_BASE2 0x3e 115139368Sobrien#define BRIDGE_PCIEIO_BASE3 0x3f 116159764Sobrien#define BRIDGE_PCIEIO_LIMIT0 0x40 117159764Sobrien#define BRIDGE_PCIEIO_LIMIT1 0x41 118159764Sobrien#define BRIDGE_PCIEIO_LIMIT2 0x42 119159764Sobrien#define BRIDGE_PCIEIO_LIMIT3 0x43 120234449Sobrien#define BRIDGE_PCIEMEM_BASE4 0x44 121159764Sobrien#define BRIDGE_PCIEMEM_BASE5 0x45 122159764Sobrien#define BRIDGE_PCIEMEM_BASE6 0x46 123159764Sobrien#define BRIDGE_PCIEMEM_LIMIT4 0x47 124159764Sobrien#define BRIDGE_PCIEMEM_LIMIT5 0x48 125159764Sobrien#define BRIDGE_PCIEMEM_LIMIT6 0x49 126159764Sobrien#define BRIDGE_PCIEIO_BASE4 0x4a 127159764Sobrien#define BRIDGE_PCIEIO_BASE5 0x4b 128159764Sobrien#define BRIDGE_PCIEIO_BASE6 0x4c 129175296Sobrien#define BRIDGE_PCIEIO_LIMIT4 0x4d 130175296Sobrien#define BRIDGE_PCIEIO_LIMIT5 0x4e 131175296Sobrien#define BRIDGE_PCIEIO_LIMIT6 0x4f 132175296Sobrien#define BRIDGE_NBU_EVENT_CNT_CTL 0x50 133234449Sobrien#define BRIDGE_EVNTCTR1_LOW 0x51 134159764Sobrien#define BRIDGE_EVNTCTR1_HI 0x52 135159764Sobrien#define BRIDGE_EVNT_CNT_CTL2 0x53 136159764Sobrien#define BRIDGE_EVNTCTR2_LOW 0x54 137159764Sobrien#define BRIDGE_EVNTCTR2_HI 0x55 138159764Sobrien#define BRIDGE_TRACEBUF_MATCH0 0x56 139159764Sobrien#define BRIDGE_TRACEBUF_MATCH1 0x57 140159764Sobrien#define BRIDGE_TRACEBUF_MATCH_LOW 0x58 141159764Sobrien#define BRIDGE_TRACEBUF_MATCH_HI 0x59 142159764Sobrien#define BRIDGE_TRACEBUF_CTRL 0x5a 143159764Sobrien#define BRIDGE_TRACEBUF_INIT 0x5b 144159764Sobrien#define BRIDGE_TRACEBUF_ACCESS 0x5c 145159764Sobrien#define BRIDGE_TRACEBUF_READ_DATA0 0x5d 146159764Sobrien#define BRIDGE_TRACEBUF_READ_DATA1 0x5d 147234449Sobrien#define BRIDGE_TRACEBUF_READ_DATA2 0x5f 148159764Sobrien#define BRIDGE_TRACEBUF_READ_DATA3 0x60 149139368Sobrien#define BRIDGE_TRACEBUF_STATUS 0x61 150159764Sobrien#define BRIDGE_ADDRESS_ERROR0 0x62 151159764Sobrien#define BRIDGE_ADDRESS_ERROR1 0x63 152159764Sobrien#define BRIDGE_ADDRESS_ERROR2 0x64 153139368Sobrien#define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65 154234449Sobrien#define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66 155139368Sobrien#define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67 156159764Sobrien#define BRIDGE_LINE_FLUSH0 0x68 157159764Sobrien#define BRIDGE_LINE_FLUSH1 0x69 158159764Sobrien#define BRIDGE_NODE_ID 0x6a 159159764Sobrien#define BRIDGE_ERROR_INTERRUPT_EN 0x6b 160159764Sobrien#define BRIDGE_PCIE0_WEIGHT 0x2c0 161139368Sobrien#define BRIDGE_PCIE1_WEIGHT 0x2c1 162139368Sobrien#define BRIDGE_PCIE2_WEIGHT 0x2c2 163159764Sobrien#define BRIDGE_PCIE3_WEIGHT 0x2c3 164159764Sobrien#define BRIDGE_USB_WEIGHT 0x2c4 165159764Sobrien#define BRIDGE_NET_WEIGHT 0x2c5 166159764Sobrien#define BRIDGE_POE_WEIGHT 0x2c6 167159764Sobrien#define BRIDGE_CMS_WEIGHT 0x2c7 168159764Sobrien#define BRIDGE_DMAENG_WEIGHT 0x2c8 169159764Sobrien#define BRIDGE_SEC_WEIGHT 0x2c9 170159764Sobrien#define BRIDGE_COMP_WEIGHT 0x2ca 171159764Sobrien#define BRIDGE_GIO_WEIGHT 0x2cb 172159764Sobrien#define BRIDGE_FLASH_WEIGHT 0x2cc 173159764Sobrien 174159764Sobrien#if !defined(LOCORE) && !defined(__ASSEMBLY__) 175159764Sobrien 176159764Sobrien#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r) 177159764Sobrien#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v) 178139368Sobrien#define nlm_get_bridge_pcibase(node) \ 179159764Sobrien nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node)) 180159764Sobrien#define nlm_get_bridge_regbase(node) \ 181159764Sobrien (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ) 182175296Sobrien 183159764Sobrien#endif 184159764Sobrien#endif 185133359Sobrien