1178173Simp/* $NetBSD: maltareg.h,v 1.1 2002/03/07 14:44:04 simonb Exp $ */ 2178173Simp 3178173Simp/* 4178173Simp * Copyright 2002 Wasabi Systems, Inc. 5178173Simp * All rights reserved. 6178173Simp * 7178173Simp * Written by Simon Burge for Wasabi Systems, Inc. 8178173Simp * 9178173Simp * Redistribution and use in source and binary forms, with or without 10178173Simp * modification, are permitted provided that the following conditions 11178173Simp * are met: 12178173Simp * 1. Redistributions of source code must retain the above copyright 13178173Simp * notice, this list of conditions and the following disclaimer. 14178173Simp * 2. Redistributions in binary form must reproduce the above copyright 15178173Simp * notice, this list of conditions and the following disclaimer in the 16178173Simp * documentation and/or other materials provided with the distribution. 17178173Simp * 3. All advertising materials mentioning features or use of this software 18178173Simp * must display the following acknowledgement: 19178173Simp * This product includes software developed for the NetBSD Project by 20178173Simp * Wasabi Systems, Inc. 21178173Simp * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22178173Simp * or promote products derived from this software without specific prior 23178173Simp * written permission. 24178173Simp * 25178173Simp * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26178173Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27178173Simp * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28178173Simp * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29178173Simp * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30178173Simp * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31178173Simp * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32178173Simp * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33178173Simp * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34178173Simp * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35178173Simp * POSSIBILITY OF SUCH DAMAGE. 36178173Simp * 37178173Simp * $FreeBSD: releng/10.3/sys/mips/malta/maltareg.h 202175 2010-01-12 21:36:08Z imp $ 38178173Simp */ 39178173Simp 40178173Simp/* 41178173Simp Memory Map 42178173Simp 43178173Simp 0000.0000 * 128MB Typically SDRAM (on Core Board) 44178173Simp 0800.0000 * 256MB Typically PCI 45178173Simp 1800.0000 * 62MB Typically PCI 46178173Simp 1be0.0000 * 2MB Typically System controller's internal registers 47178173Simp 1c00.0000 * 32MB Typically not used 48178173Simp 1e00.0000 4MB Monitor Flash 49178173Simp 1e40.0000 12MB reserved 50178173Simp 1f00.0000 12MB Switches 51178173Simp LEDs 52178173Simp ASCII display 53178173Simp Soft reset 54178173Simp FPGA revision number 55178173Simp CBUS UART (tty2) 56178173Simp General Purpose I/O 57178173Simp I2C controller 58178173Simp 1f10.0000 * 11MB Typically System Controller specific 59178173Simp 1fc0.0000 4MB Maps to Monitor Flash 60178173Simp 1fd0.0000 * 3MB Typically System Controller specific 61178173Simp 62178173Simp * depends on implementation of the Core Board and of software 63178173Simp */ 64178173Simp 65178173Simp/* 66178173Simp CPU interrupts 67178173Simp 68178173Simp NMI South Bridge or NMI button 69178173Simp 0 South Bridge INTR 70178173Simp 1 South Bridge SMI 71178173Simp 2 CBUS UART (tty2) 72178173Simp 3 COREHI (Core Card) 73178173Simp 4 CORELO (Core Card) 74178173Simp 5 Not used, driven inactive (typically CPU internal timer interrupt 75178173Simp 76178173Simp IRQ mapping (as used by YAMON) 77178173Simp 78178173Simp 0 Timer South Bridge 79178173Simp 1 Keyboard SuperIO 80178173Simp 2 Reserved by South Bridge (for cascading) 81178173Simp 3 UART (tty1) SuperIO 82178173Simp 4 UART (tty0) SuperIO 83178173Simp 5 Not used 84178173Simp 6 Floppy Disk SuperIO 85178173Simp 7 Parallel Port SuperIO 86178173Simp 8 Real Time Clock South Bridge 87178173Simp 9 I2C bus South Bridge 88178173Simp 10 PCI A,B,eth PCI slot 1..4, Ethernet 89178173Simp 11 PCI C,audio PCI slot 1..4, Audio, USB (South Bridge) 90178173Simp PCI D,USB 91178173Simp 12 Mouse SuperIO 92178173Simp 13 Reserved by South Bridge 93178173Simp 14 Primary IDE Primary IDE slot 94178173Simp 15 Secondary IDE Secondary IDE slot/Compact flash connector 95178173Simp */ 96178173Simp 97202035Simp#define MALTA_SYSTEMRAM_BASE 0x00000000ul /* System RAM: */ 98178173Simp#define MALTA_SYSTEMRAM_SIZE 0x08000000 /* 128 MByte */ 99178173Simp 100202035Simp#define MALTA_PCIMEM1_BASE 0x08000000ul /* PCI 1 memory: */ 101178173Simp#define MALTA_PCIMEM1_SIZE 0x08000000 /* 128 MByte */ 102178173Simp 103202035Simp#define MALTA_PCIMEM2_BASE 0x10000000ul /* PCI 2 memory: */ 104178173Simp#define MALTA_PCIMEM2_SIZE 0x08000000 /* 128 MByte */ 105178173Simp 106202035Simp#define MALTA_PCIMEM3_BASE 0x18000000ul /* PCI 3 memory */ 107178173Simp#define MALTA_PCIMEM3_SIZE 0x03e00000 /* 62 MByte */ 108178173Simp 109202035Simp#define MALTA_CORECTRL_BASE 0x1be00000ul /* Core control: */ 110178173Simp#define MALTA_CORECTRL_SIZE 0x00200000 /* 2 MByte */ 111178173Simp 112202035Simp#define MALTA_RESERVED_BASE1 0x1c000000ul /* Reserved: */ 113178173Simp#define MALTA_RESERVED_SIZE1 0x02000000 /* 32 MByte */ 114178173Simp 115202035Simp#define MALTA_MONITORFLASH_BASE 0x1e000000ul /* Monitor Flash: */ 116178173Simp#define MALTA_MONITORFLASH_SIZE 0x003e0000 /* 4 MByte */ 117178173Simp#define MALTA_MONITORFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */ 118178173Simp 119202035Simp#define MALTA_FILEFLASH_BASE 0x1e3e0000ul /* File Flash (for monitor): */ 120178173Simp#define MALTA_FILEFLASH_SIZE 0x00020000 /* 128 KByte */ 121178173Simp 122178173Simp#define MALTA_FILEFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */ 123178173Simp 124202035Simp#define MALTA_RESERVED_BASE2 0x1e400000ul /* Reserved: */ 125178173Simp#define MALTA_RESERVED_SIZE2 0x00c00000 /* 12 MByte */ 126178173Simp 127202035Simp#define MALTA_FPGA_BASE 0x1f000000ul /* FPGA: */ 128178173Simp#define MALTA_FPGA_SIZE 0x00c00000 /* 12 MByte */ 129178173Simp 130178173Simp#define MALTA_NMISTATUS (MALTA_FPGA_BASE + 0x24) 131178173Simp#define MALTA_NMI_SB 0x2 /* Pending NMI from the South Bridge */ 132178173Simp#define MALTA_NMI_ONNMI 0x1 /* Pending NMI from the ON/NMI push button */ 133178173Simp 134178173Simp#define MALTA_NMIACK (MALTA_FPGA_BASE + 0x104) 135178173Simp#define MALTA_NMIACK_ONNMI 0x1 /* Write 1 to acknowledge ON/NMI */ 136178173Simp 137178173Simp#define MALTA_SWITCH (MALTA_FPGA_BASE + 0x200) 138178173Simp#define MALTA_SWITCH_MASK 0xff /* settings of DIP switch S2 */ 139178173Simp 140178173Simp#define MALTA_STATUS (MALTA_FPGA_BASE + 0x208) 141178173Simp#define MALTA_ST_MFWR 0x10 /* Monitor Flash is write protected (JP1) */ 142178173Simp#define MALTA_S54 0x08 /* switch S5-4 - set YAMON factory default mode */ 143178173Simp#define MALTA_S53 0x04 /* switch S5-3 */ 144178173Simp#define MALTA_BIGEND 0x02 /* switch S5-2 - big endian mode */ 145178173Simp 146178173Simp#define MALTA_JMPRS (MALTA_FPGA_BASE + 0x210) 147178173Simp#define MALTA_JMPRS_PCICLK 0x1c /* PCI clock frequency */ 148178173Simp#define MALTA_JMPRS_EELOCK 0x02 /* I2C EEPROM is write protected */ 149178173Simp 150178173Simp#define MALTA_LEDBAR (MALTA_FPGA_BASE + 0x408) 151178173Simp#define MALTA_ASCIIWORD (MALTA_FPGA_BASE + 0x410) 152178173Simp#define MALTA_ASCII_BASE (MALTA_FPGA_BASE + 0x418) 153178173Simp#define MALTA_ASCIIPOS0 0x00 154178173Simp#define MALTA_ASCIIPOS1 0x08 155178173Simp#define MALTA_ASCIIPOS2 0x10 156178173Simp#define MALTA_ASCIIPOS3 0x18 157178173Simp#define MALTA_ASCIIPOS4 0x20 158178173Simp#define MALTA_ASCIIPOS5 0x28 159178173Simp#define MALTA_ASCIIPOS6 0x30 160178173Simp#define MALTA_ASCIIPOS7 0x38 161178173Simp 162178173Simp#define MALTA_SOFTRES (MALTA_FPGA_BASE + 0x500) 163178173Simp#define MALTA_GORESET 0x42 /* write this to MALTA_SOFTRES for board reset */ 164178173Simp 165178173Simp/* 166178173Simp * BRKRES is the number of milliseconds before a "break" on tty will 167178173Simp * trigger a reset. A value of 0 will disable the reset. 168178173Simp */ 169178173Simp#define MALTA_BRKRES (MALTA_FPGA_BASE + 0x508) 170178173Simp#define MALTA_BRKRES_MASK 0xff 171178173Simp 172178173Simp#define MALTA_CBUSUART (MALTA_FPGA_BASE + 0x900) 173178173Simp/* 16C550C UART, 8 bit registers on 8 byte boundaries */ 174178173Simp/* RXTX 0x00 */ 175178173Simp/* INTEN 0x08 */ 176178173Simp/* IIFIFO 0x10 */ 177178173Simp/* LCTRL 0x18 */ 178178173Simp/* MCTRL 0x20 */ 179178173Simp/* LSTAT 0x28 */ 180178173Simp/* MSTAT 0x30 */ 181178173Simp/* SCRATCH 0x38 */ 182178173Simp#define MALTA_CBUSUART_INTR 2 183178173Simp 184178173Simp#define MALTA_GPIO_BASE (MALTA_FPGA_BASE + 0xa00) 185178173Simp#define MALTA_GPOUT 0x0 186178173Simp#define MALTA_GPINP 0x8 187178173Simp 188178173Simp#define MALTA_I2C_BASE (MALTA_FPGA_BASE + 0xb00) 189178173Simp#define MALTA_I2CINP 0x00 190178173Simp#define MALTA_I2COE 0x08 191178173Simp#define MALTA_I2COUT 0x10 192178173Simp#define MALTA_I2CSEL 0x18 193178173Simp 194202035Simp#define MALTA_BOOTROM_BASE 0x1fc00000ul /* Boot ROM: */ 195178173Simp#define MALTA_BOOTROM_SIZE 0x00400000 /* 4 MByte */ 196178173Simp 197202035Simp#define MALTA_REVISION 0x1fc00010ul 198178173Simp#define MALTA_REV_FPGRV 0xff0000 /* CBUS FPGA revision */ 199178173Simp#define MALTA_REV_CORID 0x00fc00 /* Core Board ID */ 200178173Simp#define MALTA_REV_CORRV 0x000300 /* Core Board Revision */ 201178173Simp#define MALTA_REV_PROID 0x0000f0 /* Product ID */ 202178173Simp#define MALTA_REV_PRORV 0x00000f /* Product Revision */ 203178173Simp 204178173Simp/* PCI definitions */ 205178173Simp#define MALTA_SOUTHBRIDGE_INTR 0 206178173Simp 207178173Simp#define MALTA_PCI0_IO_BASE MALTA_PCIMEM3_BASE 208178173Simp#define MALTA_PCI0_ADDR( addr ) (MALTA_PCI0_IO_BASE + (addr)) 209178173Simp 210178173Simp#define MALTA_RTCADR 0x70 // MALTA_PCI_IO_ADDR8(0x70) 211178173Simp#define MALTA_RTCDAT 0x71 // MALTA_PCI_IO_ADDR8(0x71) 212178173Simp 213178173Simp#define MALTA_SMSC_COM1_ADR 0x3f8 214178173Simp#define MALTA_SMSC_COM2_ADR 0x2f8 215178173Simp#define MALTA_UART0ADR MALTA_PCI0_ADDR(MALTA_SMSC_COM1_ADR) 216178173Simp#define MALTA_UART1ADR MALTA_SMSC_COM2_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_COM2_ADR) 217178173Simp 218178173Simp#define MALTA_SMSC_1284_ADR 0x378 219178173Simp#define MALTA_1284ADR MALTA_SMSC_1284_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_1284_ADR) 220178173Simp 221178173Simp#define MALTA_SMSC_FDD_ADR 0x3f0 222178173Simp#define MALTA_FDDADR MALTA_SMSC_FDD_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_FDD_ADR) 223178173Simp 224178173Simp#define MALTA_SMSC_KYBD_ADR 0x60 /* Fixed 0x60, 0x64 */ 225178173Simp#define MALTA_KYBDADR MALTA_SMSC_KYBD_ADR // MALTA_PCI0_ADDR(MALTA_SMSC_KYBD_ADR) 226178173Simp#define MALTA_SMSC_MOUSE_ADR MALTA_SMSC_KYBD_ADR 227178173Simp#define MALTA_MOUSEADR MALTA_KYBDADR 228178173Simp 229178173Simp 230178173Simp#define MALTA_DMA_PCI_PCIBASE 0x00000000UL 231178173Simp#define MALTA_DMA_PCI_PHYSBASE 0x00000000UL 232178173Simp#define MALTA_DMA_PCI_SIZE (256 * 1024 * 1024) 233178173Simp 234178173Simp#define MALTA_DMA_ISA_PCIBASE 0x00800000UL 235178173Simp#define MALTA_DMA_ISA_PHYSBASE 0x00000000UL 236178173Simp#define MALTA_DMA_ISA_SIZE (8 * 1024 * 1024) 237178173Simp 238178173Simp#ifndef _LOCORE 239178173Simpvoid led_bar(uint8_t); 240178173Simpvoid led_display_word(uint32_t); 241178173Simpvoid led_display_str(const char *); 242178173Simpvoid led_display_char(int, uint8_t); 243178173Simp#endif 244