1178172Simp/* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */ 2178172Simp 3178172Simp/* 4178172Simp * Copyright (c) 1992, 1993 5178172Simp * The Regents of the University of California. All rights reserved. 6178172Simp * 7178172Simp * This code is derived from software contributed to Berkeley by 8178172Simp * Ralph Campbell and Rick Macklem. 9178172Simp * 10178172Simp * Redistribution and use in source and binary forms, with or without 11178172Simp * modification, are permitted provided that the following conditions 12178172Simp * are met: 13178172Simp * 1. Redistributions of source code must retain the above copyright 14178172Simp * notice, this list of conditions and the following disclaimer. 15178172Simp * 2. Redistributions in binary form must reproduce the above copyright 16178172Simp * notice, this list of conditions and the following disclaimer in the 17178172Simp * documentation and/or other materials provided with the distribution. 18178172Simp * 3. Neither the name of the University nor the names of its contributors 19178172Simp * may be used to endorse or promote products derived from this software 20178172Simp * without specific prior written permission. 21178172Simp * 22178172Simp * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23178172Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24178172Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25178172Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26178172Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27178172Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28178172Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29178172Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30178172Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31178172Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32178172Simp * SUCH DAMAGE. 33178172Simp * 34178172Simp * @(#)machConst.h 8.1 (Berkeley) 6/10/93 35178172Simp * 36178172Simp * machConst.h -- 37178172Simp * 38178172Simp * Machine dependent constants. 39178172Simp * 40178172Simp * Copyright (C) 1989 Digital Equipment Corporation. 41178172Simp * Permission to use, copy, modify, and distribute this software and 42178172Simp * its documentation for any purpose and without fee is hereby granted, 43178172Simp * provided that the above copyright notice appears in all copies. 44178172Simp * Digital Equipment Corporation makes no representations about the 45178172Simp * suitability of this software for any purpose. It is provided "as is" 46178172Simp * without express or implied warranty. 47178172Simp * 48178172Simp * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 49178172Simp * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 50178172Simp * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 51178172Simp * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 52178172Simp * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 53178172Simp * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 54178172Simp * 55178172Simp * $FreeBSD: releng/10.3/sys/mips/include/cpuregs.h 256172 2013-10-09 00:27:12Z adrian $ 56178172Simp */ 57178172Simp 58178172Simp#ifndef _MIPS_CPUREGS_H_ 59178172Simp#define _MIPS_CPUREGS_H_ 60178172Simp 61178172Simp/* 62178172Simp * Address space. 63178172Simp * 32-bit mips CPUS partition their 32-bit address space into four segments: 64178172Simp * 65178172Simp * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped 66178172Simp * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped 67178172Simp * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped 68178172Simp * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped 69178172Simp * 70178172Simp * Caching of mapped addresses is controlled by bits in the TLB entry. 71178172Simp */ 72178172Simp 73211453Sjchandra#define MIPS_KSEG0_LARGEST_PHYS (0x20000000) 74211453Sjchandra#define MIPS_KSEG0_PHYS_MASK (0x1fffffff) 75211453Sjchandra#define MIPS_XKPHYS_LARGEST_PHYS (0x10000000000) /* 40 bit PA */ 76211453Sjchandra#define MIPS_XKPHYS_PHYS_MASK (0x0ffffffffff) 77209928Sjchandra 78210009Simp#ifndef LOCORE 79206829Sjmallett#define MIPS_KUSEG_START 0x00000000 80206829Sjmallett#define MIPS_KSEG0_START ((intptr_t)(int32_t)0x80000000) 81206829Sjmallett#define MIPS_KSEG0_END ((intptr_t)(int32_t)0x9fffffff) 82206829Sjmallett#define MIPS_KSEG1_START ((intptr_t)(int32_t)0xa0000000) 83206829Sjmallett#define MIPS_KSEG1_END ((intptr_t)(int32_t)0xbfffffff) 84206829Sjmallett#define MIPS_KSSEG_START ((intptr_t)(int32_t)0xc0000000) 85206829Sjmallett#define MIPS_KSSEG_END ((intptr_t)(int32_t)0xdfffffff) 86206829Sjmallett#define MIPS_KSEG3_START ((intptr_t)(int32_t)0xe0000000) 87206829Sjmallett#define MIPS_KSEG3_END ((intptr_t)(int32_t)0xffffffff) 88178172Simp#define MIPS_KSEG2_START MIPS_KSSEG_START 89178172Simp#define MIPS_KSEG2_END MIPS_KSSEG_END 90210009Simp#endif 91178172Simp 92209928Sjchandra#define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START) 93209928Sjchandra#define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START) 94211453Sjchandra#define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK) 95211453Sjchandra#define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK) 96209928Sjchandra 97209928Sjchandra#define MIPS_IS_KSEG0_ADDR(x) \ 98209928Sjchandra (((vm_offset_t)(x) >= MIPS_KSEG0_START) && \ 99209928Sjchandra ((vm_offset_t)(x) <= MIPS_KSEG0_END)) 100209928Sjchandra#define MIPS_IS_KSEG1_ADDR(x) \ 101209928Sjchandra (((vm_offset_t)(x) >= MIPS_KSEG1_START) && \ 102209928Sjchandra ((vm_offset_t)(x) <= MIPS_KSEG1_END)) 103209928Sjchandra#define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) || \ 104209928Sjchandra MIPS_IS_KSEG1_ADDR(x)) 105209928Sjchandra 106210986Sneel/* 107210986Sneel * Cache Coherency Attributes: 108210986Sneel * UC: Uncached. 109210986Sneel * UA: Uncached accelerated. 110210986Sneel * C: Cacheable, coherency unspecified. 111210986Sneel * CNC: Cacheable non-coherent. 112210986Sneel * CC: Cacheable coherent. 113210986Sneel * CCE: Cacheable coherent, exclusive read. 114210986Sneel * CCEW: Cacheable coherent, exclusive write. 115210986Sneel * CCUOW: Cacheable coherent, update on write. 116210986Sneel * 117210986Sneel * Note that some bits vary in meaning across implementations (and that the 118210986Sneel * listing here is no doubt incomplete) and that the optimal cached mode varies 119210986Sneel * between implementations. 0x02 is required to be UC and 0x03 is required to 120210986Sneel * be a least C. 121210986Sneel * 122210986Sneel * We define the following logical bits: 123210986Sneel * UNCACHED: 124210986Sneel * The optimal uncached mode for the target CPU type. This must 125210986Sneel * be suitable for use in accessing memory-mapped devices. 126210986Sneel * CACHED: The optional cached mode for the target CPU type. 127210986Sneel */ 128206829Sjmallett 129210986Sneel#define MIPS_CCA_UC 0x02 /* Uncached. */ 130210986Sneel#define MIPS_CCA_C 0x03 /* Cacheable, coherency unspecified. */ 131210986Sneel 132210986Sneel#if defined(CPU_R4000) || defined(CPU_R10000) 133210986Sneel#define MIPS_CCA_CNC 0x03 134210986Sneel#define MIPS_CCA_CCE 0x04 135210986Sneel#define MIPS_CCA_CCEW 0x05 136210986Sneel 137210986Sneel#ifdef CPU_R4000 138210986Sneel#define MIPS_CCA_CCUOW 0x06 139210986Sneel#endif 140210986Sneel 141210986Sneel#ifdef CPU_R10000 142210986Sneel#define MIPS_CCA_UA 0x07 143210986Sneel#endif 144210986Sneel 145210986Sneel#define MIPS_CCA_CACHED MIPS_CCA_CCEW 146210986Sneel#endif /* defined(CPU_R4000) || defined(CPU_R10000) */ 147210986Sneel 148210986Sneel#if defined(CPU_SB1) 149210986Sneel#define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */ 150210986Sneel#endif 151210986Sneel 152256172Sadrian#if defined(CPU_MIPS74KC) 153256172Sadrian#define MIPS_CCA_UNCACHED 0x02 154256172Sadrian#define MIPS_CCA_CACHED 0x00 155256172Sadrian#endif 156256172Sadrian 157210986Sneel#ifndef MIPS_CCA_UNCACHED 158210986Sneel#define MIPS_CCA_UNCACHED MIPS_CCA_UC 159210986Sneel#endif 160210986Sneel 161210986Sneel/* 162210986Sneel * If we don't know which cached mode to use and there is a cache coherent 163210986Sneel * mode, use it. If there is not a cache coherent mode, use the required 164210986Sneel * cacheable mode. 165210986Sneel */ 166210986Sneel#ifndef MIPS_CCA_CACHED 167210986Sneel#ifdef MIPS_CCA_CC 168210986Sneel#define MIPS_CCA_CACHED MIPS_CCA_CC 169210986Sneel#else 170210986Sneel#define MIPS_CCA_CACHED MIPS_CCA_C 171210986Sneel#endif 172210986Sneel#endif 173210986Sneel 174178172Simp#define MIPS_PHYS_TO_XKPHYS(cca,x) \ 175178172Simp ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x)) 176209928Sjchandra#define MIPS_PHYS_TO_XKPHYS_CACHED(x) \ 177210986Sneel ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_CACHED) << 59) | (x)) 178209928Sjchandra#define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \ 179210986Sneel ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_UNCACHED) << 59) | (x)) 180178172Simp 181211453Sjchandra#define MIPS_XKPHYS_TO_PHYS(x) ((uintptr_t)(x) & MIPS_XKPHYS_PHYS_MASK) 182209928Sjchandra 183211453Sjchandra#define MIPS_XKPHYS_START 0x8000000000000000 184211453Sjchandra#define MIPS_XKPHYS_END 0xbfffffffffffffff 185206829Sjmallett#define MIPS_XUSEG_START 0x0000000000000000 186206829Sjmallett#define MIPS_XUSEG_END 0x0000010000000000 187206829Sjmallett#define MIPS_XKSEG_START 0xc000000000000000 188206829Sjmallett#define MIPS_XKSEG_END 0xc00000ff80000000 189214903Sgonzo#define MIPS_XKSEG_COMPAT32_START 0xffffffff80000000 190214903Sgonzo#define MIPS_XKSEG_COMPAT32_END 0xffffffffffffffff 191214903Sgonzo#define MIPS_XKSEG_TO_COMPAT32(va) ((va) & 0xffffffff) 192206829Sjmallett 193211453Sjchandra#ifdef __mips_n64 194211453Sjchandra#define MIPS_DIRECT_MAPPABLE(pa) 1 195211453Sjchandra#define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_XKPHYS_CACHED(pa) 196211453Sjchandra#define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_XKPHYS_UNCACHED(pa) 197211453Sjchandra#define MIPS_DIRECT_TO_PHYS(va) MIPS_XKPHYS_TO_PHYS(va) 198211453Sjchandra#else 199211453Sjchandra#define MIPS_DIRECT_MAPPABLE(pa) ((pa) < MIPS_KSEG0_LARGEST_PHYS) 200211453Sjchandra#define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_KSEG0(pa) 201211453Sjchandra#define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_KSEG1(pa) 202211453Sjchandra#define MIPS_DIRECT_TO_PHYS(va) MIPS_KSEG0_TO_PHYS(va) 203211453Sjchandra#endif 204211453Sjchandra 205178172Simp/* CPU dependent mtc0 hazard hook */ 206219693Sjmallett#if defined(CPU_CNMIPS) || defined(CPU_RMI) 207219693Sjmallett#define COP0_SYNC 208227658Sjchandra#elif defined(CPU_NLM) 209227658Sjchandra#define COP0_SYNC .word 0xc0 /* ehb */ 210202031Simp#elif defined(CPU_SB1) 211202031Simp#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop 212256172Sadrian#elif defined(CPU_MIPS74KC) 213256172Sadrian#define COP0_SYNC .word 0xc0 /* ehb */ 214178172Simp#else 215202996Sneel/* 216202996Sneel * Pick a reasonable default based on the "typical" spacing described in the 217202996Sneel * "CP0 Hazards" chapter of MIPS Architecture Book Vol III. 218202996Sneel */ 219256172Sadrian#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; .word 0xc0; 220178172Simp#endif 221178172Simp#define COP0_HAZARD_FPUENABLE nop; nop; nop; nop; 222178172Simp 223178172Simp/* 224178172Simp * The bits in the cause register. 225178172Simp * 226178172Simp * Bits common to r3000 and r4000: 227178172Simp * 228178172Simp * MIPS_CR_BR_DELAY Exception happened in branch delay slot. 229178172Simp * MIPS_CR_COP_ERR Coprocessor error. 230178172Simp * MIPS_CR_IP Interrupt pending bits defined below. 231178172Simp * (same meaning as in CAUSE register). 232178172Simp * MIPS_CR_EXC_CODE The exception type (see exception codes below). 233178172Simp * 234178172Simp * Differences: 235178172Simp * r3k has 4 bits of execption type, r4k has 5 bits. 236178172Simp */ 237178172Simp#define MIPS_CR_BR_DELAY 0x80000000 238178172Simp#define MIPS_CR_COP_ERR 0x30000000 239232615Sjmallett#define MIPS_CR_EXC_CODE 0x0000007C /* five bits */ 240178172Simp#define MIPS_CR_IP 0x0000FF00 241178172Simp#define MIPS_CR_EXC_CODE_SHIFT 2 242229677Sgonzo#define MIPS_CR_COP_ERR_SHIFT 28 243178172Simp 244178172Simp/* 245178172Simp * The bits in the status register. All bits are active when set to 1. 246178172Simp * 247178172Simp * R3000 status register fields: 248178172Simp * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors. 249178172Simp * MIPS_SR_TS TLB shutdown. 250178172Simp * 251178172Simp * MIPS_SR_INT_IE Master (current) interrupt enable bit. 252178172Simp * 253178172Simp * Differences: 254178172Simp * r3k has cache control is via frobbing SR register bits, whereas the 255178172Simp * r4k cache control is via explicit instructions. 256178172Simp * r3k has a 3-entry stack of kernel/user bits, whereas the 257178172Simp * r4k has kernel/supervisor/user. 258178172Simp */ 259178172Simp#define MIPS_SR_COP_USABILITY 0xf0000000 260178172Simp#define MIPS_SR_COP_0_BIT 0x10000000 261178172Simp#define MIPS_SR_COP_1_BIT 0x20000000 262178172Simp#define MIPS_SR_COP_2_BIT 0x40000000 263178172Simp 264178172Simp /* r4k and r3k differences, see below */ 265178172Simp 266178172Simp#define MIPS_SR_MX 0x01000000 /* MIPS64 */ 267178172Simp#define MIPS_SR_PX 0x00800000 /* MIPS64 */ 268178172Simp#define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */ 269178172Simp#define MIPS_SR_TS 0x00200000 270178172Simp#define MIPS_SR_DE 0x00010000 271178172Simp 272178172Simp#define MIPS_SR_INT_IE 0x00000001 273178172Simp/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ 274210009Simp#define MIPS_SR_INT_MASK 0x0000ff00 275178172Simp 276178172Simp/* 277178172Simp * R4000 status register bit definitons, 278178172Simp * where different from r2000/r3000. 279178172Simp */ 280232615Sjmallett#define MIPS_SR_XX 0x80000000 281232615Sjmallett#define MIPS_SR_RP 0x08000000 282232615Sjmallett#define MIPS_SR_FR 0x04000000 283232615Sjmallett#define MIPS_SR_RE 0x02000000 284178172Simp 285232615Sjmallett#define MIPS_SR_DIAG_DL 0x01000000 /* QED 52xx */ 286232615Sjmallett#define MIPS_SR_DIAG_IL 0x00800000 /* QED 52xx */ 287232615Sjmallett#define MIPS_SR_SR 0x00100000 288232615Sjmallett#define MIPS_SR_NMI 0x00080000 /* MIPS32/64 */ 289232615Sjmallett#define MIPS_SR_DIAG_CH 0x00040000 290232615Sjmallett#define MIPS_SR_DIAG_CE 0x00020000 291232615Sjmallett#define MIPS_SR_DIAG_PE 0x00010000 292232615Sjmallett#define MIPS_SR_EIE 0x00010000 /* TX79/R5900 */ 293232615Sjmallett#define MIPS_SR_KX 0x00000080 294232615Sjmallett#define MIPS_SR_SX 0x00000040 295232615Sjmallett#define MIPS_SR_UX 0x00000020 296232615Sjmallett#define MIPS_SR_KSU_MASK 0x00000018 297232615Sjmallett#define MIPS_SR_KSU_USER 0x00000010 298232615Sjmallett#define MIPS_SR_KSU_SUPER 0x00000008 299232615Sjmallett#define MIPS_SR_KSU_KERNEL 0x00000000 300232615Sjmallett#define MIPS_SR_ERL 0x00000004 301232615Sjmallett#define MIPS_SR_EXL 0x00000002 302178172Simp 303178172Simp/* 304178172Simp * The interrupt masks. 305178172Simp * If a bit in the mask is 1 then the interrupt is enabled (or pending). 306178172Simp */ 307178172Simp#define MIPS_INT_MASK 0xff00 308178172Simp#define MIPS_INT_MASK_5 0x8000 309178172Simp#define MIPS_INT_MASK_4 0x4000 310178172Simp#define MIPS_INT_MASK_3 0x2000 311178172Simp#define MIPS_INT_MASK_2 0x1000 312178172Simp#define MIPS_INT_MASK_1 0x0800 313178172Simp#define MIPS_INT_MASK_0 0x0400 314178172Simp#define MIPS_HARD_INT_MASK 0xfc00 315178172Simp#define MIPS_SOFT_INT_MASK_1 0x0200 316178172Simp#define MIPS_SOFT_INT_MASK_0 0x0100 317178172Simp 318178172Simp/* 319178172Simp * The bits in the MIPS3 config register. 320178172Simp * 321178172Simp * bit 0..5: R/W, Bit 6..31: R/O 322178172Simp */ 323178172Simp 324178172Simp/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 325232615Sjmallett#define MIPS_CONFIG_K0_MASK 0x00000007 326178172Simp 327178172Simp/* 328178172Simp * R/W Update on Store Conditional 329178172Simp * 0: Store Conditional uses coherency algorithm specified by TLB 330178172Simp * 1: Store Conditional uses cacheable coherent update on write 331178172Simp */ 332232615Sjmallett#define MIPS_CONFIG_CU 0x00000008 333178172Simp 334232615Sjmallett#define MIPS_CONFIG_DB 0x00000010 /* Primary D-cache line size */ 335232615Sjmallett#define MIPS_CONFIG_IB 0x00000020 /* Primary I-cache line size */ 336232615Sjmallett#define MIPS_CONFIG_CACHE_L1_LSIZE(config, bit) \ 337178172Simp (((config) & (bit)) ? 32 : 16) 338178172Simp 339232615Sjmallett#define MIPS_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ 340232615Sjmallett#define MIPS_CONFIG_DC_SHIFT 6 341232615Sjmallett#define MIPS_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ 342232615Sjmallett#define MIPS_CONFIG_IC_SHIFT 9 343232615Sjmallett#define MIPS_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */ 344178172Simp 345178172Simp/* Cache size mode indication: available only on Vr41xx CPUs */ 346232615Sjmallett#define MIPS_CONFIG_CS 0x00001000 347232615Sjmallett#define MIPS_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */ 348232615Sjmallett#define MIPS_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 349178172Simp ((base) << (((config) & (mask)) >> (shift))) 350178172Simp 351178172Simp/* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */ 352232615Sjmallett#define MIPS_CONFIG_SE 0x00001000 353178172Simp 354178172Simp/* Block ordering: 0: sequential, 1: sub-block */ 355232615Sjmallett#define MIPS_CONFIG_EB 0x00002000 356178172Simp 357178172Simp/* ECC mode - 0: ECC mode, 1: parity mode */ 358232615Sjmallett#define MIPS_CONFIG_EM 0x00004000 359178172Simp 360178172Simp/* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ 361232615Sjmallett#define MIPS_CONFIG_BE 0x00008000 362178172Simp 363178172Simp/* Dirty Shared coherency state - 0: enabled, 1: disabled */ 364232615Sjmallett#define MIPS_CONFIG_SM 0x00010000 365178172Simp 366178172Simp/* Secondary Cache - 0: present, 1: not present */ 367232615Sjmallett#define MIPS_CONFIG_SC 0x00020000 368178172Simp 369178172Simp/* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */ 370232615Sjmallett#define MIPS_CONFIG_EW_MASK 0x000c0000 371232615Sjmallett#define MIPS_CONFIG_EW_SHIFT 18 372178172Simp 373178172Simp/* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ 374232615Sjmallett#define MIPS_CONFIG_SW 0x00100000 375178172Simp 376178172Simp/* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ 377232615Sjmallett#define MIPS_CONFIG_SS 0x00200000 378178172Simp 379178172Simp/* Secondary Cache line size */ 380232615Sjmallett#define MIPS_CONFIG_SB_MASK 0x00c00000 381232615Sjmallett#define MIPS_CONFIG_SB_SHIFT 22 382232615Sjmallett#define MIPS_CONFIG_CACHE_L2_LSIZE(config) \ 383232615Sjmallett (0x10 << (((config) & MIPS_CONFIG_SB_MASK) >> MIPS_CONFIG_SB_SHIFT)) 384178172Simp 385178172Simp/* Write back data rate */ 386232615Sjmallett#define MIPS_CONFIG_EP_MASK 0x0f000000 387232615Sjmallett#define MIPS_CONFIG_EP_SHIFT 24 388178172Simp 389178172Simp/* System clock ratio - this value is CPU dependent */ 390232615Sjmallett#define MIPS_CONFIG_EC_MASK 0x70000000 391232615Sjmallett#define MIPS_CONFIG_EC_SHIFT 28 392178172Simp 393178172Simp/* Master-Checker Mode - 1: enabled */ 394232615Sjmallett#define MIPS_CONFIG_CM 0x80000000 395178172Simp 396178172Simp/* 397178172Simp * The bits in the MIPS4 config register. 398178172Simp */ 399178172Simp 400178172Simp/* 401178172Simp * Location of exception vectors. 402178172Simp * 403178172Simp * Common vectors: reset and UTLB miss. 404178172Simp */ 405210009Simp#define MIPS_RESET_EXC_VEC ((intptr_t)(int32_t)0xBFC00000) 406210009Simp#define MIPS_UTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000000) 407178172Simp 408178172Simp/* 409178172Simp * MIPS-III exception vectors 410178172Simp */ 411232615Sjmallett#define MIPS_XTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000080) 412232615Sjmallett#define MIPS_CACHE_ERR_EXC_VEC ((intptr_t)(int32_t)0x80000100) 413232615Sjmallett#define MIPS_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000180) 414178172Simp 415178172Simp/* 416178172Simp * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector. 417178172Simp */ 418232615Sjmallett#define MIPS_INTR_EXC_VEC 0x80000200 419178172Simp 420178172Simp/* 421178172Simp * Coprocessor 0 registers: 422178172Simp * 423178172Simp * v--- width for mips I,III,32,64 424178172Simp * (3=32bit, 6=64bit, i=impl dep) 425178172Simp * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index. 426178172Simp * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random. 427178172Simp * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low. 428178172Simp * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended. 429178172Simp * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context. 430178172Simp * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register. 431178172Simp * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number. 432210028Simp * 7 MIPS_COP_0_INFO ..33 Info registers 433178172Simp * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address. 434178172Simp * 9 MIPS_COP_0_COUNT .333 Count register. 435178172Simp * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high. 436178172Simp * 11 MIPS_COP_0_COMPARE .333 Compare (against Count). 437178172Simp * 12 MIPS_COP_0_STATUS 3333 Status register. 438178172Simp * 13 MIPS_COP_0_CAUSE 3333 Exception cause register. 439178172Simp * 14 MIPS_COP_0_EXC_PC 3636 Exception PC. 440178172Simp * 15 MIPS_COP_0_PRID 3333 Processor revision identifier. 441178172Simp * 16 MIPS_COP_0_CONFIG 3333 Configuration register. 442178172Simp * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1. 443178172Simp * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2. 444178172Simp * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3. 445219693Sjmallett * 16/4 MIPS_COP_0_CONFIG4 ..33 Configuration register 4. 446178172Simp * 17 MIPS_COP_0_LLADDR .336 Load Linked Address. 447178172Simp * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register. 448178172Simp * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register. 449178172Simp * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register. 450178172Simp * 23 MIPS_COP_0_DEBUG .... Debug JTAG register. 451178172Simp * 24 MIPS_COP_0_DEPC .... DEPC JTAG register. 452178172Simp * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register. 453178172Simp * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register. 454178172Simp * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register. 455178172Simp * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr). 456178172Simp * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr). 457178172Simp * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data). 458178172Simp * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data). 459178172Simp * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr). 460178172Simp * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr). 461178172Simp * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data). 462178172Simp * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data). 463178172Simp * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register. 464178172Simp * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register. 465178172Simp */ 466178172Simp 467178172Simp/* Deal with inclusion from an assembly file. */ 468178172Simp#if defined(_LOCORE) || defined(LOCORE) 469178172Simp#define _(n) $n 470178172Simp#else 471178172Simp#define _(n) n 472178172Simp#endif 473178172Simp 474178172Simp 475178172Simp#define MIPS_COP_0_TLB_INDEX _(0) 476178172Simp#define MIPS_COP_0_TLB_RANDOM _(1) 477178172Simp /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ 478178172Simp 479178172Simp#define MIPS_COP_0_TLB_CONTEXT _(4) 480178172Simp /* $5 and $6 new with MIPS-III */ 481178172Simp#define MIPS_COP_0_BAD_VADDR _(8) 482178172Simp#define MIPS_COP_0_TLB_HI _(10) 483178172Simp#define MIPS_COP_0_STATUS _(12) 484178172Simp#define MIPS_COP_0_CAUSE _(13) 485178172Simp#define MIPS_COP_0_EXC_PC _(14) 486178172Simp#define MIPS_COP_0_PRID _(15) 487178172Simp 488178172Simp/* MIPS-III */ 489178172Simp#define MIPS_COP_0_TLB_LO0 _(2) 490178172Simp#define MIPS_COP_0_TLB_LO1 _(3) 491178172Simp 492178172Simp#define MIPS_COP_0_TLB_PG_MASK _(5) 493178172Simp#define MIPS_COP_0_TLB_WIRED _(6) 494178172Simp 495178172Simp#define MIPS_COP_0_COUNT _(9) 496178172Simp#define MIPS_COP_0_COMPARE _(11) 497178172Simp 498178172Simp#define MIPS_COP_0_CONFIG _(16) 499178172Simp#define MIPS_COP_0_LLADDR _(17) 500178172Simp#define MIPS_COP_0_WATCH_LO _(18) 501178172Simp#define MIPS_COP_0_WATCH_HI _(19) 502178172Simp#define MIPS_COP_0_TLB_XCONTEXT _(20) 503178172Simp#define MIPS_COP_0_ECC _(26) 504178172Simp#define MIPS_COP_0_CACHE_ERR _(27) 505178172Simp#define MIPS_COP_0_TAG_LO _(28) 506178172Simp#define MIPS_COP_0_TAG_HI _(29) 507178172Simp#define MIPS_COP_0_ERROR_PC _(30) 508178172Simp 509178172Simp/* MIPS32/64 */ 510210028Simp#define MIPS_COP_0_INFO _(7) 511178172Simp#define MIPS_COP_0_DEBUG _(23) 512178172Simp#define MIPS_COP_0_DEPC _(24) 513178172Simp#define MIPS_COP_0_PERFCNT _(25) 514178172Simp#define MIPS_COP_0_DATA_LO _(28) 515178172Simp#define MIPS_COP_0_DATA_HI _(29) 516178172Simp#define MIPS_COP_0_DESAVE _(31) 517178172Simp 518178172Simp/* MIPS32 Config register definitions */ 519178172Simp#define MIPS_MMU_NONE 0x00 /* No MMU present */ 520178172Simp#define MIPS_MMU_TLB 0x01 /* Standard TLB */ 521178172Simp#define MIPS_MMU_BAT 0x02 /* Standard BAT */ 522178172Simp#define MIPS_MMU_FIXED 0x03 /* Standard fixed mapping */ 523178172Simp 524178172Simp#define MIPS_CONFIG0_MT_MASK 0x00000380 /* bits 9..7 MMU Type */ 525178172Simp#define MIPS_CONFIG0_MT_SHIFT 7 526178172Simp#define MIPS_CONFIG0_BE 0x00008000 /* data is big-endian */ 527178172Simp#define MIPS_CONFIG0_VI 0x00000004 /* instruction cache is virtual */ 528178172Simp 529178172Simp#define MIPS_CONFIG1_TLBSZ_MASK 0x7E000000 /* bits 30..25 # tlb entries minus one */ 530178172Simp#define MIPS_CONFIG1_TLBSZ_SHIFT 25 531205064Sneel 532178172Simp#define MIPS_CONFIG1_IS_MASK 0x01C00000 /* bits 24..22 icache sets per way */ 533178172Simp#define MIPS_CONFIG1_IS_SHIFT 22 534178172Simp#define MIPS_CONFIG1_IL_MASK 0x00380000 /* bits 21..19 icache line size */ 535178172Simp#define MIPS_CONFIG1_IL_SHIFT 19 536178172Simp#define MIPS_CONFIG1_IA_MASK 0x00070000 /* bits 18..16 icache associativity */ 537178172Simp#define MIPS_CONFIG1_IA_SHIFT 16 538178172Simp#define MIPS_CONFIG1_DS_MASK 0x0000E000 /* bits 15..13 dcache sets per way */ 539178172Simp#define MIPS_CONFIG1_DS_SHIFT 13 540178172Simp#define MIPS_CONFIG1_DL_MASK 0x00001C00 /* bits 12..10 dcache line size */ 541178172Simp#define MIPS_CONFIG1_DL_SHIFT 10 542178172Simp#define MIPS_CONFIG1_DA_MASK 0x00000380 /* bits 9.. 7 dcache associativity */ 543178172Simp#define MIPS_CONFIG1_DA_SHIFT 7 544178172Simp#define MIPS_CONFIG1_LOWBITS 0x0000007F 545178172Simp#define MIPS_CONFIG1_C2 0x00000040 /* Coprocessor 2 implemented */ 546178172Simp#define MIPS_CONFIG1_MD 0x00000020 /* MDMX ASE implemented (MIPS64) */ 547178172Simp#define MIPS_CONFIG1_PC 0x00000010 /* Performance counters implemented */ 548178172Simp#define MIPS_CONFIG1_WR 0x00000008 /* Watch registers implemented */ 549178172Simp#define MIPS_CONFIG1_CA 0x00000004 /* MIPS16e ISA implemented */ 550178172Simp#define MIPS_CONFIG1_EP 0x00000002 /* EJTAG implemented */ 551178172Simp#define MIPS_CONFIG1_FP 0x00000001 /* FPU implemented */ 552178172Simp 553219693Sjmallett#define MIPS_CONFIG4_MMUSIZEEXT 0x000000FF /* bits 7.. 0 MMU Size Extension */ 554219693Sjmallett#define MIPS_CONFIG4_MMUEXTDEF 0x0000C000 /* bits 15.14 MMU Extension Definition */ 555219693Sjmallett#define MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT 0x00004000 /* This values denotes CONFIG4 bits */ 556219693Sjmallett 557178172Simp/* 558178172Simp * Values for the code field in a break instruction. 559178172Simp */ 560178172Simp#define MIPS_BREAK_INSTR 0x0000000d 561178172Simp#define MIPS_BREAK_VAL_MASK 0x03ff0000 562178172Simp#define MIPS_BREAK_VAL_SHIFT 16 563178172Simp#define MIPS_BREAK_KDB_VAL 512 564178172Simp#define MIPS_BREAK_SSTEP_VAL 513 565178172Simp#define MIPS_BREAK_BRKPT_VAL 514 566178172Simp#define MIPS_BREAK_SOVER_VAL 515 567210009Simp#define MIPS_BREAK_DDB_VAL 516 568178172Simp#define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ 569178172Simp (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) 570178172Simp#define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ 571178172Simp (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT)) 572178172Simp#define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \ 573178172Simp (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) 574178172Simp#define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ 575178172Simp (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) 576210009Simp#define MIPS_BREAK_DDB (MIPS_BREAK_INSTR | \ 577210009Simp (MIPS_BREAK_DDB_VAL << MIPS_BREAK_VAL_SHIFT)) 578178172Simp 579178172Simp/* 580178172Simp * Mininum and maximum cache sizes. 581178172Simp */ 582178172Simp#define MIPS_MIN_CACHE_SIZE (16 * 1024) 583178172Simp#define MIPS_MAX_CACHE_SIZE (256 * 1024) 584232615Sjmallett#define MIPS_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */ 585178172Simp 586178172Simp/* 587178172Simp * The floating point version and status registers. 588178172Simp */ 589178172Simp#define MIPS_FPU_ID $0 590178172Simp#define MIPS_FPU_CSR $31 591178172Simp 592178172Simp/* 593178172Simp * The floating point coprocessor status register bits. 594178172Simp */ 595178172Simp#define MIPS_FPU_ROUNDING_BITS 0x00000003 596178172Simp#define MIPS_FPU_ROUND_RN 0x00000000 597178172Simp#define MIPS_FPU_ROUND_RZ 0x00000001 598178172Simp#define MIPS_FPU_ROUND_RP 0x00000002 599178172Simp#define MIPS_FPU_ROUND_RM 0x00000003 600178172Simp#define MIPS_FPU_STICKY_BITS 0x0000007c 601178172Simp#define MIPS_FPU_STICKY_INEXACT 0x00000004 602178172Simp#define MIPS_FPU_STICKY_UNDERFLOW 0x00000008 603178172Simp#define MIPS_FPU_STICKY_OVERFLOW 0x00000010 604178172Simp#define MIPS_FPU_STICKY_DIV0 0x00000020 605178172Simp#define MIPS_FPU_STICKY_INVALID 0x00000040 606178172Simp#define MIPS_FPU_ENABLE_BITS 0x00000f80 607178172Simp#define MIPS_FPU_ENABLE_INEXACT 0x00000080 608178172Simp#define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100 609178172Simp#define MIPS_FPU_ENABLE_OVERFLOW 0x00000200 610178172Simp#define MIPS_FPU_ENABLE_DIV0 0x00000400 611178172Simp#define MIPS_FPU_ENABLE_INVALID 0x00000800 612178172Simp#define MIPS_FPU_EXCEPTION_BITS 0x0003f000 613178172Simp#define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 614178172Simp#define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 615178172Simp#define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 616178172Simp#define MIPS_FPU_EXCEPTION_DIV0 0x00008000 617178172Simp#define MIPS_FPU_EXCEPTION_INVALID 0x00010000 618178172Simp#define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 619178172Simp#define MIPS_FPU_COND_BIT 0x00800000 620178172Simp#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ 621232615Sjmallett#define MIPS_FPC_MBZ_BITS 0xfe7c0000 622178172Simp 623178172Simp 624178172Simp/* 625178172Simp * Constants to determine if have a floating point instruction. 626178172Simp */ 627178172Simp#define MIPS_OPCODE_SHIFT 26 628178172Simp#define MIPS_OPCODE_C1 0x11 629178172Simp 630178172Simp#endif /* _MIPS_CPUREGS_H_ */ 631