BERI_DE4.hints revision 239691 
1# $FreeBSD: head/sys/mips/conf/BERI_DE4.hints 239691 2012-08-25 22:35:29Z rwatson $
2
3#
4# Altera JTAG UARTs configured for console, debugging, and data putput on the
5# Terasic DE-4.
6#
7hint.altera_jtag_uart.0.at="nexus0"
8hint.altera_jtag_uart.0.maddr=0x7f000000
9hint.altera_jtag_uart.0.msize=0x40
10hint.altera_jtag_uart.0.irq=0
11
12hint.altera_jtag_uart.1.at="nexus0"
13hint.altera_jtag_uart.1.maddr=0x7f001000
14hint.altera_jtag_uart.1.msize=0x40
15
16hint.altera_jtag_uart.2.at="nexus0"
17hint.altera_jtag_uart.2.maddr=0x7f002000
18hint.altera_jtag_uart.2.msize=0x40
19
20#
21# On-board DE4 and tPad SD Card IP core
22#
23hint.altera_sdcardc.0.at="nexus0"
24hint.altera_sdcardc.0.maddr=0x7f008000
25hint.altera_sdcardc.0.msize=0x400
26
27#
28# Terasic Multi-touch LCD (MTL), an optional feature in DE-4 configurations.
29#
30hint.terasic_mtl.0.at="nexus0"
31hint.terasic_mtl.0.reg_maddr=0x70400000
32hint.terasic_mtl.0.reg_msize=0x1000
33hint.terasic_mtl.0.pixel_maddr=0x70000000
34hint.terasic_mtl.0.pixel_msize=0x177000
35hint.terasic_mtl.0.text_maddr=0x70177000
36hint.terasic_mtl.0.text_msize=0x2000
37
38#
39# BERI Hardware Version ROM
40#
41hint.altera_avgen.0.at="nexus0"
42hint.altera_avgen.0.maddr=0x7F00A000
43hint.altera_avgen.0.msize=20
44hint.altera_avgen.0.width=4
45hint.altera_avgen.0.fileio="rw"
46hint.altera_avgen.0.devname="berirom"
47
48#
49# Expose the DE4 flash via an Avalon "generic" device.
50# This is incompatible with the isf(4) driver.
51#
52#hint.altera_avgen.0.at="nexus0"
53#hint.altera_avgen.0.maddr=0x74000000
54#hint.altera_avgen.0.msize=0x4000000
55#hint.altera_avgen.0.width=2
56#hint.altera_avgen.0.fileio="rw"
57#hint.altera_avgen.0.mmapio="rwx"
58#hint.altera_avgen.0.devname="de4flash"
59
60#
61# General Intel StrataFlash driver
62#
63hint.isf.0.at="nexus0"
64hint.isf.0.maddr=0x74000000
65hint.isf.0.msize=0x2000000
66hint.isf.1.at="nexus0"
67hint.isf.1.maddr=0x76000000
68hint.isf.1.msize=0x2000000  
69
70# Reserved configuration blocks.  Don't touch.
71hint.map.0.at="isf0"
72hint.map.0.start=0x00000000
73hint.map.0.end=0x00020000
74hint.map.0.name="config"
75hint.map.0.readonly=1
76
77# Hardwired location of bitfile
78hint.map.1.at="isf0"
79hint.map.1.start=0x00020000
80hint.map.1.end=0x01820000
81hint.map.1.name="fpga"
82
83# Kernel on first chip
84hint.map.2.at="isf0"
85hint.map.2.start=0x01820000
86hint.map.2.end=0x02000000
87hint.map.2.name="reserved"
88
89# The second chip
90hint.map.3.at="isf1"
91hint.map.3.start=0x00000000
92hint.map.3.end=0x02000000
93hint.map.3.name="kernel"
94