if_arge.c revision 220354
1188808Sgonzo/*- 2188808Sgonzo * Copyright (c) 2009, Oleksandr Tymoshenko 3188808Sgonzo * All rights reserved. 4188808Sgonzo * 5188808Sgonzo * Redistribution and use in source and binary forms, with or without 6188808Sgonzo * modification, are permitted provided that the following conditions 7188808Sgonzo * are met: 8188808Sgonzo * 1. Redistributions of source code must retain the above copyright 9188808Sgonzo * notice unmodified, this list of conditions, and the following 10188808Sgonzo * disclaimer. 11188808Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 12188808Sgonzo * notice, this list of conditions and the following disclaimer in the 13188808Sgonzo * documentation and/or other materials provided with the distribution. 14188808Sgonzo * 15188808Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16188808Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17188808Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18188808Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19188808Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20188808Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21188808Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22188808Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23188808Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24188808Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25188808Sgonzo * SUCH DAMAGE. 26188808Sgonzo */ 27188808Sgonzo 28188808Sgonzo#include <sys/cdefs.h> 29188808Sgonzo__FBSDID("$FreeBSD: head/sys/mips/atheros/if_arge.c 220354 2011-04-05 05:15:48Z adrian $"); 30188808Sgonzo 31188808Sgonzo/* 32188808Sgonzo * AR71XX gigabit ethernet driver 33188808Sgonzo */ 34192783Sgonzo#ifdef HAVE_KERNEL_OPTION_HEADERS 35192783Sgonzo#include "opt_device_polling.h" 36192783Sgonzo#endif 37192783Sgonzo 38188808Sgonzo#include <sys/param.h> 39188808Sgonzo#include <sys/endian.h> 40188808Sgonzo#include <sys/systm.h> 41188808Sgonzo#include <sys/sockio.h> 42188808Sgonzo#include <sys/mbuf.h> 43188808Sgonzo#include <sys/malloc.h> 44188808Sgonzo#include <sys/kernel.h> 45188808Sgonzo#include <sys/module.h> 46188808Sgonzo#include <sys/socket.h> 47188808Sgonzo#include <sys/taskqueue.h> 48209802Sadrian#include <sys/sysctl.h> 49188808Sgonzo 50188808Sgonzo#include <net/if.h> 51188808Sgonzo#include <net/if_arp.h> 52188808Sgonzo#include <net/ethernet.h> 53188808Sgonzo#include <net/if_dl.h> 54188808Sgonzo#include <net/if_media.h> 55188808Sgonzo#include <net/if_types.h> 56188808Sgonzo 57188808Sgonzo#include <net/bpf.h> 58188808Sgonzo 59188808Sgonzo#include <machine/bus.h> 60188808Sgonzo#include <machine/cache.h> 61188808Sgonzo#include <machine/resource.h> 62188808Sgonzo#include <vm/vm_param.h> 63188808Sgonzo#include <vm/vm.h> 64188808Sgonzo#include <vm/pmap.h> 65188808Sgonzo#include <machine/pmap.h> 66188808Sgonzo#include <sys/bus.h> 67188808Sgonzo#include <sys/rman.h> 68188808Sgonzo 69188808Sgonzo#include <dev/mii/mii.h> 70188808Sgonzo#include <dev/mii/miivar.h> 71188808Sgonzo 72188808Sgonzo#include <dev/pci/pcireg.h> 73188808Sgonzo#include <dev/pci/pcivar.h> 74188808Sgonzo 75188808SgonzoMODULE_DEPEND(arge, ether, 1, 1, 1); 76188808SgonzoMODULE_DEPEND(arge, miibus, 1, 1, 1); 77188808Sgonzo 78188808Sgonzo#include "miibus_if.h" 79188808Sgonzo 80188808Sgonzo#include <mips/atheros/ar71xxreg.h> 81188808Sgonzo#include <mips/atheros/if_argevar.h> 82219589Sadrian#include <mips/atheros/ar71xx_setup.h> 83211477Sadrian#include <mips/atheros/ar71xx_cpudef.h> 84188808Sgonzo 85220354Sadriantypedef enum { 86220354Sadrian ARGE_DBG_MII = 0x00000001, 87220354Sadrian ARGE_DBG_INTR = 0x00000002 88220354Sadrian} arge_debug_flags; 89220354Sadrian 90188808Sgonzo#undef ARGE_DEBUG 91188808Sgonzo#ifdef ARGE_DEBUG 92220354Sadrian#define ARGEDEBUG(_sc, _m, ...) \ 93220354Sadrian do { \ 94220354Sadrian if ((_m) & (_sc)->arge_debug) \ 95220354Sadrian device_printf((_sc)->arge_dev, __VA_ARGS__); \ 96220354Sadrian } while (0) 97188808Sgonzo#else 98220354Sadrian#define ARGEDEBUG(_sc, _m, ...) 99188808Sgonzo#endif 100188808Sgonzo 101188808Sgonzostatic int arge_attach(device_t); 102188808Sgonzostatic int arge_detach(device_t); 103188808Sgonzostatic void arge_flush_ddr(struct arge_softc *); 104188808Sgonzostatic int arge_ifmedia_upd(struct ifnet *); 105188808Sgonzostatic void arge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 106188808Sgonzostatic int arge_ioctl(struct ifnet *, u_long, caddr_t); 107188808Sgonzostatic void arge_init(void *); 108188808Sgonzostatic void arge_init_locked(struct arge_softc *); 109188808Sgonzostatic void arge_link_task(void *, int); 110199234Sgonzostatic void arge_set_pll(struct arge_softc *, int, int); 111188808Sgonzostatic int arge_miibus_readreg(device_t, int, int); 112188808Sgonzostatic void arge_miibus_statchg(device_t); 113188808Sgonzostatic int arge_miibus_writereg(device_t, int, int, int); 114188808Sgonzostatic int arge_probe(device_t); 115188808Sgonzostatic void arge_reset_dma(struct arge_softc *); 116188808Sgonzostatic int arge_resume(device_t); 117188808Sgonzostatic int arge_rx_ring_init(struct arge_softc *); 118188808Sgonzostatic int arge_tx_ring_init(struct arge_softc *); 119192821Sgonzo#ifdef DEVICE_POLLING 120198667Sgonzostatic int arge_poll(struct ifnet *, enum poll_cmd, int); 121192821Sgonzo#endif 122194059Sgonzostatic int arge_shutdown(device_t); 123188808Sgonzostatic void arge_start(struct ifnet *); 124188808Sgonzostatic void arge_start_locked(struct ifnet *); 125188808Sgonzostatic void arge_stop(struct arge_softc *); 126188808Sgonzostatic int arge_suspend(device_t); 127188808Sgonzo 128198667Sgonzostatic int arge_rx_locked(struct arge_softc *); 129188808Sgonzostatic void arge_tx_locked(struct arge_softc *); 130188808Sgonzostatic void arge_intr(void *); 131188808Sgonzostatic int arge_intr_filter(void *); 132188808Sgonzostatic void arge_tick(void *); 133188808Sgonzo 134199234Sgonzo/* 135199234Sgonzo * ifmedia callbacks for multiPHY MAC 136199234Sgonzo */ 137199234Sgonzovoid arge_multiphy_mediastatus(struct ifnet *, struct ifmediareq *); 138199234Sgonzoint arge_multiphy_mediachange(struct ifnet *); 139199234Sgonzo 140188808Sgonzostatic void arge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 141188808Sgonzostatic int arge_dma_alloc(struct arge_softc *); 142188808Sgonzostatic void arge_dma_free(struct arge_softc *); 143188808Sgonzostatic int arge_newbuf(struct arge_softc *, int); 144188808Sgonzostatic __inline void arge_fixup_rx(struct mbuf *); 145188808Sgonzo 146188808Sgonzostatic device_method_t arge_methods[] = { 147188808Sgonzo /* Device interface */ 148188808Sgonzo DEVMETHOD(device_probe, arge_probe), 149188808Sgonzo DEVMETHOD(device_attach, arge_attach), 150188808Sgonzo DEVMETHOD(device_detach, arge_detach), 151188808Sgonzo DEVMETHOD(device_suspend, arge_suspend), 152188808Sgonzo DEVMETHOD(device_resume, arge_resume), 153188808Sgonzo DEVMETHOD(device_shutdown, arge_shutdown), 154188808Sgonzo 155188808Sgonzo /* bus interface */ 156188808Sgonzo DEVMETHOD(bus_print_child, bus_generic_print_child), 157188808Sgonzo DEVMETHOD(bus_driver_added, bus_generic_driver_added), 158188808Sgonzo 159188808Sgonzo /* MII interface */ 160188808Sgonzo DEVMETHOD(miibus_readreg, arge_miibus_readreg), 161188808Sgonzo DEVMETHOD(miibus_writereg, arge_miibus_writereg), 162188808Sgonzo DEVMETHOD(miibus_statchg, arge_miibus_statchg), 163188808Sgonzo 164188808Sgonzo { 0, 0 } 165188808Sgonzo}; 166188808Sgonzo 167188808Sgonzostatic driver_t arge_driver = { 168188808Sgonzo "arge", 169188808Sgonzo arge_methods, 170188808Sgonzo sizeof(struct arge_softc) 171188808Sgonzo}; 172188808Sgonzo 173188808Sgonzostatic devclass_t arge_devclass; 174188808Sgonzo 175188808SgonzoDRIVER_MODULE(arge, nexus, arge_driver, arge_devclass, 0, 0); 176188808SgonzoDRIVER_MODULE(miibus, arge, miibus_driver, miibus_devclass, 0, 0); 177188808Sgonzo 178188808Sgonzo/* 179192179Sgonzo * RedBoot passes MAC address to entry point as environment 180192179Sgonzo * variable. platfrom_start parses it and stores in this variable 181192179Sgonzo */ 182192179Sgonzoextern uint32_t ar711_base_mac[ETHER_ADDR_LEN]; 183192179Sgonzo 184199038Sgonzostatic struct mtx miibus_mtx; 185199038Sgonzo 186206400SgonzoMTX_SYSINIT(miibus_mtx, &miibus_mtx, "arge mii lock", MTX_DEF); 187199038Sgonzo 188199038Sgonzo 189192179Sgonzo/* 190188808Sgonzo * Flushes all 191188808Sgonzo */ 192188808Sgonzostatic void 193188808Sgonzoarge_flush_ddr(struct arge_softc *sc) 194188808Sgonzo{ 195211497Sadrian if (sc->arge_mac_unit == 0) 196211477Sadrian ar71xx_device_flush_ddr_ge0(); 197211497Sadrian else 198211477Sadrian ar71xx_device_flush_ddr_ge1(); 199188808Sgonzo} 200188808Sgonzo 201188808Sgonzostatic int 202188808Sgonzoarge_probe(device_t dev) 203188808Sgonzo{ 204188808Sgonzo 205188808Sgonzo device_set_desc(dev, "Atheros AR71xx built-in ethernet interface"); 206188808Sgonzo return (0); 207188808Sgonzo} 208188808Sgonzo 209209802Sadrianstatic void 210209802Sadrianarge_attach_sysctl(device_t dev) 211209802Sadrian{ 212209802Sadrian struct arge_softc *sc = device_get_softc(dev); 213209802Sadrian struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 214209802Sadrian struct sysctl_oid *tree = device_get_sysctl_tree(dev); 215209802Sadrian 216209802Sadrian SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 217209802Sadrian "debug", CTLFLAG_RW, &sc->arge_debug, 0, 218209802Sadrian "arge interface debugging flags"); 219209809Sadrian 220209809Sadrian SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 221209809Sadrian "tx_pkts_aligned", CTLFLAG_RW, &sc->stats.tx_pkts_aligned, 0, 222209809Sadrian "number of TX aligned packets"); 223209809Sadrian 224209809Sadrian SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 225209809Sadrian "tx_pkts_unaligned", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned, 0, 226209809Sadrian "number of TX unaligned packets"); 227220354Sadrian 228220354Sadrian SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_prod", CTLFLAG_RW, &sc->arge_cdata.arge_tx_prod, 0, ""); 229220354Sadrian SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cons", CTLFLAG_RW, &sc->arge_cdata.arge_tx_cons, 0, ""); 230220354Sadrian SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cnt", CTLFLAG_RW, &sc->arge_cdata.arge_tx_cnt, 0, ""); 231209802Sadrian} 232209802Sadrian 233188808Sgonzostatic int 234188808Sgonzoarge_attach(device_t dev) 235188808Sgonzo{ 236188808Sgonzo uint8_t eaddr[ETHER_ADDR_LEN]; 237188808Sgonzo struct ifnet *ifp; 238188808Sgonzo struct arge_softc *sc; 239199234Sgonzo int error = 0, rid, phymask; 240192179Sgonzo uint32_t reg, rnd; 241199234Sgonzo int is_base_mac_empty, i, phys_total; 242199234Sgonzo uint32_t hint; 243220260Sadrian long eeprom_mac_addr = 0; 244188808Sgonzo 245188808Sgonzo sc = device_get_softc(dev); 246188808Sgonzo sc->arge_dev = dev; 247188808Sgonzo sc->arge_mac_unit = device_get_unit(dev); 248188808Sgonzo 249220260Sadrian /* 250220260Sadrian * Some units (eg the TP-Link WR-1043ND) do not have a convenient 251220260Sadrian * EEPROM location to read the ethernet MAC address from. 252220260Sadrian * OpenWRT simply snaffles it from a fixed location. 253220260Sadrian * 254220260Sadrian * Since multiple units seem to use this feature, include 255220260Sadrian * a method of setting the MAC address based on an flash location 256220260Sadrian * in CPU address space. 257220260Sadrian */ 258220260Sadrian if (sc->arge_mac_unit == 0 && 259220260Sadrian resource_long_value(device_get_name(dev), device_get_unit(dev), 260220260Sadrian "eeprommac", &eeprom_mac_addr) == 0) { 261220260Sadrian int i; 262220260Sadrian const char *mac = (const char *) MIPS_PHYS_TO_KSEG1(eeprom_mac_addr); 263220260Sadrian device_printf(dev, "Overriding MAC from EEPROM\n"); 264220260Sadrian for (i = 0; i < 6; i++) { 265220260Sadrian ar711_base_mac[i] = mac[i]; 266220260Sadrian } 267220260Sadrian } 268220260Sadrian 269188808Sgonzo KASSERT(((sc->arge_mac_unit == 0) || (sc->arge_mac_unit == 1)), 270188808Sgonzo ("if_arge: Only MAC0 and MAC1 supported")); 271188808Sgonzo 272188808Sgonzo /* 273188808Sgonzo * Get which PHY of 5 available we should use for this unit 274188808Sgonzo */ 275188808Sgonzo if (resource_int_value(device_get_name(dev), device_get_unit(dev), 276199234Sgonzo "phymask", &phymask) != 0) { 277188808Sgonzo /* 278188808Sgonzo * Use port 4 (WAN) for GE0. For any other port use 279188808Sgonzo * its PHY the same as its unit number 280188808Sgonzo */ 281188808Sgonzo if (sc->arge_mac_unit == 0) 282199234Sgonzo phymask = (1 << 4); 283188808Sgonzo else 284199234Sgonzo /* Use all phys up to 4 */ 285199234Sgonzo phymask = (1 << 4) - 1; 286188808Sgonzo 287199234Sgonzo device_printf(dev, "No PHY specified, using mask %d\n", phymask); 288188808Sgonzo } 289188808Sgonzo 290199234Sgonzo /* 291199234Sgonzo * Get default media & duplex mode, by default its Base100T 292199234Sgonzo * and full duplex 293199234Sgonzo */ 294199234Sgonzo if (resource_int_value(device_get_name(dev), device_get_unit(dev), 295199234Sgonzo "media", &hint) != 0) 296199234Sgonzo hint = 0; 297188808Sgonzo 298199234Sgonzo if (hint == 1000) 299199234Sgonzo sc->arge_media_type = IFM_1000_T; 300199234Sgonzo else 301199234Sgonzo sc->arge_media_type = IFM_100_TX; 302199234Sgonzo 303199234Sgonzo if (resource_int_value(device_get_name(dev), device_get_unit(dev), 304199234Sgonzo "fduplex", &hint) != 0) 305199234Sgonzo hint = 1; 306199234Sgonzo 307199234Sgonzo if (hint) 308199234Sgonzo sc->arge_duplex_mode = IFM_FDX; 309199234Sgonzo else 310199234Sgonzo sc->arge_duplex_mode = 0; 311199234Sgonzo 312199234Sgonzo sc->arge_phymask = phymask; 313199234Sgonzo 314188808Sgonzo mtx_init(&sc->arge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 315188808Sgonzo MTX_DEF); 316188808Sgonzo callout_init_mtx(&sc->arge_stat_callout, &sc->arge_mtx, 0); 317188808Sgonzo TASK_INIT(&sc->arge_link_task, 0, arge_link_task, sc); 318188808Sgonzo 319188808Sgonzo /* Map control/status registers. */ 320188808Sgonzo sc->arge_rid = 0; 321188808Sgonzo sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 322188808Sgonzo &sc->arge_rid, RF_ACTIVE); 323188808Sgonzo 324188808Sgonzo if (sc->arge_res == NULL) { 325188808Sgonzo device_printf(dev, "couldn't map memory\n"); 326188808Sgonzo error = ENXIO; 327188808Sgonzo goto fail; 328188808Sgonzo } 329188808Sgonzo 330188808Sgonzo /* Allocate interrupts */ 331188808Sgonzo rid = 0; 332188808Sgonzo sc->arge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 333188808Sgonzo RF_SHAREABLE | RF_ACTIVE); 334188808Sgonzo 335188808Sgonzo if (sc->arge_irq == NULL) { 336188808Sgonzo device_printf(dev, "couldn't map interrupt\n"); 337188808Sgonzo error = ENXIO; 338188808Sgonzo goto fail; 339188808Sgonzo } 340188808Sgonzo 341188808Sgonzo /* Allocate ifnet structure. */ 342188808Sgonzo ifp = sc->arge_ifp = if_alloc(IFT_ETHER); 343188808Sgonzo 344188808Sgonzo if (ifp == NULL) { 345188808Sgonzo device_printf(dev, "couldn't allocate ifnet structure\n"); 346188808Sgonzo error = ENOSPC; 347188808Sgonzo goto fail; 348188808Sgonzo } 349188808Sgonzo 350188808Sgonzo ifp->if_softc = sc; 351188808Sgonzo if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 352188808Sgonzo ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 353188808Sgonzo ifp->if_ioctl = arge_ioctl; 354188808Sgonzo ifp->if_start = arge_start; 355188808Sgonzo ifp->if_init = arge_init; 356198932Sgonzo sc->arge_if_flags = ifp->if_flags; 357188808Sgonzo 358188808Sgonzo /* XXX: add real size */ 359207554Ssobomax IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 360207554Ssobomax ifp->if_snd.ifq_maxlen = ifqmaxlen; 361188808Sgonzo IFQ_SET_READY(&ifp->if_snd); 362188808Sgonzo 363188808Sgonzo ifp->if_capenable = ifp->if_capabilities; 364192783Sgonzo#ifdef DEVICE_POLLING 365192783Sgonzo ifp->if_capabilities |= IFCAP_POLLING; 366192783Sgonzo#endif 367188808Sgonzo 368192179Sgonzo is_base_mac_empty = 1; 369192179Sgonzo for (i = 0; i < ETHER_ADDR_LEN; i++) { 370192179Sgonzo eaddr[i] = ar711_base_mac[i] & 0xff; 371192179Sgonzo if (eaddr[i] != 0) 372192179Sgonzo is_base_mac_empty = 0; 373192179Sgonzo } 374188808Sgonzo 375192179Sgonzo if (is_base_mac_empty) { 376192179Sgonzo /* 377192179Sgonzo * No MAC address configured. Generate the random one. 378192179Sgonzo */ 379198933Sgonzo if (bootverbose) 380192179Sgonzo device_printf(dev, 381192179Sgonzo "Generating random ethernet address.\n"); 382192179Sgonzo 383192179Sgonzo rnd = arc4random(); 384192179Sgonzo eaddr[0] = 'b'; 385192179Sgonzo eaddr[1] = 's'; 386192179Sgonzo eaddr[2] = 'd'; 387192179Sgonzo eaddr[3] = (rnd >> 24) & 0xff; 388192179Sgonzo eaddr[4] = (rnd >> 16) & 0xff; 389192179Sgonzo eaddr[5] = (rnd >> 8) & 0xff; 390192179Sgonzo } 391192179Sgonzo 392198970Sgonzo if (sc->arge_mac_unit != 0) 393198970Sgonzo eaddr[5] += sc->arge_mac_unit; 394198970Sgonzo 395188808Sgonzo if (arge_dma_alloc(sc) != 0) { 396188808Sgonzo error = ENXIO; 397188808Sgonzo goto fail; 398188808Sgonzo } 399188808Sgonzo 400192569Sdwhite /* Initialize the MAC block */ 401192569Sdwhite 402192569Sdwhite /* Step 1. Soft-reset MAC */ 403192569Sdwhite ARGE_SET_BITS(sc, AR71XX_MAC_CFG1, MAC_CFG1_SOFT_RESET); 404192569Sdwhite DELAY(20); 405192569Sdwhite 406192569Sdwhite /* Step 2. Punt the MAC core from the central reset register */ 407211477Sadrian ar71xx_device_stop(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC : RST_RESET_GE1_MAC); 408192569Sdwhite DELAY(100); 409211477Sadrian ar71xx_device_start(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC : RST_RESET_GE1_MAC); 410192569Sdwhite 411192569Sdwhite /* Step 3. Reconfigure MAC block */ 412188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_CFG1, 413188808Sgonzo MAC_CFG1_SYNC_RX | MAC_CFG1_RX_ENABLE | 414188808Sgonzo MAC_CFG1_SYNC_TX | MAC_CFG1_TX_ENABLE); 415188808Sgonzo 416188808Sgonzo reg = ARGE_READ(sc, AR71XX_MAC_CFG2); 417188808Sgonzo reg |= MAC_CFG2_ENABLE_PADCRC | MAC_CFG2_LENGTH_FIELD ; 418188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_CFG2, reg); 419188808Sgonzo 420188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_MAX_FRAME_LEN, 1536); 421188808Sgonzo 422188808Sgonzo /* Reset MII bus */ 423188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET); 424188808Sgonzo DELAY(100); 425188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_CLOCK_DIV_28); 426188808Sgonzo DELAY(100); 427188808Sgonzo 428188808Sgonzo /* 429188808Sgonzo * Set all Ethernet address registers to the same initial values 430188808Sgonzo * set all four addresses to 66-88-aa-cc-dd-ee 431188808Sgonzo */ 432192783Sgonzo ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR1, 433192783Sgonzo (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]); 434192783Sgonzo ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR2, (eaddr[0] << 8) | eaddr[1]); 435188808Sgonzo 436188808Sgonzo ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0, 437188808Sgonzo FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT); 438188808Sgonzo 439219589Sadrian switch (ar71xx_soc) { 440219589Sadrian case AR71XX_SOC_AR7240: 441219589Sadrian case AR71XX_SOC_AR7241: 442219589Sadrian case AR71XX_SOC_AR7242: 443219589Sadrian ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0010ffff); 444219589Sadrian ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x015500aa); 445219589Sadrian break; 446219589Sadrian default: 447219589Sadrian ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0fff0000); 448219589Sadrian ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x00001fff); 449219589Sadrian } 450219589Sadrian 451192783Sgonzo ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMATCH, 452192783Sgonzo FIFO_RX_FILTMATCH_DEFAULT); 453188808Sgonzo 454192783Sgonzo ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK, 455192783Sgonzo FIFO_RX_FILTMASK_DEFAULT); 456188808Sgonzo 457199234Sgonzo /* 458199234Sgonzo * Check if we have single-PHY MAC or multi-PHY 459199234Sgonzo */ 460199234Sgonzo phys_total = 0; 461199234Sgonzo for (i = 0; i < ARGE_NPHY; i++) 462199234Sgonzo if (phymask & (1 << i)) 463199234Sgonzo phys_total ++; 464199234Sgonzo 465199234Sgonzo if (phys_total == 0) { 466199234Sgonzo error = EINVAL; 467188808Sgonzo goto fail; 468188808Sgonzo } 469188808Sgonzo 470199234Sgonzo if (phys_total == 1) { 471199234Sgonzo /* Do MII setup. */ 472213894Smarius error = mii_attach(dev, &sc->arge_miibus, ifp, 473213894Smarius arge_ifmedia_upd, arge_ifmedia_sts, BMSR_DEFCAPMASK, 474213894Smarius MII_PHY_ANY, MII_OFFSET_ANY, 0); 475213894Smarius if (error != 0) { 476213894Smarius device_printf(dev, "attaching PHYs failed\n"); 477199234Sgonzo goto fail; 478199234Sgonzo } 479199234Sgonzo } 480199234Sgonzo else { 481199234Sgonzo ifmedia_init(&sc->arge_ifmedia, 0, 482199234Sgonzo arge_multiphy_mediachange, 483199234Sgonzo arge_multiphy_mediastatus); 484199234Sgonzo ifmedia_add(&sc->arge_ifmedia, 485199234Sgonzo IFM_ETHER | sc->arge_media_type | sc->arge_duplex_mode, 486199234Sgonzo 0, NULL); 487199234Sgonzo ifmedia_set(&sc->arge_ifmedia, 488199234Sgonzo IFM_ETHER | sc->arge_media_type | sc->arge_duplex_mode); 489199234Sgonzo arge_set_pll(sc, sc->arge_media_type, sc->arge_duplex_mode); 490199234Sgonzo } 491199234Sgonzo 492188808Sgonzo /* Call MI attach routine. */ 493188808Sgonzo ether_ifattach(ifp, eaddr); 494188808Sgonzo 495188808Sgonzo /* Hook interrupt last to avoid having to lock softc */ 496188808Sgonzo error = bus_setup_intr(dev, sc->arge_irq, INTR_TYPE_NET | INTR_MPSAFE, 497188808Sgonzo arge_intr_filter, arge_intr, sc, &sc->arge_intrhand); 498188808Sgonzo 499188808Sgonzo if (error) { 500188808Sgonzo device_printf(dev, "couldn't set up irq\n"); 501188808Sgonzo ether_ifdetach(ifp); 502188808Sgonzo goto fail; 503188808Sgonzo } 504188808Sgonzo 505209802Sadrian /* setup sysctl variables */ 506209802Sadrian arge_attach_sysctl(dev); 507209802Sadrian 508188808Sgonzofail: 509188808Sgonzo if (error) 510188808Sgonzo arge_detach(dev); 511188808Sgonzo 512188808Sgonzo return (error); 513188808Sgonzo} 514188808Sgonzo 515188808Sgonzostatic int 516188808Sgonzoarge_detach(device_t dev) 517188808Sgonzo{ 518192783Sgonzo struct arge_softc *sc = device_get_softc(dev); 519188808Sgonzo struct ifnet *ifp = sc->arge_ifp; 520188808Sgonzo 521188808Sgonzo KASSERT(mtx_initialized(&sc->arge_mtx), ("arge mutex not initialized")); 522188808Sgonzo 523188808Sgonzo /* These should only be active if attach succeeded */ 524188808Sgonzo if (device_is_attached(dev)) { 525188808Sgonzo ARGE_LOCK(sc); 526188808Sgonzo sc->arge_detach = 1; 527192783Sgonzo#ifdef DEVICE_POLLING 528192783Sgonzo if (ifp->if_capenable & IFCAP_POLLING) 529192783Sgonzo ether_poll_deregister(ifp); 530192783Sgonzo#endif 531192783Sgonzo 532188808Sgonzo arge_stop(sc); 533188808Sgonzo ARGE_UNLOCK(sc); 534188808Sgonzo taskqueue_drain(taskqueue_swi, &sc->arge_link_task); 535188808Sgonzo ether_ifdetach(ifp); 536188808Sgonzo } 537188808Sgonzo 538188808Sgonzo if (sc->arge_miibus) 539188808Sgonzo device_delete_child(dev, sc->arge_miibus); 540199234Sgonzo 541188808Sgonzo bus_generic_detach(dev); 542188808Sgonzo 543188808Sgonzo if (sc->arge_intrhand) 544188808Sgonzo bus_teardown_intr(dev, sc->arge_irq, sc->arge_intrhand); 545188808Sgonzo 546188808Sgonzo if (sc->arge_res) 547188808Sgonzo bus_release_resource(dev, SYS_RES_MEMORY, sc->arge_rid, 548188808Sgonzo sc->arge_res); 549188808Sgonzo 550188808Sgonzo if (ifp) 551188808Sgonzo if_free(ifp); 552188808Sgonzo 553188808Sgonzo arge_dma_free(sc); 554188808Sgonzo 555188808Sgonzo mtx_destroy(&sc->arge_mtx); 556188808Sgonzo 557188808Sgonzo return (0); 558188808Sgonzo 559188808Sgonzo} 560188808Sgonzo 561188808Sgonzostatic int 562188808Sgonzoarge_suspend(device_t dev) 563188808Sgonzo{ 564188808Sgonzo 565188808Sgonzo panic("%s", __func__); 566188808Sgonzo return 0; 567188808Sgonzo} 568188808Sgonzo 569188808Sgonzostatic int 570188808Sgonzoarge_resume(device_t dev) 571188808Sgonzo{ 572188808Sgonzo 573188808Sgonzo panic("%s", __func__); 574188808Sgonzo return 0; 575188808Sgonzo} 576188808Sgonzo 577194059Sgonzostatic int 578188808Sgonzoarge_shutdown(device_t dev) 579188808Sgonzo{ 580188808Sgonzo struct arge_softc *sc; 581188808Sgonzo 582188808Sgonzo sc = device_get_softc(dev); 583188808Sgonzo 584188808Sgonzo ARGE_LOCK(sc); 585188808Sgonzo arge_stop(sc); 586188808Sgonzo ARGE_UNLOCK(sc); 587194059Sgonzo 588194059Sgonzo return (0); 589188808Sgonzo} 590188808Sgonzo 591188808Sgonzostatic int 592188808Sgonzoarge_miibus_readreg(device_t dev, int phy, int reg) 593188808Sgonzo{ 594188808Sgonzo struct arge_softc * sc = device_get_softc(dev); 595188808Sgonzo int i, result; 596196794Sgonzo uint32_t addr = (phy << MAC_MII_PHY_ADDR_SHIFT) 597188808Sgonzo | (reg & MAC_MII_REG_MASK); 598188808Sgonzo 599199234Sgonzo if ((sc->arge_phymask & (1 << phy)) == 0) 600188808Sgonzo return (0); 601188808Sgonzo 602199038Sgonzo mtx_lock(&miibus_mtx); 603199038Sgonzo ARGE_MII_WRITE(AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE); 604199038Sgonzo ARGE_MII_WRITE(AR71XX_MAC_MII_ADDR, addr); 605199038Sgonzo ARGE_MII_WRITE(AR71XX_MAC_MII_CMD, MAC_MII_CMD_READ); 606188808Sgonzo 607188808Sgonzo i = ARGE_MII_TIMEOUT; 608199038Sgonzo while ((ARGE_MII_READ(AR71XX_MAC_MII_INDICATOR) & 609188808Sgonzo MAC_MII_INDICATOR_BUSY) && (i--)) 610188808Sgonzo DELAY(5); 611188808Sgonzo 612188808Sgonzo if (i < 0) { 613199038Sgonzo mtx_unlock(&miibus_mtx); 614220354Sadrian ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__); 615188808Sgonzo /* XXX: return ERRNO istead? */ 616188808Sgonzo return (-1); 617188808Sgonzo } 618188808Sgonzo 619199038Sgonzo result = ARGE_MII_READ(AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK; 620199038Sgonzo ARGE_MII_WRITE(AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE); 621199038Sgonzo mtx_unlock(&miibus_mtx); 622199038Sgonzo 623220354Sadrian ARGEDEBUG(sc, ARGE_DBG_MII, "%s: phy=%d, reg=%02x, value[%08x]=%04x\n", __func__, 624188808Sgonzo phy, reg, addr, result); 625188808Sgonzo 626188808Sgonzo return (result); 627188808Sgonzo} 628188808Sgonzo 629188808Sgonzostatic int 630188808Sgonzoarge_miibus_writereg(device_t dev, int phy, int reg, int data) 631188808Sgonzo{ 632188808Sgonzo struct arge_softc * sc = device_get_softc(dev); 633188808Sgonzo int i; 634196794Sgonzo uint32_t addr = 635196794Sgonzo (phy << MAC_MII_PHY_ADDR_SHIFT) | (reg & MAC_MII_REG_MASK); 636188808Sgonzo 637199038Sgonzo 638199234Sgonzo if ((sc->arge_phymask & (1 << phy)) == 0) 639199038Sgonzo return (-1); 640199038Sgonzo 641220354Sadrian ARGEDEBUG(sc, ARGE_DBG_MII, "%s: phy=%d, reg=%02x, value=%04x\n", __func__, 642188808Sgonzo phy, reg, data); 643188808Sgonzo 644199038Sgonzo mtx_lock(&miibus_mtx); 645199038Sgonzo ARGE_MII_WRITE(AR71XX_MAC_MII_ADDR, addr); 646199038Sgonzo ARGE_MII_WRITE(AR71XX_MAC_MII_CONTROL, data); 647188808Sgonzo 648188808Sgonzo i = ARGE_MII_TIMEOUT; 649199038Sgonzo while ((ARGE_MII_READ(AR71XX_MAC_MII_INDICATOR) & 650188808Sgonzo MAC_MII_INDICATOR_BUSY) && (i--)) 651188808Sgonzo DELAY(5); 652188808Sgonzo 653199038Sgonzo mtx_unlock(&miibus_mtx); 654199038Sgonzo 655188808Sgonzo if (i < 0) { 656220354Sadrian ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__); 657188808Sgonzo /* XXX: return ERRNO istead? */ 658188808Sgonzo return (-1); 659188808Sgonzo } 660188808Sgonzo 661188808Sgonzo return (0); 662188808Sgonzo} 663188808Sgonzo 664188808Sgonzostatic void 665188808Sgonzoarge_miibus_statchg(device_t dev) 666188808Sgonzo{ 667188808Sgonzo struct arge_softc *sc; 668188808Sgonzo 669188808Sgonzo sc = device_get_softc(dev); 670188808Sgonzo taskqueue_enqueue(taskqueue_swi, &sc->arge_link_task); 671188808Sgonzo} 672188808Sgonzo 673188808Sgonzostatic void 674188808Sgonzoarge_link_task(void *arg, int pending) 675188808Sgonzo{ 676188808Sgonzo struct arge_softc *sc; 677188808Sgonzo struct mii_data *mii; 678188808Sgonzo struct ifnet *ifp; 679199234Sgonzo uint32_t media, duplex; 680188808Sgonzo 681188808Sgonzo sc = (struct arge_softc *)arg; 682188808Sgonzo 683188808Sgonzo ARGE_LOCK(sc); 684188808Sgonzo mii = device_get_softc(sc->arge_miibus); 685188808Sgonzo ifp = sc->arge_ifp; 686188808Sgonzo if (mii == NULL || ifp == NULL || 687188808Sgonzo (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 688188808Sgonzo ARGE_UNLOCK(sc); 689188808Sgonzo return; 690188808Sgonzo } 691188808Sgonzo 692188808Sgonzo if (mii->mii_media_status & IFM_ACTIVE) { 693188808Sgonzo 694188808Sgonzo media = IFM_SUBTYPE(mii->mii_media_active); 695188808Sgonzo 696188808Sgonzo if (media != IFM_NONE) { 697188808Sgonzo sc->arge_link_status = 1; 698199234Sgonzo duplex = mii->mii_media_active & IFM_GMASK; 699199234Sgonzo arge_set_pll(sc, media, duplex); 700199234Sgonzo } 701199234Sgonzo } else 702199234Sgonzo sc->arge_link_status = 0; 703188808Sgonzo 704199234Sgonzo ARGE_UNLOCK(sc); 705199234Sgonzo} 706192783Sgonzo 707199234Sgonzostatic void 708199234Sgonzoarge_set_pll(struct arge_softc *sc, int media, int duplex) 709199234Sgonzo{ 710211511Sadrian uint32_t cfg, ifcontrol, rx_filtmask; 711219589Sadrian uint32_t fifo_tx; 712211511Sadrian int if_speed; 713192783Sgonzo 714199234Sgonzo cfg = ARGE_READ(sc, AR71XX_MAC_CFG2); 715199234Sgonzo cfg &= ~(MAC_CFG2_IFACE_MODE_1000 716199234Sgonzo | MAC_CFG2_IFACE_MODE_10_100 717199234Sgonzo | MAC_CFG2_FULL_DUPLEX); 718188808Sgonzo 719199234Sgonzo if (duplex == IFM_FDX) 720199234Sgonzo cfg |= MAC_CFG2_FULL_DUPLEX; 721188808Sgonzo 722199234Sgonzo ifcontrol = ARGE_READ(sc, AR71XX_MAC_IFCONTROL); 723199234Sgonzo ifcontrol &= ~MAC_IFCONTROL_SPEED; 724199234Sgonzo rx_filtmask = 725199234Sgonzo ARGE_READ(sc, AR71XX_MAC_FIFO_RX_FILTMASK); 726199234Sgonzo rx_filtmask &= ~FIFO_RX_MASK_BYTE_MODE; 727188808Sgonzo 728199234Sgonzo switch(media) { 729199234Sgonzo case IFM_10_T: 730199234Sgonzo cfg |= MAC_CFG2_IFACE_MODE_10_100; 731211511Sadrian if_speed = 10; 732199234Sgonzo break; 733199234Sgonzo case IFM_100_TX: 734199234Sgonzo cfg |= MAC_CFG2_IFACE_MODE_10_100; 735199234Sgonzo ifcontrol |= MAC_IFCONTROL_SPEED; 736211511Sadrian if_speed = 100; 737199234Sgonzo break; 738199234Sgonzo case IFM_1000_T: 739199234Sgonzo case IFM_1000_SX: 740199234Sgonzo cfg |= MAC_CFG2_IFACE_MODE_1000; 741199234Sgonzo rx_filtmask |= FIFO_RX_MASK_BYTE_MODE; 742211511Sadrian if_speed = 1000; 743199234Sgonzo break; 744199234Sgonzo default: 745211511Sadrian if_speed = 100; 746199234Sgonzo device_printf(sc->arge_dev, 747199234Sgonzo "Unknown media %d\n", media); 748199234Sgonzo } 749188808Sgonzo 750219589Sadrian switch (ar71xx_soc) { 751219589Sadrian case AR71XX_SOC_AR7240: 752219589Sadrian case AR71XX_SOC_AR7241: 753219589Sadrian case AR71XX_SOC_AR7242: 754219589Sadrian fifo_tx = 0x01f00140; 755219589Sadrian break; 756219589Sadrian case AR71XX_SOC_AR9130: 757219589Sadrian case AR71XX_SOC_AR9132: 758219589Sadrian fifo_tx = 0x00780fff; 759219589Sadrian break; 760219589Sadrian default: 761219589Sadrian fifo_tx = 0x008001ff; 762219589Sadrian } 763188808Sgonzo 764199234Sgonzo ARGE_WRITE(sc, AR71XX_MAC_CFG2, cfg); 765199234Sgonzo ARGE_WRITE(sc, AR71XX_MAC_IFCONTROL, ifcontrol); 766199234Sgonzo ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK, 767199234Sgonzo rx_filtmask); 768219589Sadrian ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD, fifo_tx); 769188808Sgonzo 770199234Sgonzo /* set PLL registers */ 771211511Sadrian if (sc->arge_mac_unit == 0) 772211511Sadrian ar71xx_device_set_pll_ge0(if_speed); 773211511Sadrian else 774211511Sadrian ar71xx_device_set_pll_ge1(if_speed); 775188808Sgonzo} 776188808Sgonzo 777199234Sgonzo 778188808Sgonzostatic void 779188808Sgonzoarge_reset_dma(struct arge_softc *sc) 780188808Sgonzo{ 781188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, 0); 782188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 0); 783188808Sgonzo 784188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, 0); 785188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, 0); 786188808Sgonzo 787188808Sgonzo /* Clear all possible RX interrupts */ 788192569Sdwhite while(ARGE_READ(sc, AR71XX_DMA_RX_STATUS) & DMA_RX_STATUS_PKT_RECVD) 789188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD); 790188808Sgonzo 791188808Sgonzo /* 792188808Sgonzo * Clear all possible TX interrupts 793188808Sgonzo */ 794192569Sdwhite while(ARGE_READ(sc, AR71XX_DMA_TX_STATUS) & DMA_TX_STATUS_PKT_SENT) 795188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT); 796188808Sgonzo 797188808Sgonzo /* 798188808Sgonzo * Now Rx/Tx errors 799188808Sgonzo */ 800188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, 801188808Sgonzo DMA_RX_STATUS_BUS_ERROR | DMA_RX_STATUS_OVERFLOW); 802188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, 803188808Sgonzo DMA_TX_STATUS_BUS_ERROR | DMA_TX_STATUS_UNDERRUN); 804188808Sgonzo} 805188808Sgonzo 806188808Sgonzo 807188808Sgonzo 808188808Sgonzostatic void 809188808Sgonzoarge_init(void *xsc) 810188808Sgonzo{ 811188808Sgonzo struct arge_softc *sc = xsc; 812188808Sgonzo 813188808Sgonzo ARGE_LOCK(sc); 814188808Sgonzo arge_init_locked(sc); 815188808Sgonzo ARGE_UNLOCK(sc); 816188808Sgonzo} 817188808Sgonzo 818188808Sgonzostatic void 819188808Sgonzoarge_init_locked(struct arge_softc *sc) 820188808Sgonzo{ 821188808Sgonzo struct ifnet *ifp = sc->arge_ifp; 822188808Sgonzo struct mii_data *mii; 823188808Sgonzo 824188808Sgonzo ARGE_LOCK_ASSERT(sc); 825188808Sgonzo 826188808Sgonzo arge_stop(sc); 827188808Sgonzo 828188808Sgonzo /* Init circular RX list. */ 829188808Sgonzo if (arge_rx_ring_init(sc) != 0) { 830188808Sgonzo device_printf(sc->arge_dev, 831188808Sgonzo "initialization failed: no memory for rx buffers\n"); 832188808Sgonzo arge_stop(sc); 833188808Sgonzo return; 834188808Sgonzo } 835188808Sgonzo 836188808Sgonzo /* Init tx descriptors. */ 837188808Sgonzo arge_tx_ring_init(sc); 838188808Sgonzo 839188808Sgonzo arge_reset_dma(sc); 840188808Sgonzo 841188808Sgonzo 842199234Sgonzo if (sc->arge_miibus) { 843199234Sgonzo sc->arge_link_status = 0; 844199234Sgonzo mii = device_get_softc(sc->arge_miibus); 845199234Sgonzo mii_mediachg(mii); 846199234Sgonzo } 847199234Sgonzo else { 848199234Sgonzo /* 849199234Sgonzo * Sun always shines over multiPHY interface 850199234Sgonzo */ 851199234Sgonzo sc->arge_link_status = 1; 852199234Sgonzo } 853199234Sgonzo 854188808Sgonzo ifp->if_drv_flags |= IFF_DRV_RUNNING; 855188808Sgonzo ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 856188808Sgonzo 857199234Sgonzo if (sc->arge_miibus) 858199234Sgonzo callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc); 859192783Sgonzo 860188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, ARGE_TX_RING_ADDR(sc, 0)); 861188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, ARGE_RX_RING_ADDR(sc, 0)); 862188808Sgonzo 863188808Sgonzo /* Start listening */ 864188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN); 865188808Sgonzo 866188808Sgonzo /* Enable interrupts */ 867188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL); 868188808Sgonzo} 869188808Sgonzo 870188808Sgonzo/* 871209807Sadrian * Return whether the mbuf chain is correctly aligned 872209807Sadrian * for the arge TX engine. 873209807Sadrian * 874209807Sadrian * The TX engine requires each fragment to be aligned to a 875209807Sadrian * 4 byte boundary and the size of each fragment except 876209807Sadrian * the last to be a multiple of 4 bytes. 877209807Sadrian */ 878209807Sadrianstatic int 879209807Sadrianarge_mbuf_chain_is_tx_aligned(struct mbuf *m0) 880209807Sadrian{ 881209807Sadrian struct mbuf *m; 882209807Sadrian 883209807Sadrian for (m = m0; m != NULL; m = m->m_next) { 884209807Sadrian if((mtod(m, intptr_t) & 3) != 0) 885209807Sadrian return 0; 886209807Sadrian if ((m->m_next != NULL) && ((m->m_len & 0x03) != 0)) 887209807Sadrian return 0; 888209807Sadrian } 889209807Sadrian return 1; 890209807Sadrian} 891209807Sadrian 892209807Sadrian/* 893188808Sgonzo * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 894188808Sgonzo * pointers to the fragment pointers. 895188808Sgonzo */ 896188808Sgonzostatic int 897188808Sgonzoarge_encap(struct arge_softc *sc, struct mbuf **m_head) 898188808Sgonzo{ 899188808Sgonzo struct arge_txdesc *txd; 900188808Sgonzo struct arge_desc *desc, *prev_desc; 901188808Sgonzo bus_dma_segment_t txsegs[ARGE_MAXFRAGS]; 902192569Sdwhite int error, i, nsegs, prod, prev_prod; 903192783Sgonzo struct mbuf *m; 904188808Sgonzo 905188808Sgonzo ARGE_LOCK_ASSERT(sc); 906188808Sgonzo 907192783Sgonzo /* 908192783Sgonzo * Fix mbuf chain, all fragments should be 4 bytes aligned and 909192783Sgonzo * even 4 bytes 910192783Sgonzo */ 911192783Sgonzo m = *m_head; 912209807Sadrian if (! arge_mbuf_chain_is_tx_aligned(m)) { 913209809Sadrian sc->stats.tx_pkts_unaligned++; 914192783Sgonzo m = m_defrag(*m_head, M_DONTWAIT); 915192783Sgonzo if (m == NULL) { 916192783Sgonzo *m_head = NULL; 917192783Sgonzo return (ENOBUFS); 918192783Sgonzo } 919192783Sgonzo *m_head = m; 920209809Sadrian } else 921209809Sadrian sc->stats.tx_pkts_aligned++; 922192783Sgonzo 923188808Sgonzo prod = sc->arge_cdata.arge_tx_prod; 924188808Sgonzo txd = &sc->arge_cdata.arge_txdesc[prod]; 925188808Sgonzo error = bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_tx_tag, 926188808Sgonzo txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 927188808Sgonzo 928188808Sgonzo if (error == EFBIG) { 929188808Sgonzo panic("EFBIG"); 930188808Sgonzo } else if (error != 0) 931188808Sgonzo return (error); 932188808Sgonzo 933188808Sgonzo if (nsegs == 0) { 934188808Sgonzo m_freem(*m_head); 935188808Sgonzo *m_head = NULL; 936188808Sgonzo return (EIO); 937188808Sgonzo } 938188808Sgonzo 939188808Sgonzo /* Check number of available descriptors. */ 940188808Sgonzo if (sc->arge_cdata.arge_tx_cnt + nsegs >= (ARGE_TX_RING_COUNT - 1)) { 941188808Sgonzo bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap); 942188808Sgonzo return (ENOBUFS); 943188808Sgonzo } 944188808Sgonzo 945188808Sgonzo txd->tx_m = *m_head; 946188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap, 947188808Sgonzo BUS_DMASYNC_PREWRITE); 948188808Sgonzo 949188808Sgonzo /* 950188808Sgonzo * Make a list of descriptors for this packet. DMA controller will 951188808Sgonzo * walk through it while arge_link is not zero. 952188808Sgonzo */ 953188808Sgonzo prev_prod = prod; 954188808Sgonzo desc = prev_desc = NULL; 955188808Sgonzo for (i = 0; i < nsegs; i++) { 956188808Sgonzo desc = &sc->arge_rdata.arge_tx_ring[prod]; 957188808Sgonzo desc->packet_ctrl = ARGE_DMASIZE(txsegs[i].ds_len); 958188808Sgonzo 959192783Sgonzo if (txsegs[i].ds_addr & 3) 960192783Sgonzo panic("TX packet address unaligned\n"); 961192783Sgonzo 962188808Sgonzo desc->packet_addr = txsegs[i].ds_addr; 963192783Sgonzo 964188808Sgonzo /* link with previous descriptor */ 965188808Sgonzo if (prev_desc) 966188808Sgonzo prev_desc->packet_ctrl |= ARGE_DESC_MORE; 967188808Sgonzo 968188808Sgonzo sc->arge_cdata.arge_tx_cnt++; 969188808Sgonzo prev_desc = desc; 970188808Sgonzo ARGE_INC(prod, ARGE_TX_RING_COUNT); 971188808Sgonzo } 972188808Sgonzo 973188808Sgonzo /* Update producer index. */ 974188808Sgonzo sc->arge_cdata.arge_tx_prod = prod; 975188808Sgonzo 976188808Sgonzo /* Sync descriptors. */ 977188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag, 978188808Sgonzo sc->arge_cdata.arge_tx_ring_map, 979188808Sgonzo BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 980188808Sgonzo 981188808Sgonzo /* Start transmitting */ 982188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, DMA_TX_CONTROL_EN); 983188808Sgonzo return (0); 984188808Sgonzo} 985188808Sgonzo 986188808Sgonzostatic void 987188808Sgonzoarge_start(struct ifnet *ifp) 988188808Sgonzo{ 989188808Sgonzo struct arge_softc *sc; 990188808Sgonzo 991188808Sgonzo sc = ifp->if_softc; 992188808Sgonzo 993188808Sgonzo ARGE_LOCK(sc); 994188808Sgonzo arge_start_locked(ifp); 995188808Sgonzo ARGE_UNLOCK(sc); 996188808Sgonzo} 997188808Sgonzo 998188808Sgonzostatic void 999188808Sgonzoarge_start_locked(struct ifnet *ifp) 1000188808Sgonzo{ 1001188808Sgonzo struct arge_softc *sc; 1002188808Sgonzo struct mbuf *m_head; 1003188808Sgonzo int enq; 1004188808Sgonzo 1005188808Sgonzo sc = ifp->if_softc; 1006188808Sgonzo 1007188808Sgonzo ARGE_LOCK_ASSERT(sc); 1008188808Sgonzo 1009188808Sgonzo if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1010188808Sgonzo IFF_DRV_RUNNING || sc->arge_link_status == 0 ) 1011188808Sgonzo return; 1012188808Sgonzo 1013188808Sgonzo arge_flush_ddr(sc); 1014188808Sgonzo 1015188808Sgonzo for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1016188808Sgonzo sc->arge_cdata.arge_tx_cnt < ARGE_TX_RING_COUNT - 2; ) { 1017188808Sgonzo IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1018188808Sgonzo if (m_head == NULL) 1019188808Sgonzo break; 1020188808Sgonzo 1021188808Sgonzo 1022188808Sgonzo /* 1023188808Sgonzo * Pack the data into the transmit ring. 1024188808Sgonzo */ 1025188808Sgonzo if (arge_encap(sc, &m_head)) { 1026188808Sgonzo if (m_head == NULL) 1027188808Sgonzo break; 1028188808Sgonzo IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1029188808Sgonzo ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1030188808Sgonzo break; 1031188808Sgonzo } 1032188808Sgonzo 1033188808Sgonzo enq++; 1034188808Sgonzo /* 1035188808Sgonzo * If there's a BPF listener, bounce a copy of this frame 1036188808Sgonzo * to him. 1037188808Sgonzo */ 1038188808Sgonzo ETHER_BPF_MTAP(ifp, m_head); 1039188808Sgonzo } 1040188808Sgonzo} 1041188808Sgonzo 1042188808Sgonzostatic void 1043188808Sgonzoarge_stop(struct arge_softc *sc) 1044188808Sgonzo{ 1045188808Sgonzo struct ifnet *ifp; 1046188808Sgonzo 1047188808Sgonzo ARGE_LOCK_ASSERT(sc); 1048188808Sgonzo 1049188808Sgonzo ifp = sc->arge_ifp; 1050188808Sgonzo ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1051199234Sgonzo if (sc->arge_miibus) 1052199234Sgonzo callout_stop(&sc->arge_stat_callout); 1053188808Sgonzo 1054188808Sgonzo /* mask out interrupts */ 1055188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_INTR, 0); 1056188808Sgonzo 1057188808Sgonzo arge_reset_dma(sc); 1058188808Sgonzo} 1059188808Sgonzo 1060188808Sgonzo 1061188808Sgonzostatic int 1062188808Sgonzoarge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1063188808Sgonzo{ 1064188808Sgonzo struct arge_softc *sc = ifp->if_softc; 1065188808Sgonzo struct ifreq *ifr = (struct ifreq *) data; 1066188808Sgonzo struct mii_data *mii; 1067188808Sgonzo int error; 1068192783Sgonzo#ifdef DEVICE_POLLING 1069192783Sgonzo int mask; 1070192783Sgonzo#endif 1071188808Sgonzo 1072188808Sgonzo switch (command) { 1073188808Sgonzo case SIOCSIFFLAGS: 1074198932Sgonzo ARGE_LOCK(sc); 1075198932Sgonzo if ((ifp->if_flags & IFF_UP) != 0) { 1076198932Sgonzo if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1077198932Sgonzo if (((ifp->if_flags ^ sc->arge_if_flags) 1078198939Sgonzo & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1079198939Sgonzo /* XXX: handle promisc & multi flags */ 1080198939Sgonzo } 1081198939Sgonzo 1082198932Sgonzo } else { 1083198932Sgonzo if (!sc->arge_detach) 1084198932Sgonzo arge_init_locked(sc); 1085198932Sgonzo } 1086198932Sgonzo } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1087198932Sgonzo ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1088198932Sgonzo arge_stop(sc); 1089198932Sgonzo } 1090198932Sgonzo sc->arge_if_flags = ifp->if_flags; 1091198932Sgonzo ARGE_UNLOCK(sc); 1092188808Sgonzo error = 0; 1093188808Sgonzo break; 1094188808Sgonzo case SIOCADDMULTI: 1095188808Sgonzo case SIOCDELMULTI: 1096198932Sgonzo /* XXX: implement SIOCDELMULTI */ 1097188808Sgonzo error = 0; 1098188808Sgonzo break; 1099188808Sgonzo case SIOCGIFMEDIA: 1100188808Sgonzo case SIOCSIFMEDIA: 1101199234Sgonzo if (sc->arge_miibus) { 1102199234Sgonzo mii = device_get_softc(sc->arge_miibus); 1103199234Sgonzo error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1104199234Sgonzo } 1105199234Sgonzo else 1106199234Sgonzo error = ifmedia_ioctl(ifp, ifr, &sc->arge_ifmedia, command); 1107188808Sgonzo break; 1108198933Sgonzo case SIOCSIFCAP: 1109198932Sgonzo /* XXX: Check other capabilities */ 1110192783Sgonzo#ifdef DEVICE_POLLING 1111198933Sgonzo mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1112198933Sgonzo if (mask & IFCAP_POLLING) { 1113198933Sgonzo if (ifr->ifr_reqcap & IFCAP_POLLING) { 1114192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_INTR, 0); 1115198933Sgonzo error = ether_poll_register(arge_poll, ifp); 1116198933Sgonzo if (error) 1117198933Sgonzo return error; 1118198933Sgonzo ARGE_LOCK(sc); 1119198933Sgonzo ifp->if_capenable |= IFCAP_POLLING; 1120198933Sgonzo ARGE_UNLOCK(sc); 1121198933Sgonzo } else { 1122192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL); 1123198933Sgonzo error = ether_poll_deregister(ifp); 1124198933Sgonzo ARGE_LOCK(sc); 1125198933Sgonzo ifp->if_capenable &= ~IFCAP_POLLING; 1126198933Sgonzo ARGE_UNLOCK(sc); 1127198933Sgonzo } 1128198933Sgonzo } 1129198932Sgonzo error = 0; 1130198933Sgonzo break; 1131192783Sgonzo#endif 1132188808Sgonzo default: 1133188808Sgonzo error = ether_ioctl(ifp, command, data); 1134188808Sgonzo break; 1135188808Sgonzo } 1136188808Sgonzo 1137188808Sgonzo return (error); 1138188808Sgonzo} 1139188808Sgonzo 1140188808Sgonzo/* 1141188808Sgonzo * Set media options. 1142188808Sgonzo */ 1143188808Sgonzostatic int 1144188808Sgonzoarge_ifmedia_upd(struct ifnet *ifp) 1145188808Sgonzo{ 1146188808Sgonzo struct arge_softc *sc; 1147188808Sgonzo struct mii_data *mii; 1148188808Sgonzo struct mii_softc *miisc; 1149188808Sgonzo int error; 1150188808Sgonzo 1151188808Sgonzo sc = ifp->if_softc; 1152188808Sgonzo ARGE_LOCK(sc); 1153188808Sgonzo mii = device_get_softc(sc->arge_miibus); 1154188808Sgonzo if (mii->mii_instance) { 1155188808Sgonzo LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1156188808Sgonzo mii_phy_reset(miisc); 1157188808Sgonzo } 1158188808Sgonzo error = mii_mediachg(mii); 1159188808Sgonzo ARGE_UNLOCK(sc); 1160188808Sgonzo 1161188808Sgonzo return (error); 1162188808Sgonzo} 1163188808Sgonzo 1164188808Sgonzo/* 1165188808Sgonzo * Report current media status. 1166188808Sgonzo */ 1167188808Sgonzostatic void 1168188808Sgonzoarge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1169188808Sgonzo{ 1170188808Sgonzo struct arge_softc *sc = ifp->if_softc; 1171188808Sgonzo struct mii_data *mii; 1172188808Sgonzo 1173188808Sgonzo mii = device_get_softc(sc->arge_miibus); 1174188808Sgonzo ARGE_LOCK(sc); 1175188808Sgonzo mii_pollstat(mii); 1176188808Sgonzo ARGE_UNLOCK(sc); 1177188808Sgonzo ifmr->ifm_active = mii->mii_media_active; 1178188808Sgonzo ifmr->ifm_status = mii->mii_media_status; 1179188808Sgonzo} 1180188808Sgonzo 1181188808Sgonzostruct arge_dmamap_arg { 1182188808Sgonzo bus_addr_t arge_busaddr; 1183188808Sgonzo}; 1184188808Sgonzo 1185188808Sgonzostatic void 1186188808Sgonzoarge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1187188808Sgonzo{ 1188188808Sgonzo struct arge_dmamap_arg *ctx; 1189188808Sgonzo 1190188808Sgonzo if (error != 0) 1191188808Sgonzo return; 1192188808Sgonzo ctx = arg; 1193188808Sgonzo ctx->arge_busaddr = segs[0].ds_addr; 1194188808Sgonzo} 1195188808Sgonzo 1196188808Sgonzostatic int 1197188808Sgonzoarge_dma_alloc(struct arge_softc *sc) 1198188808Sgonzo{ 1199188808Sgonzo struct arge_dmamap_arg ctx; 1200188808Sgonzo struct arge_txdesc *txd; 1201188808Sgonzo struct arge_rxdesc *rxd; 1202188808Sgonzo int error, i; 1203188808Sgonzo 1204188808Sgonzo /* Create parent DMA tag. */ 1205188808Sgonzo error = bus_dma_tag_create( 1206188808Sgonzo bus_get_dma_tag(sc->arge_dev), /* parent */ 1207188808Sgonzo 1, 0, /* alignment, boundary */ 1208188808Sgonzo BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1209188808Sgonzo BUS_SPACE_MAXADDR, /* highaddr */ 1210188808Sgonzo NULL, NULL, /* filter, filterarg */ 1211188808Sgonzo BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1212188808Sgonzo 0, /* nsegments */ 1213188808Sgonzo BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1214188808Sgonzo 0, /* flags */ 1215188808Sgonzo NULL, NULL, /* lockfunc, lockarg */ 1216188808Sgonzo &sc->arge_cdata.arge_parent_tag); 1217188808Sgonzo if (error != 0) { 1218188808Sgonzo device_printf(sc->arge_dev, "failed to create parent DMA tag\n"); 1219188808Sgonzo goto fail; 1220188808Sgonzo } 1221188808Sgonzo /* Create tag for Tx ring. */ 1222188808Sgonzo error = bus_dma_tag_create( 1223188808Sgonzo sc->arge_cdata.arge_parent_tag, /* parent */ 1224188808Sgonzo ARGE_RING_ALIGN, 0, /* alignment, boundary */ 1225188808Sgonzo BUS_SPACE_MAXADDR, /* lowaddr */ 1226188808Sgonzo BUS_SPACE_MAXADDR, /* highaddr */ 1227188808Sgonzo NULL, NULL, /* filter, filterarg */ 1228188808Sgonzo ARGE_TX_DMA_SIZE, /* maxsize */ 1229188808Sgonzo 1, /* nsegments */ 1230188808Sgonzo ARGE_TX_DMA_SIZE, /* maxsegsize */ 1231188808Sgonzo 0, /* flags */ 1232188808Sgonzo NULL, NULL, /* lockfunc, lockarg */ 1233188808Sgonzo &sc->arge_cdata.arge_tx_ring_tag); 1234188808Sgonzo if (error != 0) { 1235188808Sgonzo device_printf(sc->arge_dev, "failed to create Tx ring DMA tag\n"); 1236188808Sgonzo goto fail; 1237188808Sgonzo } 1238188808Sgonzo 1239188808Sgonzo /* Create tag for Rx ring. */ 1240188808Sgonzo error = bus_dma_tag_create( 1241188808Sgonzo sc->arge_cdata.arge_parent_tag, /* parent */ 1242188808Sgonzo ARGE_RING_ALIGN, 0, /* alignment, boundary */ 1243188808Sgonzo BUS_SPACE_MAXADDR, /* lowaddr */ 1244188808Sgonzo BUS_SPACE_MAXADDR, /* highaddr */ 1245188808Sgonzo NULL, NULL, /* filter, filterarg */ 1246188808Sgonzo ARGE_RX_DMA_SIZE, /* maxsize */ 1247188808Sgonzo 1, /* nsegments */ 1248188808Sgonzo ARGE_RX_DMA_SIZE, /* maxsegsize */ 1249188808Sgonzo 0, /* flags */ 1250188808Sgonzo NULL, NULL, /* lockfunc, lockarg */ 1251188808Sgonzo &sc->arge_cdata.arge_rx_ring_tag); 1252188808Sgonzo if (error != 0) { 1253188808Sgonzo device_printf(sc->arge_dev, "failed to create Rx ring DMA tag\n"); 1254188808Sgonzo goto fail; 1255188808Sgonzo } 1256188808Sgonzo 1257188808Sgonzo /* Create tag for Tx buffers. */ 1258188808Sgonzo error = bus_dma_tag_create( 1259188808Sgonzo sc->arge_cdata.arge_parent_tag, /* parent */ 1260188808Sgonzo sizeof(uint32_t), 0, /* alignment, boundary */ 1261188808Sgonzo BUS_SPACE_MAXADDR, /* lowaddr */ 1262188808Sgonzo BUS_SPACE_MAXADDR, /* highaddr */ 1263188808Sgonzo NULL, NULL, /* filter, filterarg */ 1264188808Sgonzo MCLBYTES * ARGE_MAXFRAGS, /* maxsize */ 1265188808Sgonzo ARGE_MAXFRAGS, /* nsegments */ 1266188808Sgonzo MCLBYTES, /* maxsegsize */ 1267188808Sgonzo 0, /* flags */ 1268188808Sgonzo NULL, NULL, /* lockfunc, lockarg */ 1269188808Sgonzo &sc->arge_cdata.arge_tx_tag); 1270188808Sgonzo if (error != 0) { 1271188808Sgonzo device_printf(sc->arge_dev, "failed to create Tx DMA tag\n"); 1272188808Sgonzo goto fail; 1273188808Sgonzo } 1274188808Sgonzo 1275188808Sgonzo /* Create tag for Rx buffers. */ 1276188808Sgonzo error = bus_dma_tag_create( 1277188808Sgonzo sc->arge_cdata.arge_parent_tag, /* parent */ 1278188808Sgonzo ARGE_RX_ALIGN, 0, /* alignment, boundary */ 1279188808Sgonzo BUS_SPACE_MAXADDR, /* lowaddr */ 1280188808Sgonzo BUS_SPACE_MAXADDR, /* highaddr */ 1281188808Sgonzo NULL, NULL, /* filter, filterarg */ 1282188808Sgonzo MCLBYTES, /* maxsize */ 1283192821Sgonzo ARGE_MAXFRAGS, /* nsegments */ 1284188808Sgonzo MCLBYTES, /* maxsegsize */ 1285188808Sgonzo 0, /* flags */ 1286188808Sgonzo NULL, NULL, /* lockfunc, lockarg */ 1287188808Sgonzo &sc->arge_cdata.arge_rx_tag); 1288188808Sgonzo if (error != 0) { 1289188808Sgonzo device_printf(sc->arge_dev, "failed to create Rx DMA tag\n"); 1290188808Sgonzo goto fail; 1291188808Sgonzo } 1292188808Sgonzo 1293188808Sgonzo /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1294188808Sgonzo error = bus_dmamem_alloc(sc->arge_cdata.arge_tx_ring_tag, 1295188808Sgonzo (void **)&sc->arge_rdata.arge_tx_ring, BUS_DMA_WAITOK | 1296188808Sgonzo BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->arge_cdata.arge_tx_ring_map); 1297188808Sgonzo if (error != 0) { 1298188808Sgonzo device_printf(sc->arge_dev, 1299188808Sgonzo "failed to allocate DMA'able memory for Tx ring\n"); 1300188808Sgonzo goto fail; 1301188808Sgonzo } 1302188808Sgonzo 1303188808Sgonzo ctx.arge_busaddr = 0; 1304188808Sgonzo error = bus_dmamap_load(sc->arge_cdata.arge_tx_ring_tag, 1305188808Sgonzo sc->arge_cdata.arge_tx_ring_map, sc->arge_rdata.arge_tx_ring, 1306188808Sgonzo ARGE_TX_DMA_SIZE, arge_dmamap_cb, &ctx, 0); 1307188808Sgonzo if (error != 0 || ctx.arge_busaddr == 0) { 1308188808Sgonzo device_printf(sc->arge_dev, 1309188808Sgonzo "failed to load DMA'able memory for Tx ring\n"); 1310188808Sgonzo goto fail; 1311188808Sgonzo } 1312188808Sgonzo sc->arge_rdata.arge_tx_ring_paddr = ctx.arge_busaddr; 1313188808Sgonzo 1314188808Sgonzo /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1315188808Sgonzo error = bus_dmamem_alloc(sc->arge_cdata.arge_rx_ring_tag, 1316188808Sgonzo (void **)&sc->arge_rdata.arge_rx_ring, BUS_DMA_WAITOK | 1317188808Sgonzo BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->arge_cdata.arge_rx_ring_map); 1318188808Sgonzo if (error != 0) { 1319188808Sgonzo device_printf(sc->arge_dev, 1320188808Sgonzo "failed to allocate DMA'able memory for Rx ring\n"); 1321188808Sgonzo goto fail; 1322188808Sgonzo } 1323188808Sgonzo 1324188808Sgonzo ctx.arge_busaddr = 0; 1325188808Sgonzo error = bus_dmamap_load(sc->arge_cdata.arge_rx_ring_tag, 1326188808Sgonzo sc->arge_cdata.arge_rx_ring_map, sc->arge_rdata.arge_rx_ring, 1327188808Sgonzo ARGE_RX_DMA_SIZE, arge_dmamap_cb, &ctx, 0); 1328188808Sgonzo if (error != 0 || ctx.arge_busaddr == 0) { 1329188808Sgonzo device_printf(sc->arge_dev, 1330188808Sgonzo "failed to load DMA'able memory for Rx ring\n"); 1331188808Sgonzo goto fail; 1332188808Sgonzo } 1333188808Sgonzo sc->arge_rdata.arge_rx_ring_paddr = ctx.arge_busaddr; 1334188808Sgonzo 1335188808Sgonzo /* Create DMA maps for Tx buffers. */ 1336188808Sgonzo for (i = 0; i < ARGE_TX_RING_COUNT; i++) { 1337188808Sgonzo txd = &sc->arge_cdata.arge_txdesc[i]; 1338188808Sgonzo txd->tx_m = NULL; 1339188808Sgonzo txd->tx_dmamap = NULL; 1340188808Sgonzo error = bus_dmamap_create(sc->arge_cdata.arge_tx_tag, 0, 1341188808Sgonzo &txd->tx_dmamap); 1342188808Sgonzo if (error != 0) { 1343188808Sgonzo device_printf(sc->arge_dev, 1344188808Sgonzo "failed to create Tx dmamap\n"); 1345188808Sgonzo goto fail; 1346188808Sgonzo } 1347188808Sgonzo } 1348188808Sgonzo /* Create DMA maps for Rx buffers. */ 1349188808Sgonzo if ((error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0, 1350188808Sgonzo &sc->arge_cdata.arge_rx_sparemap)) != 0) { 1351188808Sgonzo device_printf(sc->arge_dev, 1352188808Sgonzo "failed to create spare Rx dmamap\n"); 1353188808Sgonzo goto fail; 1354188808Sgonzo } 1355188808Sgonzo for (i = 0; i < ARGE_RX_RING_COUNT; i++) { 1356188808Sgonzo rxd = &sc->arge_cdata.arge_rxdesc[i]; 1357188808Sgonzo rxd->rx_m = NULL; 1358188808Sgonzo rxd->rx_dmamap = NULL; 1359188808Sgonzo error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0, 1360188808Sgonzo &rxd->rx_dmamap); 1361188808Sgonzo if (error != 0) { 1362188808Sgonzo device_printf(sc->arge_dev, 1363188808Sgonzo "failed to create Rx dmamap\n"); 1364188808Sgonzo goto fail; 1365188808Sgonzo } 1366188808Sgonzo } 1367188808Sgonzo 1368188808Sgonzofail: 1369188808Sgonzo return (error); 1370188808Sgonzo} 1371188808Sgonzo 1372188808Sgonzostatic void 1373188808Sgonzoarge_dma_free(struct arge_softc *sc) 1374188808Sgonzo{ 1375188808Sgonzo struct arge_txdesc *txd; 1376188808Sgonzo struct arge_rxdesc *rxd; 1377188808Sgonzo int i; 1378188808Sgonzo 1379188808Sgonzo /* Tx ring. */ 1380188808Sgonzo if (sc->arge_cdata.arge_tx_ring_tag) { 1381188808Sgonzo if (sc->arge_cdata.arge_tx_ring_map) 1382188808Sgonzo bus_dmamap_unload(sc->arge_cdata.arge_tx_ring_tag, 1383188808Sgonzo sc->arge_cdata.arge_tx_ring_map); 1384188808Sgonzo if (sc->arge_cdata.arge_tx_ring_map && 1385188808Sgonzo sc->arge_rdata.arge_tx_ring) 1386188808Sgonzo bus_dmamem_free(sc->arge_cdata.arge_tx_ring_tag, 1387188808Sgonzo sc->arge_rdata.arge_tx_ring, 1388188808Sgonzo sc->arge_cdata.arge_tx_ring_map); 1389188808Sgonzo sc->arge_rdata.arge_tx_ring = NULL; 1390188808Sgonzo sc->arge_cdata.arge_tx_ring_map = NULL; 1391188808Sgonzo bus_dma_tag_destroy(sc->arge_cdata.arge_tx_ring_tag); 1392188808Sgonzo sc->arge_cdata.arge_tx_ring_tag = NULL; 1393188808Sgonzo } 1394188808Sgonzo /* Rx ring. */ 1395188808Sgonzo if (sc->arge_cdata.arge_rx_ring_tag) { 1396188808Sgonzo if (sc->arge_cdata.arge_rx_ring_map) 1397188808Sgonzo bus_dmamap_unload(sc->arge_cdata.arge_rx_ring_tag, 1398188808Sgonzo sc->arge_cdata.arge_rx_ring_map); 1399188808Sgonzo if (sc->arge_cdata.arge_rx_ring_map && 1400188808Sgonzo sc->arge_rdata.arge_rx_ring) 1401188808Sgonzo bus_dmamem_free(sc->arge_cdata.arge_rx_ring_tag, 1402188808Sgonzo sc->arge_rdata.arge_rx_ring, 1403188808Sgonzo sc->arge_cdata.arge_rx_ring_map); 1404188808Sgonzo sc->arge_rdata.arge_rx_ring = NULL; 1405188808Sgonzo sc->arge_cdata.arge_rx_ring_map = NULL; 1406188808Sgonzo bus_dma_tag_destroy(sc->arge_cdata.arge_rx_ring_tag); 1407188808Sgonzo sc->arge_cdata.arge_rx_ring_tag = NULL; 1408188808Sgonzo } 1409188808Sgonzo /* Tx buffers. */ 1410188808Sgonzo if (sc->arge_cdata.arge_tx_tag) { 1411188808Sgonzo for (i = 0; i < ARGE_TX_RING_COUNT; i++) { 1412188808Sgonzo txd = &sc->arge_cdata.arge_txdesc[i]; 1413188808Sgonzo if (txd->tx_dmamap) { 1414188808Sgonzo bus_dmamap_destroy(sc->arge_cdata.arge_tx_tag, 1415188808Sgonzo txd->tx_dmamap); 1416188808Sgonzo txd->tx_dmamap = NULL; 1417188808Sgonzo } 1418188808Sgonzo } 1419188808Sgonzo bus_dma_tag_destroy(sc->arge_cdata.arge_tx_tag); 1420188808Sgonzo sc->arge_cdata.arge_tx_tag = NULL; 1421188808Sgonzo } 1422188808Sgonzo /* Rx buffers. */ 1423188808Sgonzo if (sc->arge_cdata.arge_rx_tag) { 1424188808Sgonzo for (i = 0; i < ARGE_RX_RING_COUNT; i++) { 1425188808Sgonzo rxd = &sc->arge_cdata.arge_rxdesc[i]; 1426188808Sgonzo if (rxd->rx_dmamap) { 1427188808Sgonzo bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag, 1428188808Sgonzo rxd->rx_dmamap); 1429188808Sgonzo rxd->rx_dmamap = NULL; 1430188808Sgonzo } 1431188808Sgonzo } 1432188808Sgonzo if (sc->arge_cdata.arge_rx_sparemap) { 1433188808Sgonzo bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag, 1434188808Sgonzo sc->arge_cdata.arge_rx_sparemap); 1435188808Sgonzo sc->arge_cdata.arge_rx_sparemap = 0; 1436188808Sgonzo } 1437188808Sgonzo bus_dma_tag_destroy(sc->arge_cdata.arge_rx_tag); 1438188808Sgonzo sc->arge_cdata.arge_rx_tag = NULL; 1439188808Sgonzo } 1440188808Sgonzo 1441188808Sgonzo if (sc->arge_cdata.arge_parent_tag) { 1442188808Sgonzo bus_dma_tag_destroy(sc->arge_cdata.arge_parent_tag); 1443188808Sgonzo sc->arge_cdata.arge_parent_tag = NULL; 1444188808Sgonzo } 1445188808Sgonzo} 1446188808Sgonzo 1447188808Sgonzo/* 1448188808Sgonzo * Initialize the transmit descriptors. 1449188808Sgonzo */ 1450188808Sgonzostatic int 1451188808Sgonzoarge_tx_ring_init(struct arge_softc *sc) 1452188808Sgonzo{ 1453188808Sgonzo struct arge_ring_data *rd; 1454188808Sgonzo struct arge_txdesc *txd; 1455188808Sgonzo bus_addr_t addr; 1456188808Sgonzo int i; 1457188808Sgonzo 1458188808Sgonzo sc->arge_cdata.arge_tx_prod = 0; 1459188808Sgonzo sc->arge_cdata.arge_tx_cons = 0; 1460188808Sgonzo sc->arge_cdata.arge_tx_cnt = 0; 1461188808Sgonzo 1462188808Sgonzo rd = &sc->arge_rdata; 1463188808Sgonzo bzero(rd->arge_tx_ring, sizeof(rd->arge_tx_ring)); 1464188808Sgonzo for (i = 0; i < ARGE_TX_RING_COUNT; i++) { 1465188808Sgonzo if (i == ARGE_TX_RING_COUNT - 1) 1466188808Sgonzo addr = ARGE_TX_RING_ADDR(sc, 0); 1467188808Sgonzo else 1468188808Sgonzo addr = ARGE_TX_RING_ADDR(sc, i + 1); 1469188808Sgonzo rd->arge_tx_ring[i].packet_ctrl = ARGE_DESC_EMPTY; 1470188808Sgonzo rd->arge_tx_ring[i].next_desc = addr; 1471188808Sgonzo txd = &sc->arge_cdata.arge_txdesc[i]; 1472188808Sgonzo txd->tx_m = NULL; 1473188808Sgonzo } 1474188808Sgonzo 1475188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag, 1476188808Sgonzo sc->arge_cdata.arge_tx_ring_map, 1477188808Sgonzo BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1478188808Sgonzo 1479188808Sgonzo return (0); 1480188808Sgonzo} 1481188808Sgonzo 1482188808Sgonzo/* 1483188808Sgonzo * Initialize the RX descriptors and allocate mbufs for them. Note that 1484188808Sgonzo * we arrange the descriptors in a closed ring, so that the last descriptor 1485188808Sgonzo * points back to the first. 1486188808Sgonzo */ 1487188808Sgonzostatic int 1488188808Sgonzoarge_rx_ring_init(struct arge_softc *sc) 1489188808Sgonzo{ 1490188808Sgonzo struct arge_ring_data *rd; 1491188808Sgonzo struct arge_rxdesc *rxd; 1492188808Sgonzo bus_addr_t addr; 1493188808Sgonzo int i; 1494188808Sgonzo 1495188808Sgonzo sc->arge_cdata.arge_rx_cons = 0; 1496188808Sgonzo 1497188808Sgonzo rd = &sc->arge_rdata; 1498188808Sgonzo bzero(rd->arge_rx_ring, sizeof(rd->arge_rx_ring)); 1499188808Sgonzo for (i = 0; i < ARGE_RX_RING_COUNT; i++) { 1500188808Sgonzo rxd = &sc->arge_cdata.arge_rxdesc[i]; 1501188808Sgonzo rxd->rx_m = NULL; 1502188808Sgonzo rxd->desc = &rd->arge_rx_ring[i]; 1503188808Sgonzo if (i == ARGE_RX_RING_COUNT - 1) 1504188808Sgonzo addr = ARGE_RX_RING_ADDR(sc, 0); 1505188808Sgonzo else 1506188808Sgonzo addr = ARGE_RX_RING_ADDR(sc, i + 1); 1507188808Sgonzo rd->arge_rx_ring[i].next_desc = addr; 1508192783Sgonzo if (arge_newbuf(sc, i) != 0) { 1509188808Sgonzo return (ENOBUFS); 1510192783Sgonzo } 1511188808Sgonzo } 1512188808Sgonzo 1513188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag, 1514188808Sgonzo sc->arge_cdata.arge_rx_ring_map, 1515195434Sgonzo BUS_DMASYNC_PREWRITE); 1516188808Sgonzo 1517188808Sgonzo return (0); 1518188808Sgonzo} 1519188808Sgonzo 1520188808Sgonzo/* 1521188808Sgonzo * Initialize an RX descriptor and attach an MBUF cluster. 1522188808Sgonzo */ 1523188808Sgonzostatic int 1524188808Sgonzoarge_newbuf(struct arge_softc *sc, int idx) 1525188808Sgonzo{ 1526188808Sgonzo struct arge_desc *desc; 1527188808Sgonzo struct arge_rxdesc *rxd; 1528188808Sgonzo struct mbuf *m; 1529188808Sgonzo bus_dma_segment_t segs[1]; 1530188808Sgonzo bus_dmamap_t map; 1531188808Sgonzo int nsegs; 1532188808Sgonzo 1533188808Sgonzo m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1534188808Sgonzo if (m == NULL) 1535188808Sgonzo return (ENOBUFS); 1536188808Sgonzo m->m_len = m->m_pkthdr.len = MCLBYTES; 1537188808Sgonzo m_adj(m, sizeof(uint64_t)); 1538188808Sgonzo 1539188808Sgonzo if (bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_rx_tag, 1540188808Sgonzo sc->arge_cdata.arge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1541188808Sgonzo m_freem(m); 1542188808Sgonzo return (ENOBUFS); 1543188808Sgonzo } 1544188808Sgonzo KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1545188808Sgonzo 1546188808Sgonzo rxd = &sc->arge_cdata.arge_rxdesc[idx]; 1547188808Sgonzo if (rxd->rx_m != NULL) { 1548188808Sgonzo bus_dmamap_unload(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap); 1549188808Sgonzo } 1550188808Sgonzo map = rxd->rx_dmamap; 1551188808Sgonzo rxd->rx_dmamap = sc->arge_cdata.arge_rx_sparemap; 1552188808Sgonzo sc->arge_cdata.arge_rx_sparemap = map; 1553188808Sgonzo rxd->rx_m = m; 1554188808Sgonzo desc = rxd->desc; 1555192783Sgonzo if (segs[0].ds_addr & 3) 1556192783Sgonzo panic("RX packet address unaligned"); 1557188808Sgonzo desc->packet_addr = segs[0].ds_addr; 1558192783Sgonzo desc->packet_ctrl = ARGE_DESC_EMPTY | ARGE_DMASIZE(segs[0].ds_len); 1559188808Sgonzo 1560195434Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag, 1561195434Sgonzo sc->arge_cdata.arge_rx_ring_map, 1562195434Sgonzo BUS_DMASYNC_PREWRITE); 1563195434Sgonzo 1564188808Sgonzo return (0); 1565188808Sgonzo} 1566188808Sgonzo 1567188808Sgonzostatic __inline void 1568188808Sgonzoarge_fixup_rx(struct mbuf *m) 1569188808Sgonzo{ 1570198933Sgonzo int i; 1571198933Sgonzo uint16_t *src, *dst; 1572188808Sgonzo 1573188808Sgonzo src = mtod(m, uint16_t *); 1574188808Sgonzo dst = src - 1; 1575188808Sgonzo 1576195434Sgonzo for (i = 0; i < m->m_len / sizeof(uint16_t); i++) { 1577188808Sgonzo *dst++ = *src++; 1578195434Sgonzo } 1579188808Sgonzo 1580195434Sgonzo if (m->m_len % sizeof(uint16_t)) 1581195434Sgonzo *(uint8_t *)dst = *(uint8_t *)src; 1582195434Sgonzo 1583188808Sgonzo m->m_data -= ETHER_ALIGN; 1584188808Sgonzo} 1585188808Sgonzo 1586192783Sgonzo#ifdef DEVICE_POLLING 1587198667Sgonzostatic int 1588192783Sgonzoarge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1589192783Sgonzo{ 1590192783Sgonzo struct arge_softc *sc = ifp->if_softc; 1591198667Sgonzo int rx_npkts = 0; 1592188808Sgonzo 1593198933Sgonzo if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1594192783Sgonzo ARGE_LOCK(sc); 1595192783Sgonzo arge_tx_locked(sc); 1596198667Sgonzo rx_npkts = arge_rx_locked(sc); 1597192783Sgonzo ARGE_UNLOCK(sc); 1598198933Sgonzo } 1599198667Sgonzo 1600198667Sgonzo return (rx_npkts); 1601192783Sgonzo} 1602192783Sgonzo#endif /* DEVICE_POLLING */ 1603192783Sgonzo 1604192783Sgonzo 1605188808Sgonzostatic void 1606188808Sgonzoarge_tx_locked(struct arge_softc *sc) 1607188808Sgonzo{ 1608188808Sgonzo struct arge_txdesc *txd; 1609188808Sgonzo struct arge_desc *cur_tx; 1610188808Sgonzo struct ifnet *ifp; 1611188808Sgonzo uint32_t ctrl; 1612188808Sgonzo int cons, prod; 1613188808Sgonzo 1614188808Sgonzo ARGE_LOCK_ASSERT(sc); 1615188808Sgonzo 1616188808Sgonzo cons = sc->arge_cdata.arge_tx_cons; 1617188808Sgonzo prod = sc->arge_cdata.arge_tx_prod; 1618188808Sgonzo if (cons == prod) 1619188808Sgonzo return; 1620188808Sgonzo 1621188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag, 1622188808Sgonzo sc->arge_cdata.arge_tx_ring_map, 1623188808Sgonzo BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1624188808Sgonzo 1625188808Sgonzo ifp = sc->arge_ifp; 1626188808Sgonzo /* 1627188808Sgonzo * Go through our tx list and free mbufs for those 1628188808Sgonzo * frames that have been transmitted. 1629188808Sgonzo */ 1630188808Sgonzo for (; cons != prod; ARGE_INC(cons, ARGE_TX_RING_COUNT)) { 1631188808Sgonzo cur_tx = &sc->arge_rdata.arge_tx_ring[cons]; 1632188808Sgonzo ctrl = cur_tx->packet_ctrl; 1633188808Sgonzo /* Check if descriptor has "finished" flag */ 1634188808Sgonzo if ((ctrl & ARGE_DESC_EMPTY) == 0) 1635188808Sgonzo break; 1636188808Sgonzo 1637188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT); 1638188808Sgonzo 1639188808Sgonzo sc->arge_cdata.arge_tx_cnt--; 1640188808Sgonzo ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1641188808Sgonzo 1642188808Sgonzo txd = &sc->arge_cdata.arge_txdesc[cons]; 1643188808Sgonzo 1644188808Sgonzo ifp->if_opackets++; 1645188808Sgonzo 1646188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap, 1647188808Sgonzo BUS_DMASYNC_POSTWRITE); 1648188808Sgonzo bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap); 1649188808Sgonzo 1650188808Sgonzo /* Free only if it's first descriptor in list */ 1651188808Sgonzo if (txd->tx_m) 1652188808Sgonzo m_freem(txd->tx_m); 1653188808Sgonzo txd->tx_m = NULL; 1654188808Sgonzo 1655188808Sgonzo /* reset descriptor */ 1656188808Sgonzo cur_tx->packet_addr = 0; 1657188808Sgonzo } 1658188808Sgonzo 1659188808Sgonzo sc->arge_cdata.arge_tx_cons = cons; 1660188808Sgonzo 1661188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag, 1662188808Sgonzo sc->arge_cdata.arge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1663188808Sgonzo} 1664188808Sgonzo 1665188808Sgonzo 1666198667Sgonzostatic int 1667188808Sgonzoarge_rx_locked(struct arge_softc *sc) 1668188808Sgonzo{ 1669188808Sgonzo struct arge_rxdesc *rxd; 1670188808Sgonzo struct ifnet *ifp = sc->arge_ifp; 1671192783Sgonzo int cons, prog, packet_len, i; 1672188808Sgonzo struct arge_desc *cur_rx; 1673188808Sgonzo struct mbuf *m; 1674198667Sgonzo int rx_npkts = 0; 1675188808Sgonzo 1676188808Sgonzo ARGE_LOCK_ASSERT(sc); 1677188808Sgonzo 1678188808Sgonzo cons = sc->arge_cdata.arge_rx_cons; 1679188808Sgonzo 1680188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag, 1681188808Sgonzo sc->arge_cdata.arge_rx_ring_map, 1682188808Sgonzo BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1683188808Sgonzo 1684188808Sgonzo for (prog = 0; prog < ARGE_RX_RING_COUNT; 1685188808Sgonzo ARGE_INC(cons, ARGE_RX_RING_COUNT)) { 1686188808Sgonzo cur_rx = &sc->arge_rdata.arge_rx_ring[cons]; 1687188808Sgonzo rxd = &sc->arge_cdata.arge_rxdesc[cons]; 1688188808Sgonzo m = rxd->rx_m; 1689188808Sgonzo 1690188808Sgonzo if ((cur_rx->packet_ctrl & ARGE_DESC_EMPTY) != 0) 1691188808Sgonzo break; 1692188808Sgonzo 1693188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD); 1694188808Sgonzo 1695188808Sgonzo prog++; 1696188808Sgonzo 1697188808Sgonzo packet_len = ARGE_DMASIZE(cur_rx->packet_ctrl); 1698188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap, 1699195434Sgonzo BUS_DMASYNC_POSTREAD); 1700188808Sgonzo m = rxd->rx_m; 1701188808Sgonzo 1702188808Sgonzo arge_fixup_rx(m); 1703188808Sgonzo m->m_pkthdr.rcvif = ifp; 1704188808Sgonzo /* Skip 4 bytes of CRC */ 1705188808Sgonzo m->m_pkthdr.len = m->m_len = packet_len - ETHER_CRC_LEN; 1706188808Sgonzo ifp->if_ipackets++; 1707198667Sgonzo rx_npkts++; 1708188808Sgonzo 1709188808Sgonzo ARGE_UNLOCK(sc); 1710188808Sgonzo (*ifp->if_input)(ifp, m); 1711188808Sgonzo ARGE_LOCK(sc); 1712192783Sgonzo cur_rx->packet_addr = 0; 1713192783Sgonzo } 1714188808Sgonzo 1715192783Sgonzo if (prog > 0) { 1716192783Sgonzo 1717192783Sgonzo i = sc->arge_cdata.arge_rx_cons; 1718192783Sgonzo for (; prog > 0 ; prog--) { 1719192783Sgonzo if (arge_newbuf(sc, i) != 0) { 1720192783Sgonzo device_printf(sc->arge_dev, 1721192783Sgonzo "Failed to allocate buffer\n"); 1722192783Sgonzo break; 1723192783Sgonzo } 1724192783Sgonzo ARGE_INC(i, ARGE_RX_RING_COUNT); 1725188808Sgonzo } 1726188808Sgonzo 1727188808Sgonzo bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag, 1728188808Sgonzo sc->arge_cdata.arge_rx_ring_map, 1729195434Sgonzo BUS_DMASYNC_PREWRITE); 1730188808Sgonzo 1731188808Sgonzo sc->arge_cdata.arge_rx_cons = cons; 1732188808Sgonzo } 1733198667Sgonzo 1734198667Sgonzo return (rx_npkts); 1735188808Sgonzo} 1736188808Sgonzo 1737188808Sgonzostatic int 1738188808Sgonzoarge_intr_filter(void *arg) 1739188808Sgonzo{ 1740188808Sgonzo struct arge_softc *sc = arg; 1741188808Sgonzo uint32_t status, ints; 1742188808Sgonzo 1743188808Sgonzo status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS); 1744188808Sgonzo ints = ARGE_READ(sc, AR71XX_DMA_INTR); 1745188808Sgonzo 1746220354Sadrian ARGEDEBUG(sc, ARGE_DBG_INTR, "int mask(filter) = %b\n", ints, 1747188808Sgonzo "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD" 1748188808Sgonzo "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT"); 1749220354Sadrian ARGEDEBUG(sc, ARGE_DBG_INTR, "status(filter) = %b\n", status, 1750188808Sgonzo "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD" 1751188808Sgonzo "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT"); 1752188808Sgonzo 1753188808Sgonzo if (status & DMA_INTR_ALL) { 1754191644Sgonzo sc->arge_intr_status |= status; 1755192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_INTR, 0); 1756188808Sgonzo return (FILTER_SCHEDULE_THREAD); 1757192783Sgonzo } 1758188808Sgonzo 1759188808Sgonzo sc->arge_intr_status = 0; 1760188808Sgonzo return (FILTER_STRAY); 1761188808Sgonzo} 1762188808Sgonzo 1763188808Sgonzostatic void 1764188808Sgonzoarge_intr(void *arg) 1765188808Sgonzo{ 1766188808Sgonzo struct arge_softc *sc = arg; 1767188808Sgonzo uint32_t status; 1768188808Sgonzo 1769192783Sgonzo status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS); 1770192783Sgonzo status |= sc->arge_intr_status; 1771188808Sgonzo 1772220354Sadrian ARGEDEBUG(sc, ARGE_DBG_INTR, "int status(intr) = %b\n", status, 1773188808Sgonzo "\20\10\7RX_OVERFLOW\5RX_PKT_RCVD" 1774188808Sgonzo "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT"); 1775188808Sgonzo 1776188808Sgonzo /* 1777188808Sgonzo * Is it our interrupt at all? 1778188808Sgonzo */ 1779188808Sgonzo if (status == 0) 1780188808Sgonzo return; 1781188808Sgonzo 1782188808Sgonzo if (status & DMA_INTR_RX_BUS_ERROR) { 1783188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_BUS_ERROR); 1784188808Sgonzo device_printf(sc->arge_dev, "RX bus error"); 1785188808Sgonzo return; 1786188808Sgonzo } 1787188808Sgonzo 1788188808Sgonzo if (status & DMA_INTR_TX_BUS_ERROR) { 1789188808Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_BUS_ERROR); 1790188808Sgonzo device_printf(sc->arge_dev, "TX bus error"); 1791188808Sgonzo return; 1792188808Sgonzo } 1793188808Sgonzo 1794192783Sgonzo ARGE_LOCK(sc); 1795188808Sgonzo 1796192783Sgonzo if (status & DMA_INTR_RX_PKT_RCVD) 1797192783Sgonzo arge_rx_locked(sc); 1798188808Sgonzo 1799192783Sgonzo /* 1800192783Sgonzo * RX overrun disables the receiver. 1801192783Sgonzo * Clear indication and re-enable rx. 1802192783Sgonzo */ 1803192783Sgonzo if ( status & DMA_INTR_RX_OVERFLOW) { 1804192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_OVERFLOW); 1805192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN); 1806192783Sgonzo } 1807188808Sgonzo 1808192783Sgonzo if (status & DMA_INTR_TX_PKT_SENT) 1809192783Sgonzo arge_tx_locked(sc); 1810192783Sgonzo /* 1811192783Sgonzo * Underrun turns off TX. Clear underrun indication. 1812192783Sgonzo * If there's anything left in the ring, reactivate the tx. 1813192783Sgonzo */ 1814192569Sdwhite if (status & DMA_INTR_TX_UNDERRUN) { 1815192569Sdwhite ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_UNDERRUN); 1816219590Sadrian if (sc->arge_cdata.arge_tx_cnt > 0 ) { 1817192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 1818192783Sgonzo DMA_TX_CONTROL_EN); 1819192783Sgonzo } 1820192569Sdwhite } 1821192569Sdwhite 1822192946Sgonzo /* 1823192946Sgonzo * We handled all bits, clear status 1824192946Sgonzo */ 1825192946Sgonzo sc->arge_intr_status = 0; 1826188808Sgonzo ARGE_UNLOCK(sc); 1827192783Sgonzo /* 1828192783Sgonzo * re-enable all interrupts 1829192783Sgonzo */ 1830192783Sgonzo ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL); 1831188808Sgonzo} 1832188808Sgonzo 1833192783Sgonzo 1834188808Sgonzostatic void 1835188808Sgonzoarge_tick(void *xsc) 1836188808Sgonzo{ 1837188808Sgonzo struct arge_softc *sc = xsc; 1838188808Sgonzo struct mii_data *mii; 1839188808Sgonzo 1840188808Sgonzo ARGE_LOCK_ASSERT(sc); 1841188808Sgonzo 1842199234Sgonzo if (sc->arge_miibus) { 1843199234Sgonzo mii = device_get_softc(sc->arge_miibus); 1844199234Sgonzo mii_tick(mii); 1845199234Sgonzo callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc); 1846199234Sgonzo } 1847188808Sgonzo} 1848199234Sgonzo 1849199234Sgonzoint 1850199234Sgonzoarge_multiphy_mediachange(struct ifnet *ifp) 1851199234Sgonzo{ 1852199234Sgonzo struct arge_softc *sc = ifp->if_softc; 1853199234Sgonzo struct ifmedia *ifm = &sc->arge_ifmedia; 1854199234Sgonzo struct ifmedia_entry *ife = ifm->ifm_cur; 1855199234Sgonzo 1856199234Sgonzo if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1857199234Sgonzo return (EINVAL); 1858199234Sgonzo 1859199234Sgonzo if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1860199234Sgonzo device_printf(sc->arge_dev, 1861199234Sgonzo "AUTO is not supported for multiphy MAC"); 1862199234Sgonzo return (EINVAL); 1863199234Sgonzo } 1864199234Sgonzo 1865199234Sgonzo /* 1866199234Sgonzo * Ignore everything 1867199234Sgonzo */ 1868199234Sgonzo return (0); 1869199234Sgonzo} 1870199234Sgonzo 1871199234Sgonzovoid 1872199234Sgonzoarge_multiphy_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1873199234Sgonzo{ 1874199234Sgonzo struct arge_softc *sc = ifp->if_softc; 1875199234Sgonzo 1876199234Sgonzo ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 1877199234Sgonzo ifmr->ifm_active = IFM_ETHER | sc->arge_media_type | 1878199234Sgonzo sc->arge_duplex_mode; 1879199234Sgonzo} 1880199234Sgonzo 1881