ar71xx_machdep.c revision 192132 
1/*-
2 * Copyright (c) 2009 Oleksandr Tymoshenko
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD$");
29
30#include <sys/param.h>
31#include <machine/cpuregs.h>
32
33#include <mips/sentry5/s5reg.h>
34
35#include "opt_ddb.h"
36
37#include <sys/param.h>
38#include <sys/conf.h>
39#include <sys/kernel.h>
40#include <sys/systm.h>
41#include <sys/bus.h>
42#include <sys/cons.h>
43#include <sys/kdb.h>
44
45#include <vm/vm.h>
46#include <vm/vm_page.h>
47
48#include <machine/clock.h>
49#include <machine/cpu.h>
50#include <machine/hwfunc.h>
51#include <machine/md_var.h>
52#include <machine/trap.h>
53#include <machine/vmparam.h>
54
55#include <mips/atheros/ar71xxreg.h>
56
57extern int *edata;
58extern int *end;
59
60void
61platform_halt(void)
62{
63
64}
65
66void
67platform_identify(void)
68{
69
70}
71
72void
73platform_reset(void)
74{
75	uint32_t reg = ATH_READ_REG(AR71XX_RST_RESET);
76
77	ATH_WRITE_REG(AR71XX_RST_RESET, reg | RST_RESET_FULL_CHIP);
78	/* Wait for reset */
79	while(1)
80		;
81}
82
83void
84platform_trap_enter(void)
85{
86
87}
88
89void
90platform_trap_exit(void)
91{
92
93}
94
95void
96platform_start(__register_t a0 __unused, __register_t a1 __unused,
97    __register_t a2 __unused, __register_t a3 __unused)
98{
99	vm_offset_t kernend;
100	uint64_t platform_counter_freq, freq;
101	uint32_t reg, div, pll_config;
102
103	/* clear the BSS and SBSS segments */
104	kernend = round_page((vm_offset_t)&end);
105	memset(&edata, 0, kernend - (vm_offset_t)(&edata));
106
107	/* TODO: Get available memory from RedBoot. Is it possible? */
108	realmem = btoc(64*1024*1024);
109	/* phys_avail regions are in bytes */
110	phys_avail[0] = MIPS_KSEG0_TO_PHYS((vm_offset_t)&end);
111	phys_avail[1] = ctob(realmem);
112
113	physmem = realmem;
114
115	/*
116	 * ns8250 uart code uses DELAY so ticker should be inititalized
117	 * before cninit. And tick_init_params refers to hz, so * init_param1
118	 * should be called first.
119	 */
120	init_param1();
121	pll_config = ATH_READ_REG(AR71XX_PLL_CPU_CONFIG);
122	div = ((pll_config >> PLL_FB_SHIFT) & PLL_FB_MASK) + 1;
123	freq = div * AR71XX_BASE_FREQ;
124	div = ((pll_config >> PLL_CPU_DIV_SEL_SHIFT) & PLL_CPU_DIV_SEL_MASK)
125	    + 1;
126	platform_counter_freq = freq / div;
127	mips_timer_init_params(platform_counter_freq, 0);
128	cninit();
129
130	printf("platform frequency: %lld\n", platform_counter_freq);
131	printf("arguments: \n");
132	printf("  a0 = %08x\n", a0);
133	printf("  a1 = %08x\n", a1);
134	printf("  a2 = %08x\n", a2);
135	printf("  a3 = %08x\n", a3);
136
137	init_param2(physmem);
138	mips_cpu_init();
139	pmap_bootstrap();
140	mips_proc0_init();
141	mutex_init();
142
143	/*
144	 * Reset USB devices
145	 */
146	reg = ATH_READ_REG(AR71XX_RST_RESET);
147	reg |=
148	    RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY;
149	ATH_WRITE_REG(AR71XX_RST_RESET, reg);
150	DELAY(1000);
151	reg &=
152	    ~(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY);
153	ATH_WRITE_REG(AR71XX_RST_RESET, reg);
154
155	ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG,
156	    USB_CTRL_CONFIG_OHCI_DES_SWAP | USB_CTRL_CONFIG_OHCI_BUF_SWAP |
157	    USB_CTRL_CONFIG_EHCI_DES_SWAP | USB_CTRL_CONFIG_EHCI_BUF_SWAP);
158
159	ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
160	    (32 << USB_CTRL_FLADJ_HOST_SHIFT) | (3 << USB_CTRL_FLADJ_A5_SHIFT));
161	DELAY(1000);
162
163#ifdef DDB
164	kdb_init();
165#endif
166}
167