ar71xx_gpio.c revision 253510 
1/*-
2 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
3 * Copyright (c) 2009, Luiz Otavio O Souza.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice unmodified, this list of conditions, and the following
11 *    disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * GPIO driver for AR71xx
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_gpio.c 253510 2013-07-21 03:55:18Z adrian $");
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/bus.h>
39
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <sys/rman.h>
43#include <sys/lock.h>
44#include <sys/mutex.h>
45#include <sys/gpio.h>
46
47#include <machine/bus.h>
48#include <machine/resource.h>
49#include <mips/atheros/ar71xxreg.h>
50#include <mips/atheros/ar71xx_setup.h>
51#include <mips/atheros/ar71xx_gpiovar.h>
52#include <mips/atheros/ar933xreg.h>
53#include <mips/atheros/ar934xreg.h>
54
55#include "gpio_if.h"
56
57#define	DEFAULT_CAPS	(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
58
59/*
60 * Helpers
61 */
62static void ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc,
63    uint32_t mask);
64static void ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc,
65    uint32_t mask);
66static void ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc,
67    struct gpio_pin *pin, uint32_t flags);
68
69/*
70 * Driver stuff
71 */
72static int ar71xx_gpio_probe(device_t dev);
73static int ar71xx_gpio_attach(device_t dev);
74static int ar71xx_gpio_detach(device_t dev);
75static int ar71xx_gpio_filter(void *arg);
76static void ar71xx_gpio_intr(void *arg);
77
78/*
79 * GPIO interface
80 */
81static int ar71xx_gpio_pin_max(device_t dev, int *maxpin);
82static int ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps);
83static int ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t
84    *flags);
85static int ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name);
86static int ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags);
87static int ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
88static int ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
89static int ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin);
90
91static void
92ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc, uint32_t mask)
93{
94	if (ar71xx_soc == AR71XX_SOC_AR9341 ||
95	    ar71xx_soc == AR71XX_SOC_AR9342 ||
96	    ar71xx_soc == AR71XX_SOC_AR9344)
97		GPIO_SET_BITS(sc, AR934X_GPIO_REG_FUNC, mask);
98	else
99		GPIO_SET_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
100}
101
102static void
103ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc, uint32_t mask)
104{
105	if (ar71xx_soc == AR71XX_SOC_AR9341 ||
106	    ar71xx_soc == AR71XX_SOC_AR9342 ||
107	    ar71xx_soc == AR71XX_SOC_AR9344)
108		GPIO_CLEAR_BITS(sc, AR934X_GPIO_REG_FUNC, mask);
109	else
110		GPIO_CLEAR_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
111}
112
113static void
114ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc, struct gpio_pin *pin,
115    unsigned int flags)
116{
117	uint32_t mask;
118
119	mask = 1 << pin->gp_pin;
120
121	/*
122	 * Manage input/output
123	 */
124	if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
125		pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
126		if (flags & GPIO_PIN_OUTPUT) {
127			pin->gp_flags |= GPIO_PIN_OUTPUT;
128			GPIO_SET_BITS(sc, AR71XX_GPIO_OE, mask);
129		}
130		else {
131			pin->gp_flags |= GPIO_PIN_INPUT;
132			GPIO_CLEAR_BITS(sc, AR71XX_GPIO_OE, mask);
133		}
134	}
135}
136
137static int
138ar71xx_gpio_pin_max(device_t dev, int *maxpin)
139{
140
141	switch (ar71xx_soc) {
142		case AR71XX_SOC_AR9130:
143		case AR71XX_SOC_AR9132:
144			*maxpin = AR91XX_GPIO_PINS - 1;
145			break;
146		case AR71XX_SOC_AR7240:
147		case AR71XX_SOC_AR7241:
148		case AR71XX_SOC_AR7242:
149			*maxpin = AR724X_GPIO_PINS - 1;
150			break;
151		case AR71XX_SOC_AR9330:
152		case AR71XX_SOC_AR9331:
153			*maxpin = AR933X_GPIO_COUNT - 1;
154			break;
155		case AR71XX_SOC_AR9341:
156		case AR71XX_SOC_AR9342:
157		case AR71XX_SOC_AR9344:
158			*maxpin = AR934X_GPIO_COUNT - 1;
159		default:
160			*maxpin = AR71XX_GPIO_PINS - 1;
161	}
162	return (0);
163}
164
165static int
166ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
167{
168	struct ar71xx_gpio_softc *sc = device_get_softc(dev);
169	int i;
170
171	for (i = 0; i < sc->gpio_npins; i++) {
172		if (sc->gpio_pins[i].gp_pin == pin)
173			break;
174	}
175
176	if (i >= sc->gpio_npins)
177		return (EINVAL);
178
179	GPIO_LOCK(sc);
180	*caps = sc->gpio_pins[i].gp_caps;
181	GPIO_UNLOCK(sc);
182
183	return (0);
184}
185
186static int
187ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
188{
189	struct ar71xx_gpio_softc *sc = device_get_softc(dev);
190	int i;
191
192	for (i = 0; i < sc->gpio_npins; i++) {
193		if (sc->gpio_pins[i].gp_pin == pin)
194			break;
195	}
196
197	if (i >= sc->gpio_npins)
198		return (EINVAL);
199
200	GPIO_LOCK(sc);
201	*flags = sc->gpio_pins[i].gp_flags;
202	GPIO_UNLOCK(sc);
203
204	return (0);
205}
206
207static int
208ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
209{
210	struct ar71xx_gpio_softc *sc = device_get_softc(dev);
211	int i;
212
213	for (i = 0; i < sc->gpio_npins; i++) {
214		if (sc->gpio_pins[i].gp_pin == pin)
215			break;
216	}
217
218	if (i >= sc->gpio_npins)
219		return (EINVAL);
220
221	GPIO_LOCK(sc);
222	memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
223	GPIO_UNLOCK(sc);
224
225	return (0);
226}
227
228static int
229ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
230{
231	int i;
232	struct ar71xx_gpio_softc *sc = device_get_softc(dev);
233
234	for (i = 0; i < sc->gpio_npins; i++) {
235		if (sc->gpio_pins[i].gp_pin == pin)
236			break;
237	}
238
239	if (i >= sc->gpio_npins)
240		return (EINVAL);
241
242	/* Check for unwanted flags. */
243	if ((flags & sc->gpio_pins[i].gp_caps) != flags)
244		return (EINVAL);
245
246	/* Can't mix input/output together */
247	if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) ==
248	    (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT))
249		return (EINVAL);
250
251	ar71xx_gpio_pin_configure(sc, &sc->gpio_pins[i], flags);
252	return (0);
253}
254
255static int
256ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
257{
258	struct ar71xx_gpio_softc *sc = device_get_softc(dev);
259	int i;
260
261	for (i = 0; i < sc->gpio_npins; i++) {
262		if (sc->gpio_pins[i].gp_pin == pin)
263			break;
264	}
265
266	if (i >= sc->gpio_npins)
267		return (EINVAL);
268
269	if (value)
270		GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
271	else
272		GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
273
274	return (0);
275}
276
277static int
278ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
279{
280	struct ar71xx_gpio_softc *sc = device_get_softc(dev);
281	int i;
282
283	for (i = 0; i < sc->gpio_npins; i++) {
284		if (sc->gpio_pins[i].gp_pin == pin)
285			break;
286	}
287
288	if (i >= sc->gpio_npins)
289		return (EINVAL);
290
291	*val = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0;
292
293	return (0);
294}
295
296static int
297ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin)
298{
299	int res, i;
300	struct ar71xx_gpio_softc *sc = device_get_softc(dev);
301
302	for (i = 0; i < sc->gpio_npins; i++) {
303		if (sc->gpio_pins[i].gp_pin == pin)
304			break;
305	}
306
307	if (i >= sc->gpio_npins)
308		return (EINVAL);
309
310	res = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0;
311	if (res)
312		GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
313	else
314		GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
315
316	return (0);
317}
318
319static int
320ar71xx_gpio_filter(void *arg)
321{
322
323	/* TODO: something useful */
324	return (FILTER_STRAY);
325}
326
327
328
329static void
330ar71xx_gpio_intr(void *arg)
331{
332	struct ar71xx_gpio_softc *sc = arg;
333	GPIO_LOCK(sc);
334	/* TODO: something useful */
335	GPIO_UNLOCK(sc);
336}
337
338static int
339ar71xx_gpio_probe(device_t dev)
340{
341
342	device_set_desc(dev, "Atheros AR71XX GPIO driver");
343	return (0);
344}
345
346static int
347ar71xx_gpio_attach(device_t dev)
348{
349	struct ar71xx_gpio_softc *sc = device_get_softc(dev);
350	int error = 0;
351	int i, j, maxpin;
352	int mask, pinon;
353	int old = 0;
354
355	KASSERT((device_get_unit(dev) == 0),
356	    ("ar71xx_gpio: Only one gpio module supported"));
357
358	mtx_init(&sc->gpio_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
359
360	/* Map control/status registers. */
361	sc->gpio_mem_rid = 0;
362	sc->gpio_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
363	    &sc->gpio_mem_rid, RF_ACTIVE);
364
365	if (sc->gpio_mem_res == NULL) {
366		device_printf(dev, "couldn't map memory\n");
367		error = ENXIO;
368		ar71xx_gpio_detach(dev);
369		return(error);
370	}
371
372	if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
373	    &sc->gpio_irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
374		device_printf(dev, "unable to allocate IRQ resource\n");
375		return (ENXIO);
376	}
377
378	if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC,
379	    ar71xx_gpio_filter, ar71xx_gpio_intr, sc, &sc->gpio_ih))) {
380		device_printf(dev,
381		    "WARNING: unable to register interrupt handler\n");
382		return (ENXIO);
383	}
384
385	sc->dev = dev;
386
387	/* Enable function bits that are required */
388	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
389	    "function_set", &mask) == 0) {
390		device_printf(dev, "function_set: 0x%x\n", mask);
391		ar71xx_gpio_function_enable(sc, mask);
392		old = 1;
393	}
394	/* Disable function bits that are required */
395	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
396	    "function_clear", &mask) == 0) {
397		device_printf(dev, "function_clear: 0x%x\n", mask);
398		ar71xx_gpio_function_disable(sc, mask);
399		old = 1;
400	}
401	/* Handle previous behaviour */
402	if (old == 0) {
403		ar71xx_gpio_function_enable(sc, GPIO_FUNC_SPI_CS1_EN);
404		ar71xx_gpio_function_enable(sc, GPIO_FUNC_SPI_CS2_EN);
405	}
406
407	/* Configure all pins as input */
408	/* disable interrupts for all pins */
409	GPIO_WRITE(sc, AR71XX_GPIO_INT_MASK, 0);
410
411	/* Initialise all pins specified in the mask, up to the pin count */
412	(void) ar71xx_gpio_pin_max(dev, &maxpin);
413	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
414	    "pinmask", &mask) != 0)
415		mask = 0;
416	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
417	    "pinon", &pinon) != 0)
418		pinon = 0;
419	device_printf(dev, "gpio pinmask=0x%x\n", mask);
420	for (i = 0, j = 0; j < maxpin; j++) {
421		if ((mask & (1 << j)) == 0)
422			continue;
423		snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
424		    "pin %d", j);
425		sc->gpio_pins[i].gp_pin = j;
426		sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
427		sc->gpio_pins[i].gp_flags = 0;
428		ar71xx_gpio_pin_configure(sc, &sc->gpio_pins[i], DEFAULT_CAPS);
429		i++;
430	}
431	sc->gpio_npins = i;
432	for (i = 0; i < sc->gpio_npins; i++) {
433		j = sc->gpio_pins[i].gp_pin;
434		if ((pinon & (1 << j)) != 0)
435			ar71xx_gpio_pin_set(dev, j, 1);
436	}
437	device_add_child(dev, "gpioc", device_get_unit(dev));
438	device_add_child(dev, "gpiobus", device_get_unit(dev));
439	return (bus_generic_attach(dev));
440}
441
442static int
443ar71xx_gpio_detach(device_t dev)
444{
445	struct ar71xx_gpio_softc *sc = device_get_softc(dev);
446
447	KASSERT(mtx_initialized(&sc->gpio_mtx), ("gpio mutex not initialized"));
448
449	ar71xx_gpio_function_disable(sc, GPIO_FUNC_SPI_CS1_EN);
450	ar71xx_gpio_function_disable(sc, GPIO_FUNC_SPI_CS2_EN);
451	bus_generic_detach(dev);
452
453	if (sc->gpio_mem_res)
454		bus_release_resource(dev, SYS_RES_MEMORY, sc->gpio_mem_rid,
455		    sc->gpio_mem_res);
456
457	mtx_destroy(&sc->gpio_mtx);
458
459	return(0);
460}
461
462static device_method_t ar71xx_gpio_methods[] = {
463	DEVMETHOD(device_probe, ar71xx_gpio_probe),
464	DEVMETHOD(device_attach, ar71xx_gpio_attach),
465	DEVMETHOD(device_detach, ar71xx_gpio_detach),
466
467	/* GPIO protocol */
468	DEVMETHOD(gpio_pin_max, ar71xx_gpio_pin_max),
469	DEVMETHOD(gpio_pin_getname, ar71xx_gpio_pin_getname),
470	DEVMETHOD(gpio_pin_getflags, ar71xx_gpio_pin_getflags),
471	DEVMETHOD(gpio_pin_getcaps, ar71xx_gpio_pin_getcaps),
472	DEVMETHOD(gpio_pin_setflags, ar71xx_gpio_pin_setflags),
473	DEVMETHOD(gpio_pin_get, ar71xx_gpio_pin_get),
474	DEVMETHOD(gpio_pin_set, ar71xx_gpio_pin_set),
475	DEVMETHOD(gpio_pin_toggle, ar71xx_gpio_pin_toggle),
476	{0, 0},
477};
478
479static driver_t ar71xx_gpio_driver = {
480	"gpio",
481	ar71xx_gpio_methods,
482	sizeof(struct ar71xx_gpio_softc),
483};
484static devclass_t ar71xx_gpio_devclass;
485
486DRIVER_MODULE(ar71xx_gpio, apb, ar71xx_gpio_driver, ar71xx_gpio_devclass, 0, 0);
487