ar71xx_gpio.c revision 250165 
1/*-
2 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
3 * Copyright (c) 2009, Luiz Otavio O Souza.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice unmodified, this list of conditions, and the following
11 *    disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * GPIO driver for AR71xx
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_gpio.c 250165 2013-05-02 00:40:45Z adrian $");
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/bus.h>
39
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <sys/rman.h>
43#include <sys/lock.h>
44#include <sys/mutex.h>
45#include <sys/gpio.h>
46
47#include <machine/bus.h>
48#include <machine/resource.h>
49#include <mips/atheros/ar71xxreg.h>
50#include <mips/atheros/ar71xx_setup.h>
51#include <mips/atheros/ar71xx_gpiovar.h>
52#include <mips/atheros/ar933xreg.h>
53
54#include "gpio_if.h"
55
56#define	DEFAULT_CAPS	(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
57
58/*
59 * Helpers
60 */
61static void ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc,
62    uint32_t mask);
63static void ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc,
64    uint32_t mask);
65static void ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc,
66    struct gpio_pin *pin, uint32_t flags);
67
68/*
69 * Driver stuff
70 */
71static int ar71xx_gpio_probe(device_t dev);
72static int ar71xx_gpio_attach(device_t dev);
73static int ar71xx_gpio_detach(device_t dev);
74static int ar71xx_gpio_filter(void *arg);
75static void ar71xx_gpio_intr(void *arg);
76
77/*
78 * GPIO interface
79 */
80static int ar71xx_gpio_pin_max(device_t dev, int *maxpin);
81static int ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps);
82static int ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t
83    *flags);
84static int ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name);
85static int ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags);
86static int ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
87static int ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
88static int ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin);
89
90static void
91ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc, uint32_t mask)
92{
93	GPIO_SET_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
94}
95
96static void
97ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc, uint32_t mask)
98{
99	GPIO_CLEAR_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
100}
101
102static void
103ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc, struct gpio_pin *pin,
104    unsigned int flags)
105{
106	uint32_t mask;
107
108	mask = 1 << pin->gp_pin;
109
110	/*
111	 * Manage input/output
112	 */
113	if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
114		pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
115		if (flags & GPIO_PIN_OUTPUT) {
116			pin->gp_flags |= GPIO_PIN_OUTPUT;
117			GPIO_SET_BITS(sc, AR71XX_GPIO_OE, mask);
118		}
119		else {
120			pin->gp_flags |= GPIO_PIN_INPUT;
121			GPIO_CLEAR_BITS(sc, AR71XX_GPIO_OE, mask);
122		}
123	}
124}
125
126static int
127ar71xx_gpio_pin_max(device_t dev, int *maxpin)
128{
129
130	switch (ar71xx_soc) {
131		case AR71XX_SOC_AR9130:
132		case AR71XX_SOC_AR9132:
133			*maxpin = AR91XX_GPIO_PINS - 1;
134			break;
135		case AR71XX_SOC_AR7240:
136		case AR71XX_SOC_AR7241:
137		case AR71XX_SOC_AR7242:
138			*maxpin = AR724X_GPIO_PINS - 1;
139			break;
140		case AR71XX_SOC_AR9330:
141		case AR71XX_SOC_AR9331:
142			*maxpin = AR933X_GPIO_COUNT - 1;
143			break;
144		default:
145			*maxpin = AR71XX_GPIO_PINS - 1;
146	}
147	return (0);
148}
149
150static int
151ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
152{
153	struct ar71xx_gpio_softc *sc = device_get_softc(dev);
154	int i;
155
156	for (i = 0; i < sc->gpio_npins; i++) {
157		if (sc->gpio_pins[i].gp_pin == pin)
158			break;
159	}
160
161	if (i >= sc->gpio_npins)
162		return (EINVAL);
163
164	GPIO_LOCK(sc);
165	*caps = sc->gpio_pins[i].gp_caps;
166	GPIO_UNLOCK(sc);
167
168	return (0);
169}
170
171static int
172ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
173{
174	struct ar71xx_gpio_softc *sc = device_get_softc(dev);
175	int i;
176
177	for (i = 0; i < sc->gpio_npins; i++) {
178		if (sc->gpio_pins[i].gp_pin == pin)
179			break;
180	}
181
182	if (i >= sc->gpio_npins)
183		return (EINVAL);
184
185	GPIO_LOCK(sc);
186	*flags = sc->gpio_pins[i].gp_flags;
187	GPIO_UNLOCK(sc);
188
189	return (0);
190}
191
192static int
193ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
194{
195	struct ar71xx_gpio_softc *sc = device_get_softc(dev);
196	int i;
197
198	for (i = 0; i < sc->gpio_npins; i++) {
199		if (sc->gpio_pins[i].gp_pin == pin)
200			break;
201	}
202
203	if (i >= sc->gpio_npins)
204		return (EINVAL);
205
206	GPIO_LOCK(sc);
207	memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
208	GPIO_UNLOCK(sc);
209
210	return (0);
211}
212
213static int
214ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
215{
216	int i;
217	struct ar71xx_gpio_softc *sc = device_get_softc(dev);
218
219	for (i = 0; i < sc->gpio_npins; i++) {
220		if (sc->gpio_pins[i].gp_pin == pin)
221			break;
222	}
223
224	if (i >= sc->gpio_npins)
225		return (EINVAL);
226
227	/* Check for unwanted flags. */
228	if ((flags & sc->gpio_pins[i].gp_caps) != flags)
229		return (EINVAL);
230
231	/* Can't mix input/output together */
232	if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) ==
233	    (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT))
234		return (EINVAL);
235
236	ar71xx_gpio_pin_configure(sc, &sc->gpio_pins[i], flags);
237	return (0);
238}
239
240static int
241ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
242{
243	struct ar71xx_gpio_softc *sc = device_get_softc(dev);
244	int i;
245
246	for (i = 0; i < sc->gpio_npins; i++) {
247		if (sc->gpio_pins[i].gp_pin == pin)
248			break;
249	}
250
251	if (i >= sc->gpio_npins)
252		return (EINVAL);
253
254	if (value)
255		GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
256	else
257		GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
258
259	return (0);
260}
261
262static int
263ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
264{
265	struct ar71xx_gpio_softc *sc = device_get_softc(dev);
266	int i;
267
268	for (i = 0; i < sc->gpio_npins; i++) {
269		if (sc->gpio_pins[i].gp_pin == pin)
270			break;
271	}
272
273	if (i >= sc->gpio_npins)
274		return (EINVAL);
275
276	*val = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0;
277
278	return (0);
279}
280
281static int
282ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin)
283{
284	int res, i;
285	struct ar71xx_gpio_softc *sc = device_get_softc(dev);
286
287	for (i = 0; i < sc->gpio_npins; i++) {
288		if (sc->gpio_pins[i].gp_pin == pin)
289			break;
290	}
291
292	if (i >= sc->gpio_npins)
293		return (EINVAL);
294
295	res = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0;
296	if (res)
297		GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
298	else
299		GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
300
301	return (0);
302}
303
304static int
305ar71xx_gpio_filter(void *arg)
306{
307
308	/* TODO: something useful */
309	return (FILTER_STRAY);
310}
311
312
313
314static void
315ar71xx_gpio_intr(void *arg)
316{
317	struct ar71xx_gpio_softc *sc = arg;
318	GPIO_LOCK(sc);
319	/* TODO: something useful */
320	GPIO_UNLOCK(sc);
321}
322
323static int
324ar71xx_gpio_probe(device_t dev)
325{
326
327	device_set_desc(dev, "Atheros AR71XX GPIO driver");
328	return (0);
329}
330
331static int
332ar71xx_gpio_attach(device_t dev)
333{
334	struct ar71xx_gpio_softc *sc = device_get_softc(dev);
335	int error = 0;
336	int i, j, maxpin;
337	int mask, pinon;
338	int old = 0;
339
340	KASSERT((device_get_unit(dev) == 0),
341	    ("ar71xx_gpio: Only one gpio module supported"));
342
343	mtx_init(&sc->gpio_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
344
345	/* Map control/status registers. */
346	sc->gpio_mem_rid = 0;
347	sc->gpio_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
348	    &sc->gpio_mem_rid, RF_ACTIVE);
349
350	if (sc->gpio_mem_res == NULL) {
351		device_printf(dev, "couldn't map memory\n");
352		error = ENXIO;
353		ar71xx_gpio_detach(dev);
354		return(error);
355	}
356
357	if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
358	    &sc->gpio_irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
359		device_printf(dev, "unable to allocate IRQ resource\n");
360		return (ENXIO);
361	}
362
363	if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC,
364	    ar71xx_gpio_filter, ar71xx_gpio_intr, sc, &sc->gpio_ih))) {
365		device_printf(dev,
366		    "WARNING: unable to register interrupt handler\n");
367		return (ENXIO);
368	}
369
370	sc->dev = dev;
371
372	/* Enable function bits that are required */
373	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
374	    "function_set", &mask) == 0) {
375		device_printf(dev, "function_set: 0x%x\n", mask);
376		ar71xx_gpio_function_enable(sc, mask);
377		old = 1;
378	}
379	/* Disable function bits that are required */
380	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
381	    "function_clear", &mask) == 0) {
382		device_printf(dev, "function_clear: 0x%x\n", mask);
383		ar71xx_gpio_function_disable(sc, mask);
384		old = 1;
385	}
386	/* Handle previous behaviour */
387	if (old == 0) {
388		ar71xx_gpio_function_enable(sc, GPIO_FUNC_SPI_CS1_EN);
389		ar71xx_gpio_function_enable(sc, GPIO_FUNC_SPI_CS2_EN);
390	}
391
392	/* Configure all pins as input */
393	/* disable interrupts for all pins */
394	GPIO_WRITE(sc, AR71XX_GPIO_INT_MASK, 0);
395
396	/* Initialise all pins specified in the mask, up to the pin count */
397	(void) ar71xx_gpio_pin_max(dev, &maxpin);
398	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
399	    "pinmask", &mask) != 0)
400		mask = 0;
401	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
402	    "pinon", &pinon) != 0)
403		pinon = 0;
404	device_printf(dev, "gpio pinmask=0x%x\n", mask);
405	for (i = 0, j = 0; j < maxpin; j++) {
406		if ((mask & (1 << j)) == 0)
407			continue;
408		snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
409		    "pin %d", j);
410		sc->gpio_pins[i].gp_pin = j;
411		sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
412		sc->gpio_pins[i].gp_flags = 0;
413		ar71xx_gpio_pin_configure(sc, &sc->gpio_pins[i], DEFAULT_CAPS);
414		i++;
415	}
416	sc->gpio_npins = i;
417	for (i = 0; i < sc->gpio_npins; i++) {
418		j = sc->gpio_pins[i].gp_pin;
419		if ((pinon & (1 << j)) != 0)
420			ar71xx_gpio_pin_set(dev, j, 1);
421	}
422	device_add_child(dev, "gpioc", device_get_unit(dev));
423	device_add_child(dev, "gpiobus", device_get_unit(dev));
424	return (bus_generic_attach(dev));
425}
426
427static int
428ar71xx_gpio_detach(device_t dev)
429{
430	struct ar71xx_gpio_softc *sc = device_get_softc(dev);
431
432	KASSERT(mtx_initialized(&sc->gpio_mtx), ("gpio mutex not initialized"));
433
434	ar71xx_gpio_function_disable(sc, GPIO_FUNC_SPI_CS1_EN);
435	ar71xx_gpio_function_disable(sc, GPIO_FUNC_SPI_CS2_EN);
436	bus_generic_detach(dev);
437
438	if (sc->gpio_mem_res)
439		bus_release_resource(dev, SYS_RES_MEMORY, sc->gpio_mem_rid,
440		    sc->gpio_mem_res);
441
442	mtx_destroy(&sc->gpio_mtx);
443
444	return(0);
445}
446
447static device_method_t ar71xx_gpio_methods[] = {
448	DEVMETHOD(device_probe, ar71xx_gpio_probe),
449	DEVMETHOD(device_attach, ar71xx_gpio_attach),
450	DEVMETHOD(device_detach, ar71xx_gpio_detach),
451
452	/* GPIO protocol */
453	DEVMETHOD(gpio_pin_max, ar71xx_gpio_pin_max),
454	DEVMETHOD(gpio_pin_getname, ar71xx_gpio_pin_getname),
455	DEVMETHOD(gpio_pin_getflags, ar71xx_gpio_pin_getflags),
456	DEVMETHOD(gpio_pin_getcaps, ar71xx_gpio_pin_getcaps),
457	DEVMETHOD(gpio_pin_setflags, ar71xx_gpio_pin_setflags),
458	DEVMETHOD(gpio_pin_get, ar71xx_gpio_pin_get),
459	DEVMETHOD(gpio_pin_set, ar71xx_gpio_pin_set),
460	DEVMETHOD(gpio_pin_toggle, ar71xx_gpio_pin_toggle),
461	{0, 0},
462};
463
464static driver_t ar71xx_gpio_driver = {
465	"gpio",
466	ar71xx_gpio_methods,
467	sizeof(struct ar71xx_gpio_softc),
468};
469static devclass_t ar71xx_gpio_devclass;
470
471DRIVER_MODULE(ar71xx_gpio, apb, ar71xx_gpio_driver, ar71xx_gpio_devclass, 0, 0);
472