ar71xx_gpio.c revision 255334
1/*- 2 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org> 3 * Copyright (c) 2009, Luiz Otavio O Souza. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * GPIO driver for AR71xx 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_gpio.c 255334 2013-09-06 23:39:56Z loos $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39 40#include <sys/kernel.h> 41#include <sys/module.h> 42#include <sys/rman.h> 43#include <sys/lock.h> 44#include <sys/mutex.h> 45#include <sys/gpio.h> 46 47#include <machine/bus.h> 48#include <machine/resource.h> 49#include <mips/atheros/ar71xxreg.h> 50#include <mips/atheros/ar71xx_setup.h> 51#include <mips/atheros/ar71xx_gpiovar.h> 52#include <mips/atheros/ar933xreg.h> 53#include <mips/atheros/ar934xreg.h> 54 55#include "gpio_if.h" 56 57#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT) 58 59/* 60 * Helpers 61 */ 62static void ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc, 63 uint32_t mask); 64static void ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc, 65 uint32_t mask); 66static void ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc, 67 struct gpio_pin *pin, uint32_t flags); 68 69/* 70 * Driver stuff 71 */ 72static int ar71xx_gpio_probe(device_t dev); 73static int ar71xx_gpio_attach(device_t dev); 74static int ar71xx_gpio_detach(device_t dev); 75static int ar71xx_gpio_filter(void *arg); 76static void ar71xx_gpio_intr(void *arg); 77 78/* 79 * GPIO interface 80 */ 81static int ar71xx_gpio_pin_max(device_t dev, int *maxpin); 82static int ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps); 83static int ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t 84 *flags); 85static int ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name); 86static int ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags); 87static int ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value); 88static int ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val); 89static int ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin); 90 91static void 92ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc, uint32_t mask) 93{ 94 if (ar71xx_soc == AR71XX_SOC_AR9341 || 95 ar71xx_soc == AR71XX_SOC_AR9342 || 96 ar71xx_soc == AR71XX_SOC_AR9344) 97 GPIO_SET_BITS(sc, AR934X_GPIO_REG_FUNC, mask); 98 else 99 GPIO_SET_BITS(sc, AR71XX_GPIO_FUNCTION, mask); 100} 101 102static void 103ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc, uint32_t mask) 104{ 105 if (ar71xx_soc == AR71XX_SOC_AR9341 || 106 ar71xx_soc == AR71XX_SOC_AR9342 || 107 ar71xx_soc == AR71XX_SOC_AR9344) 108 GPIO_CLEAR_BITS(sc, AR934X_GPIO_REG_FUNC, mask); 109 else 110 GPIO_CLEAR_BITS(sc, AR71XX_GPIO_FUNCTION, mask); 111} 112 113static void 114ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc, struct gpio_pin *pin, 115 unsigned int flags) 116{ 117 uint32_t mask; 118 119 mask = 1 << pin->gp_pin; 120 121 /* 122 * Manage input/output 123 */ 124 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { 125 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT); 126 if (flags & GPIO_PIN_OUTPUT) { 127 pin->gp_flags |= GPIO_PIN_OUTPUT; 128 GPIO_SET_BITS(sc, AR71XX_GPIO_OE, mask); 129 } 130 else { 131 pin->gp_flags |= GPIO_PIN_INPUT; 132 GPIO_CLEAR_BITS(sc, AR71XX_GPIO_OE, mask); 133 } 134 } 135} 136 137static int 138ar71xx_gpio_pin_max(device_t dev, int *maxpin) 139{ 140 141 switch (ar71xx_soc) { 142 case AR71XX_SOC_AR9130: 143 case AR71XX_SOC_AR9132: 144 *maxpin = AR91XX_GPIO_PINS - 1; 145 break; 146 case AR71XX_SOC_AR7240: 147 case AR71XX_SOC_AR7241: 148 case AR71XX_SOC_AR7242: 149 *maxpin = AR724X_GPIO_PINS - 1; 150 break; 151 case AR71XX_SOC_AR9330: 152 case AR71XX_SOC_AR9331: 153 *maxpin = AR933X_GPIO_COUNT - 1; 154 break; 155 case AR71XX_SOC_AR9341: 156 case AR71XX_SOC_AR9342: 157 case AR71XX_SOC_AR9344: 158 *maxpin = AR934X_GPIO_COUNT - 1; 159 break; 160 default: 161 *maxpin = AR71XX_GPIO_PINS - 1; 162 } 163 return (0); 164} 165 166static int 167ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 168{ 169 struct ar71xx_gpio_softc *sc = device_get_softc(dev); 170 int i; 171 172 for (i = 0; i < sc->gpio_npins; i++) { 173 if (sc->gpio_pins[i].gp_pin == pin) 174 break; 175 } 176 177 if (i >= sc->gpio_npins) 178 return (EINVAL); 179 180 GPIO_LOCK(sc); 181 *caps = sc->gpio_pins[i].gp_caps; 182 GPIO_UNLOCK(sc); 183 184 return (0); 185} 186 187static int 188ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 189{ 190 struct ar71xx_gpio_softc *sc = device_get_softc(dev); 191 int i; 192 193 for (i = 0; i < sc->gpio_npins; i++) { 194 if (sc->gpio_pins[i].gp_pin == pin) 195 break; 196 } 197 198 if (i >= sc->gpio_npins) 199 return (EINVAL); 200 201 GPIO_LOCK(sc); 202 *flags = sc->gpio_pins[i].gp_flags; 203 GPIO_UNLOCK(sc); 204 205 return (0); 206} 207 208static int 209ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 210{ 211 struct ar71xx_gpio_softc *sc = device_get_softc(dev); 212 int i; 213 214 for (i = 0; i < sc->gpio_npins; i++) { 215 if (sc->gpio_pins[i].gp_pin == pin) 216 break; 217 } 218 219 if (i >= sc->gpio_npins) 220 return (EINVAL); 221 222 GPIO_LOCK(sc); 223 memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME); 224 GPIO_UNLOCK(sc); 225 226 return (0); 227} 228 229static int 230ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 231{ 232 int i; 233 struct ar71xx_gpio_softc *sc = device_get_softc(dev); 234 235 for (i = 0; i < sc->gpio_npins; i++) { 236 if (sc->gpio_pins[i].gp_pin == pin) 237 break; 238 } 239 240 if (i >= sc->gpio_npins) 241 return (EINVAL); 242 243 /* Check for unwanted flags. */ 244 if ((flags & sc->gpio_pins[i].gp_caps) != flags) 245 return (EINVAL); 246 247 /* Can't mix input/output together */ 248 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 249 (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) 250 return (EINVAL); 251 252 ar71xx_gpio_pin_configure(sc, &sc->gpio_pins[i], flags); 253 return (0); 254} 255 256static int 257ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 258{ 259 struct ar71xx_gpio_softc *sc = device_get_softc(dev); 260 int i; 261 262 for (i = 0; i < sc->gpio_npins; i++) { 263 if (sc->gpio_pins[i].gp_pin == pin) 264 break; 265 } 266 267 if (i >= sc->gpio_npins) 268 return (EINVAL); 269 270 if (value) 271 GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin)); 272 else 273 GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin)); 274 275 return (0); 276} 277 278static int 279ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 280{ 281 struct ar71xx_gpio_softc *sc = device_get_softc(dev); 282 int i; 283 284 for (i = 0; i < sc->gpio_npins; i++) { 285 if (sc->gpio_pins[i].gp_pin == pin) 286 break; 287 } 288 289 if (i >= sc->gpio_npins) 290 return (EINVAL); 291 292 *val = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0; 293 294 return (0); 295} 296 297static int 298ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin) 299{ 300 int res, i; 301 struct ar71xx_gpio_softc *sc = device_get_softc(dev); 302 303 for (i = 0; i < sc->gpio_npins; i++) { 304 if (sc->gpio_pins[i].gp_pin == pin) 305 break; 306 } 307 308 if (i >= sc->gpio_npins) 309 return (EINVAL); 310 311 res = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0; 312 if (res) 313 GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin)); 314 else 315 GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin)); 316 317 return (0); 318} 319 320static int 321ar71xx_gpio_filter(void *arg) 322{ 323 324 /* TODO: something useful */ 325 return (FILTER_STRAY); 326} 327 328 329 330static void 331ar71xx_gpio_intr(void *arg) 332{ 333 struct ar71xx_gpio_softc *sc = arg; 334 GPIO_LOCK(sc); 335 /* TODO: something useful */ 336 GPIO_UNLOCK(sc); 337} 338 339static int 340ar71xx_gpio_probe(device_t dev) 341{ 342 343 device_set_desc(dev, "Atheros AR71XX GPIO driver"); 344 return (0); 345} 346 347static int 348ar71xx_gpio_attach(device_t dev) 349{ 350 struct ar71xx_gpio_softc *sc = device_get_softc(dev); 351 int error = 0; 352 int i, j, maxpin; 353 int mask, pinon; 354 int old = 0; 355 356 KASSERT((device_get_unit(dev) == 0), 357 ("ar71xx_gpio: Only one gpio module supported")); 358 359 mtx_init(&sc->gpio_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 360 361 /* Map control/status registers. */ 362 sc->gpio_mem_rid = 0; 363 sc->gpio_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 364 &sc->gpio_mem_rid, RF_ACTIVE); 365 366 if (sc->gpio_mem_res == NULL) { 367 device_printf(dev, "couldn't map memory\n"); 368 error = ENXIO; 369 ar71xx_gpio_detach(dev); 370 return(error); 371 } 372 373 if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 374 &sc->gpio_irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) { 375 device_printf(dev, "unable to allocate IRQ resource\n"); 376 return (ENXIO); 377 } 378 379 if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC, 380 ar71xx_gpio_filter, ar71xx_gpio_intr, sc, &sc->gpio_ih))) { 381 device_printf(dev, 382 "WARNING: unable to register interrupt handler\n"); 383 return (ENXIO); 384 } 385 386 sc->dev = dev; 387 388 /* Enable function bits that are required */ 389 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 390 "function_set", &mask) == 0) { 391 device_printf(dev, "function_set: 0x%x\n", mask); 392 ar71xx_gpio_function_enable(sc, mask); 393 old = 1; 394 } 395 /* Disable function bits that are required */ 396 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 397 "function_clear", &mask) == 0) { 398 device_printf(dev, "function_clear: 0x%x\n", mask); 399 ar71xx_gpio_function_disable(sc, mask); 400 old = 1; 401 } 402 /* Handle previous behaviour */ 403 if (old == 0) { 404 ar71xx_gpio_function_enable(sc, GPIO_FUNC_SPI_CS1_EN); 405 ar71xx_gpio_function_enable(sc, GPIO_FUNC_SPI_CS2_EN); 406 } 407 408 /* Configure all pins as input */ 409 /* disable interrupts for all pins */ 410 GPIO_WRITE(sc, AR71XX_GPIO_INT_MASK, 0); 411 412 /* Initialise all pins specified in the mask, up to the pin count */ 413 (void) ar71xx_gpio_pin_max(dev, &maxpin); 414 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 415 "pinmask", &mask) != 0) 416 mask = 0; 417 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 418 "pinon", &pinon) != 0) 419 pinon = 0; 420 device_printf(dev, "gpio pinmask=0x%x\n", mask); 421 for (i = 0, j = 0; j <= maxpin; j++) { 422 if ((mask & (1 << j)) == 0) 423 continue; 424 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, 425 "pin %d", j); 426 sc->gpio_pins[i].gp_pin = j; 427 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS; 428 sc->gpio_pins[i].gp_flags = 0; 429 ar71xx_gpio_pin_configure(sc, &sc->gpio_pins[i], DEFAULT_CAPS); 430 i++; 431 } 432 sc->gpio_npins = i; 433 for (i = 0; i < sc->gpio_npins; i++) { 434 j = sc->gpio_pins[i].gp_pin; 435 if ((pinon & (1 << j)) != 0) 436 ar71xx_gpio_pin_set(dev, j, 1); 437 } 438 device_add_child(dev, "gpioc", device_get_unit(dev)); 439 device_add_child(dev, "gpiobus", device_get_unit(dev)); 440 return (bus_generic_attach(dev)); 441} 442 443static int 444ar71xx_gpio_detach(device_t dev) 445{ 446 struct ar71xx_gpio_softc *sc = device_get_softc(dev); 447 448 KASSERT(mtx_initialized(&sc->gpio_mtx), ("gpio mutex not initialized")); 449 450 ar71xx_gpio_function_disable(sc, GPIO_FUNC_SPI_CS1_EN); 451 ar71xx_gpio_function_disable(sc, GPIO_FUNC_SPI_CS2_EN); 452 bus_generic_detach(dev); 453 454 if (sc->gpio_mem_res) 455 bus_release_resource(dev, SYS_RES_MEMORY, sc->gpio_mem_rid, 456 sc->gpio_mem_res); 457 458 mtx_destroy(&sc->gpio_mtx); 459 460 return(0); 461} 462 463static device_method_t ar71xx_gpio_methods[] = { 464 DEVMETHOD(device_probe, ar71xx_gpio_probe), 465 DEVMETHOD(device_attach, ar71xx_gpio_attach), 466 DEVMETHOD(device_detach, ar71xx_gpio_detach), 467 468 /* GPIO protocol */ 469 DEVMETHOD(gpio_pin_max, ar71xx_gpio_pin_max), 470 DEVMETHOD(gpio_pin_getname, ar71xx_gpio_pin_getname), 471 DEVMETHOD(gpio_pin_getflags, ar71xx_gpio_pin_getflags), 472 DEVMETHOD(gpio_pin_getcaps, ar71xx_gpio_pin_getcaps), 473 DEVMETHOD(gpio_pin_setflags, ar71xx_gpio_pin_setflags), 474 DEVMETHOD(gpio_pin_get, ar71xx_gpio_pin_get), 475 DEVMETHOD(gpio_pin_set, ar71xx_gpio_pin_set), 476 DEVMETHOD(gpio_pin_toggle, ar71xx_gpio_pin_toggle), 477 {0, 0}, 478}; 479 480static driver_t ar71xx_gpio_driver = { 481 "gpio", 482 ar71xx_gpio_methods, 483 sizeof(struct ar71xx_gpio_softc), 484}; 485static devclass_t ar71xx_gpio_devclass; 486 487DRIVER_MODULE(ar71xx_gpio, apb, ar71xx_gpio_driver, ar71xx_gpio_devclass, 0, 0); 488