1187499Simp/* $NetBSD: aureg.h,v 1.18 2006/10/02 06:44:00 gdamore Exp $ */ 2187499Simp 3187499Simp/* 4187499Simp * Copyright 2002 Wasabi Systems, Inc. 5187499Simp * All rights reserved. 6187499Simp * 7187499Simp * Written by Simon Burge for Wasabi Systems, Inc. 8187499Simp * 9187499Simp * Redistribution and use in source and binary forms, with or without 10187499Simp * modification, are permitted provided that the following conditions 11187499Simp * are met: 12187499Simp * 1. Redistributions of source code must retain the above copyright 13187499Simp * notice, this list of conditions and the following disclaimer. 14187499Simp * 2. Redistributions in binary form must reproduce the above copyright 15187499Simp * notice, this list of conditions and the following disclaimer in the 16187499Simp * documentation and/or other materials provided with the distribution. 17187499Simp * 3. All advertising materials mentioning features or use of this software 18187499Simp * must display the following acknowledgement: 19187499Simp * This product includes software developed for the NetBSD Project by 20187499Simp * Wasabi Systems, Inc. 21187499Simp * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22187499Simp * or promote products derived from this software without specific prior 23187499Simp * written permission. 24187499Simp * 25187499Simp * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26187499Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27187499Simp * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28187499Simp * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29187499Simp * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30187499Simp * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31187499Simp * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32187499Simp * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33187499Simp * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34187499Simp * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35187499Simp * POSSIBILITY OF SUCH DAMAGE. 36187499Simp */ 37187499Simp 38187499Simp#ifndef _MIPS_ALCHEMY_AUREG_H 39187499Simp#define _MIPS_ALCHEMY_AUREG_H 40187499Simp 41187499Simp/************************************************************************/ 42187499Simp/******************** AC97 Controller registers *********************/ 43187499Simp/************************************************************************/ 44187499Simp#define AC97_BASE 0x10000000 45187499Simp 46187499Simp/************************************************************************/ 47187499Simp/*********************** USB Host registers *************************/ 48187499Simp/************************************************************************/ 49187499Simp#define USBH_BASE 0x10100000 50187499Simp#define AU1550_USBH_BASE 0x14020000 51187499Simp 52187499Simp#define USBH_ENABLE 0x7fffc 53187499Simp#define USBH_SIZE 0x100000 54187499Simp 55187499Simp#define AU1550_USBH_ENABLE 0x7ffc 56187499Simp#define AU1550_USBH_SIZE 0x60000 57187499Simp 58187499Simp/************************************************************************/ 59187499Simp/********************** USB Device registers ************************/ 60187499Simp/************************************************************************/ 61187499Simp#define USBD_BASE 0x10200000 62187499Simp 63187499Simp/************************************************************************/ 64187499Simp/************************* IRDA registers ***************************/ 65187499Simp/************************************************************************/ 66187499Simp#define IRDA_BASE 0x10300000 67187499Simp 68187499Simp/************************************************************************/ 69187499Simp/****************** Interrupt Controller registers ******************/ 70187499Simp/************************************************************************/ 71187499Simp 72187499Simp#define IC0_BASE 0x10400000 73187499Simp#define IC1_BASE 0x11800000 74187499Simp 75187499Simp/* 76187499Simp * The *_READ registers read the current value of the register 77187499Simp * The *_SET registers set to 1 all bits that are written 1 78187499Simp * The *_CLEAR registers clear to zero all bits that are written as 1 79187499Simp */ 80187499Simp#define IC_CONFIG0_READ 0x40 /* See table below */ 81187499Simp#define IC_CONFIG0_SET 0x40 82187499Simp#define IC_CONFIG0_CLEAR 0x44 83187499Simp 84187499Simp#define IC_CONFIG1_READ 0x48 /* See table below */ 85187499Simp#define IC_CONFIG1_SET 0x48 86187499Simp#define IC_CONFIG1_CLEAR 0x4c 87187499Simp 88187499Simp#define IC_CONFIG2_READ 0x50 /* See table below */ 89187499Simp#define IC_CONFIG2_SET 0x50 90187499Simp#define IC_CONFIG2_CLEAR 0x54 91187499Simp 92187499Simp#define IC_REQUEST0_INT 0x54 /* Show active interrupts on request 0 */ 93187499Simp 94187499Simp#define IC_SOURCE_READ 0x58 /* Interrupt source */ 95187499Simp#define IC_SOURCE_SET 0x58 /* 0 - test bit used as source */ 96187499Simp#define IC_SOURCE_CLEAR 0x5c /* 1 - peripheral/GPIO used as source */ 97187499Simp 98187499Simp#define IC_REQUEST1_INT 0x5c /* Show active interrupts on request 1 */ 99187499Simp 100187499Simp#define IC_ASSIGN_REQUEST_READ 0x60 /* Assigns the interrupt to one of the */ 101187499Simp#define IC_ASSIGN_REQUEST_SET 0x60 /* CPU requests (0 - assign to request 1, */ 102187499Simp#define IC_ASSIGN_REQUEST_CLEAR 0x64 /* 1 - assign to request 0) */ 103187499Simp 104187499Simp#define IC_WAKEUP_READ 0x68 /* Controls whether the interrupt can */ 105187499Simp#define IC_WAKEUP_SET 0x68 /* cause a wakeup from IDLE */ 106187499Simp#define IC_WAKEUP_CLEAR 0x6c 107187499Simp 108187499Simp#define IC_MASK_READ 0x70 /* Enables/Disables the interrupt */ 109187499Simp#define IC_MASK_SET 0x70 110187499Simp#define IC_MASK_CLEAR 0x74 111187499Simp 112187499Simp#define IC_RISING_EDGE 0x78 /* Check/clear rising edge */ 113187499Simp 114187499Simp#define IC_FALLING_EDGE 0x7c /* Check/clear falling edge */ 115187499Simp 116187499Simp#define IC_TEST_BIT 0x80 /* single bit source select */ 117187499Simp 118187499Simp/* 119187499Simp * Interrupt Configuration Register Functions 120187499Simp * 121187499Simp * Cfg2[n] Cfg1[n] Cfg0[n] Function 122187499Simp * 0 0 0 Interrupts Disabled 123187499Simp * 0 0 1 Rising Edge Enabled 124187499Simp * 0 1 0 Falling Edge Enabled 125187499Simp * 0 1 1 Rising and Falling Edge Enabled 126187499Simp * 1 0 0 Interrupts Disabled 127187499Simp * 1 0 1 High Level Enabled 128187499Simp * 1 1 0 Low Level Enabled 129187499Simp * 1 1 1 Both Levels and Both Edges Enabled 130187499Simp */ 131187499Simp 132187499Simp/************************************************************************/ 133187499Simp/************* Programable Serial Controller registers **************/ 134187499Simp/************************************************************************/ 135187499Simp 136187499Simp#define PSC0_BASE 0x11A00000 137187499Simp#define PSC1_BASE 0x11B00000 138187499Simp#define PSC2_BASE 0x10A00000 139187499Simp#define PSC3_BASE 0x10B00000 140187499Simp 141187499Simp 142187499Simp/************************************************************************/ 143187499Simp/********************** Ethernet MAC registers **********************/ 144187499Simp/************************************************************************/ 145187499Simp 146187499Simp#define MAC0_BASE 0x10500000 147187499Simp#define MAC1_BASE 0x10510000 148187499Simp#define MACx_SIZE 0x28 149187499Simp 150187499Simp#define AU1500_MAC0_BASE 0x11500000 /* Grr, different on Au1500 */ 151187499Simp#define AU1500_MAC1_BASE 0x11510000 /* Grr, different on Au1500 */ 152187499Simp 153187499Simp#define MAC0_ENABLE 0x10520000 154187499Simp#define MAC1_ENABLE 0x10520004 155187499Simp#define MACENx_SIZE 0x04 156187499Simp 157187499Simp#define AU1500_MAC0_ENABLE 0x11520000 /* Grr, different on Au1500 */ 158187499Simp#define AU1500_MAC1_ENABLE 0x11520004 /* Grr, different on Au1500 */ 159187499Simp 160187499Simp#define MAC0_DMA_BASE 0x14004000 161187499Simp#define MAC1_DMA_BASE 0x14004200 162187499Simp#define MACx_DMA_SIZE 0x140 163187499Simp 164187499Simp/************************************************************************/ 165187499Simp/********************** Static Bus registers ************************/ 166187499Simp/************************************************************************/ 167187499Simp#define STATIC_BUS_BASE 0x14001000 168187499Simp 169187499Simp/************************************************************************/ 170187499Simp/******************** Secure Digital registers **********************/ 171187499Simp/************************************************************************/ 172187499Simp#define SD0_BASE 0x10600000 173187499Simp#define SD1_BASE 0x10680000 174187499Simp 175187499Simp/************************************************************************/ 176187499Simp/************************* I^2S registers ***************************/ 177187499Simp/************************************************************************/ 178187499Simp#define I2S_BASE 0x11000000 179187499Simp 180187499Simp/************************************************************************/ 181187499Simp/************************** UART registers **************************/ 182187499Simp/************************************************************************/ 183187499Simp 184187499Simp#define UART0_BASE 0x11100000 185187499Simp#define UART1_BASE 0x11200000 186187499Simp#define UART2_BASE 0x11300000 187187499Simp#define UART3_BASE 0x11400000 188187499Simp 189187499Simp/************************************************************************/ 190187499Simp/************************* SSI registers ****************************/ 191187499Simp/************************************************************************/ 192187499Simp#define SSI0_BASE 0x11600000 193187499Simp#define SSI1_BASE 0x11680000 194187499Simp 195187499Simp/************************************************************************/ 196187499Simp/************************ GPIO2 registers ***************************/ 197187499Simp/************************************************************************/ 198187499Simp#define GPIO_BASE 0x11900100 199187499Simp 200187499Simp/************************************************************************/ 201187499Simp/************************ GPIO2 registers ***************************/ 202187499Simp/************************************************************************/ 203187499Simp#define GPIO2_BASE 0x11700000 204187499Simp 205187499Simp/************************************************************************/ 206187499Simp/************************* PCI registers ****************************/ 207187499Simp/************************************************************************/ 208187499Simp#define PCI_BASE 0x14005000 209187499Simp#define PCI_HEADER 0x14005100 210187499Simp#define PCI_MEM_BASE 0x400000000ULL 211187499Simp#define PCI_IO_BASE 0x500000000ULL 212187499Simp#define PCI_CONFIG_BASE 0x600000000ULL 213187499Simp 214187499Simp/************************************************************************/ 215187499Simp/*********************** PCMCIA registers ***************************/ 216187499Simp/************************************************************************/ 217187499Simp#define PCMCIA_BASE 0xF00000000ULL 218187499Simp 219187499Simp/************************************************************************/ 220187499Simp/****************** Programmable Counter registers ******************/ 221187499Simp/************************************************************************/ 222187499Simp 223187499Simp#define SYS_BASE 0x11900000 224187499Simp 225187499Simp#define PC_BASE SYS_BASE 226187499Simp 227187499Simp#define PC_TRIM0 0x00 /* PC0 Divide (16 bits) */ 228187499Simp#define PC_COUNTER_WRITE0 0x04 /* set PC0 */ 229187499Simp#define PC_MATCH0_0 0x08 /* match counter & interrupt */ 230187499Simp#define PC_MATCH1_0 0x0c /* match counter & interrupt */ 231187499Simp#define PC_MATCH2_0 0x10 /* match counter & interrupt */ 232187499Simp#define PC_COUNTER_CONTROL 0x14 /* Programmable Counter Control */ 233187499Simp#define CC_E1S 0x00800000 /* Enable PC1 write status */ 234187499Simp#define CC_T1S 0x00100000 /* Trim PC1 write status */ 235187499Simp#define CC_M21 0x00080000 /* Match 2 of PC1 write status */ 236187499Simp#define CC_M11 0x00040000 /* Match 1 of PC1 write status */ 237187499Simp#define CC_M01 0x00020000 /* Match 0 of PC1 write status */ 238187499Simp#define CC_C1S 0x00010000 /* PC1 write status */ 239187499Simp#define CC_BP 0x00004000 /* Bypass OSC (use GPIO1) */ 240187499Simp#define CC_EN1 0x00002000 /* Enable PC1 */ 241187499Simp#define CC_BT1 0x00001000 /* Bypass Trim on PC1 */ 242187499Simp#define CC_EN0 0x00000800 /* Enable PC0 */ 243187499Simp#define CC_BT0 0x00000400 /* Bypass Trim on PC0 */ 244187499Simp#define CC_EO 0x00000100 /* Enable Oscillator */ 245187499Simp#define CC_E0S 0x00000080 /* Enable PC0 write status */ 246187499Simp#define CC_32S 0x00000020 /* 32.768kHz OSC status */ 247187499Simp#define CC_T0S 0x00000010 /* Trim PC0 write status */ 248187499Simp#define CC_M20 0x00000008 /* Match 2 of PC0 write status */ 249187499Simp#define CC_M10 0x00000004 /* Match 1 of PC0 write status */ 250187499Simp#define CC_M00 0x00000002 /* Match 0 of PC0 write status */ 251187499Simp#define CC_C0S 0x00000001 /* PC0 write status */ 252187499Simp#define PC_COUNTER_READ_0 0x40 /* get PC0 */ 253187499Simp#define PC_TRIM1 0x44 /* PC1 Divide (16 bits) */ 254187499Simp#define PC_COUNTER_WRITE1 0x48 /* set PC1 */ 255187499Simp#define PC_MATCH0_1 0x4c /* match counter & interrupt */ 256187499Simp#define PC_MATCH1_1 0x50 /* match counter & interrupt */ 257187499Simp#define PC_MATCH2_1 0x54 /* match counter & interrupt */ 258187499Simp#define PC_COUNTER_READ_1 0x58 /* get PC1 */ 259187499Simp 260187499Simp#define PC_SIZE 0x5c /* size of register set */ 261187499Simp#define PC_RATE 32768 /* counter rate is 32.768kHz */ 262187499Simp 263187499Simp/************************************************************************/ 264187499Simp/******************* Frequency Generator Registers ******************/ 265187499Simp/************************************************************************/ 266187499Simp 267187499Simp#define SYS_FREQCTRL0 (SYS_BASE + 0x20) 268187499Simp#define SFC_FRDIV2(f) (f<<22) /* 29:22. Freq Divider 2 */ 269187499Simp#define SFC_FE2 (1<<21) /* Freq generator output enable 2 */ 270187499Simp#define SFC_FS2 (1<<20) /* Freq generator source 2 */ 271187499Simp#define SFC_FRDIV1(f) (f<<12) /* 19:12. Freq Divider 1 */ 272187499Simp#define SFC_FE1 (1<<11) /* Freq generator output enable 1 */ 273187499Simp#define SFC_FS1 (1<<10) /* Freq generator source 1 */ 274187499Simp#define SFC_FRDIV0(f) (f<<2) /* 9:2. Freq Divider 0 */ 275187499Simp#define SFC_FE0 2 /* Freq generator output enable 0 */ 276187499Simp#define SFC_FS0 1 /* Freq generator source 0 */ 277187499Simp 278187499Simp#define SYS_FREQCTRL1 (SYS_BASE + 0x24) 279187499Simp#define SFC_FRDIV5(f) (f<<22) /* 29:22. Freq Divider 5 */ 280187499Simp#define SFC_FE5 (1<<21) /* Freq generator output enable 5 */ 281187499Simp#define SFC_FS5 (1<<20) /* Freq generator source 5 */ 282187499Simp#define SFC_FRDIV4(f) (f<<12) /* 19:12. Freq Divider 4 */ 283187499Simp#define SFC_FE4 (1<<11) /* Freq generator output enable 4 */ 284187499Simp#define SFC_FS4 (1<<10) /* Freq generator source 4 */ 285187499Simp#define SFC_FRDIV3(f) (f<<2) /* 9:2. Freq Divider 3 */ 286187499Simp#define SFC_FE3 2 /* Freq generator output enable 3 */ 287187499Simp#define SFC_FS3 1 /* Freq generator source 3 */ 288187499Simp 289187499Simp/************************************************************************/ 290187499Simp/****************** Clock Source Control Registers ******************/ 291187499Simp/************************************************************************/ 292187499Simp 293187499Simp#define SYS_CLKSRC (SYS_BASE + 0x28) 294187499Simp#define SCS_ME1(n) (n<<27) /* EXTCLK1 Clock Mux input select */ 295187499Simp#define SCS_ME0(n) (n<<22) /* EXTCLK0 Clock Mux input select */ 296187499Simp#define SCS_MPC(n) (n<<17) /* PCI clock mux input select */ 297187499Simp#define SCS_MUH(n) (n<<12) /* USB Host clock mux input select */ 298187499Simp#define SCS_MUD(n) (n<<7) /* USB Device clock mux input select */ 299187499Simp#define SCS_MEx_AUX 0x1 /* Aux clock */ 300187499Simp#define SCS_MEx_FREQ0 0x2 /* FREQ0 */ 301187499Simp#define SCS_MEx_FREQ1 0x3 /* FREQ1 */ 302187499Simp#define SCS_MEx_FREQ2 0x4 /* FREQ2 */ 303187499Simp#define SCS_MEx_FREQ3 0x5 /* FREQ3 */ 304187499Simp#define SCS_MEx_FREQ4 0x6 /* FREQ4 */ 305187499Simp#define SCS_MEx_FREQ5 0x7 /* FREQ5 */ 306187499Simp#define SCS_DE1 (1<<26) /* EXTCLK1 clock divider select */ 307187499Simp#define SCS_CE1 (1<<25) /* EXTCLK1 clock select */ 308187499Simp#define SCS_DE0 (1<<21) /* EXTCLK0 clock divider select */ 309187499Simp#define SCS_CE0 (1<<20) /* EXTCLK0 clock select */ 310187499Simp#define SCS_DPC (1<<16) /* PCI clock divider select */ 311187499Simp#define SCS_CPC (1<<15) /* PCI clock select */ 312187499Simp#define SCS_DUH (1<<11) /* USB Host clock divider select */ 313187499Simp#define SCS_CUH (1<<10) /* USB Host clock select */ 314187499Simp#define SCS_DUD (1<<6) /* USB Device clock divider select */ 315187499Simp#define SCS_CUD (1<<5) /* USB Device clock select */ 316187499Simp/* 317187499Simp * Au1550 bits, needed for PSCs. Note that some bits collide with 318187499Simp * earlier parts. On Au1550, USB clocks (both device and host) are 319187499Simp * shared with PSC2, and must be configured for 48MHz. DBAU1550 YAMON 320187499Simp * does this by default. Also, EXTCLK0 is shared with PSC3. DBAU1550 321187499Simp * YAMON does not configure any clocks besides PSC2. 322187499Simp */ 323187499Simp#define SCS_MP3(n) (n<<22) /* psc3_intclock mux */ 324187499Simp#define SCS_DP3 (1<<21) /* psc3_intclock divider */ 325187499Simp#define SCS_CP3 (1<<20) /* psc3_intclock select */ 326187499Simp#define SCS_MP1(n) (n<<12) /* psc1_intclock mux */ 327187499Simp#define SCS_DP1 (1<<11) /* psc1_intclock divider */ 328187499Simp#define SCS_CP1 (1<<10) /* psc1_intclock select */ 329187499Simp#define SCS_MP0(n) (n<<7) /* psc0_intclock mux */ 330187499Simp#define SCS_DP0 (1<<6) /* psc0_intclock divider */ 331187499Simp#define SCS_CP0 (1<<5) /* psc0_intclock seelct */ 332187499Simp#define SCS_MP2(n) (n<<2) /* psc2_intclock mux */ 333187499Simp#define SCS_DP2 (1<<1) /* psc2_intclock divider */ 334187499Simp#define SCS_CP2 (1<<0) /* psc2_intclock select */ 335187499Simp 336187499Simp/************************************************************************/ 337187499Simp/*************************** PIN Function *****************************/ 338187499Simp/************************************************************************/ 339187499Simp 340187499Simp#define SYS_PINFUNC (SYS_BASE + 0x2c) 341187499Simp#define SPF_PSC3_MASK (7<<20) 342187499Simp#define SPF_PSC3_AC97 (0<<17) /* select AC97/SPI */ 343187499Simp#define SPF_PSC3_I2S (1<<17) /* select I2S */ 344187499Simp#define SPF_PSC3_SMBUS (3<<17) /* select SMbus */ 345187499Simp#define SPF_PSC3_GPIO (7<<17) /* select gpio215:211 */ 346187499Simp#define SPF_PSC2_MASK (7<<17) 347187499Simp#define SPF_PSC2_AC97 (0<<17) /* select AC97/SPI */ 348187499Simp#define SPF_PSC2_I2S (1<<17) /* select I2S */ 349187499Simp#define SPF_PSC2_SMBUS (3<<17) /* select SMbus */ 350187499Simp#define SPF_PSC2_GPIO (7<<17) /* select gpio210:206*/ 351187499Simp#define SPF_CS (1<<16) /* extclk0 or 32kHz osc */ 352187499Simp#define SPF_USB (1<<15) /* host or device usb otg */ 353187499Simp#define SPF_U3T (1<<14) /* uart3 tx or gpio23 */ 354187499Simp#define SPF_U1R (1<<13) /* uart1 rx or gpio22 */ 355187499Simp#define SPF_U1T (1<<12) /* uart1 tx or gpio21 */ 356187499Simp#define SPF_EX1 (1<<10) /* gpio3 or extclk1 */ 357187499Simp#define SPF_EX0 (1<<9) /* gpio2 or extclk0/32kHz osc*/ 358187499Simp#define SPF_U3 (1<<7) /* gpio14:9 or uart3 */ 359187499Simp#define SPF_MBSa (1<<5) /* must be set */ 360187499Simp#define SPF_NI2 (1<<4) /* enet1 or gpio28:24 */ 361187499Simp#define SPF_U0 (1<<3) /* uart0 or gpio20 */ 362187499Simp#define SPF_MBSb (1<<2) /* must be set */ 363187499Simp#define SPF_S1 (1<<1) /* gpio17 or psc1_sync1 */ 364187499Simp#define SPF_S0 (1<<0) /* gpio16 or psc0_sync1 */ 365187499Simp 366187499Simp/************************************************************************/ 367187499Simp/*************************** PLL Control *****************************/ 368187499Simp/************************************************************************/ 369187499Simp 370187499Simp#define SYS_CPUPLL (SYS_BASE + 0x60) 371187499Simp#define SYS_AUXPLL (SYS_BASE + 0x64) 372187499Simp 373187499Simp#endif /* _MIPS_ALCHEMY_AUREG_H */ 374