__udivsi3.S revision 66633
1179404Sobrien.file "__udivsi3.s" 2218822Sdim 3179404Sobrien// $FreeBSD: head/sys/libkern/ia64/__udivsi3.S 66633 2000-10-04 17:53:03Z dfr $ 4179404Sobrien// 5179404Sobrien// Copyright (c) 2000, Intel Corporation 6179404Sobrien// All rights reserved. 7179404Sobrien// 8179404Sobrien// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache, 9179404Sobrien// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab, 10179404Sobrien// Intel Corporation. 11179404Sobrien// 12179404Sobrien// WARRANTY DISCLAIMER 13179404Sobrien// 14179404Sobrien// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 15179404Sobrien// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 16179404Sobrien// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17179404Sobrien// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS 18218822Sdim// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19179404Sobrien// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20218822Sdim// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21179404Sobrien// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 22179404Sobrien// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING 23179404Sobrien// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24179404Sobrien// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25179404Sobrien// 26179404Sobrien// Intel Corporation is the author of this code, and requests that all 27179404Sobrien// problem reports or change requests be submitted to it directly at 28179404Sobrien// http://developer.intel.com/opensource. 29179404Sobrien// 30179404Sobrien 31.section .text 32 33// 32-bit unsigned integer divide 34 35.proc __udivsi3# 36.align 32 37.global __udivsi3# 38.align 32 39 40__udivsi3: 41 42{ .mii 43 alloc r31=ar.pfs,2,0,0,0 44 nop.i 0 45 nop.i 0;; 46} { .mii 47 nop.m 0 48 49 // 32-BIT UNSIGNED INTEGER DIVIDE BEGINS HERE 50 51 // general register used: 52 // r32 - 32-bit unsigned integer dividend 53 // r33 - 32-bit unsigned integer divisor 54 // r8 - 32-bit unsigned integer result 55 // r2 - scratch register 56 // floating-point registers used: f6, f7, f8, f9 57 // predicate registers used: p6 58 59 zxt4 r32=r32 60 zxt4 r33=r33;; 61} { .mmb 62 setf.sig f6=r32 63 setf.sig f7=r33 64 nop.b 0;; 65} { .mfi 66 nop.m 0 67 fcvt.xf f6=f6 68 nop.i 0 69} { .mfi 70 nop.m 0 71 fcvt.xf f7=f7 72 mov r2 = 0x0ffdd;; 73} { .mfi 74 setf.exp f9 = r2 75 // (1) y0 76 frcpa.s1 f8,p6=f6,f7 77 nop.i 0;; 78} { .mfi 79 nop.m 0 80 // (2) q0 = a * y0 81 (p6) fma.s1 f6=f6,f8,f0 82 nop.i 0 83} { .mfi 84 nop.m 0 85 // (3) e0 = 1 - b * y0 86 (p6) fnma.s1 f7=f7,f8,f1 87 nop.i 0;; 88} { .mfi 89 nop.m 0 90 // (4) q1 = q0 + e0 * q0 91 (p6) fma.s1 f6=f7,f6,f6 92 nop.i 0 93} { .mfi 94 nop.m 0 95 // (5) e1 = e0 * e0 + 2^-34 96 (p6) fma.s1 f7=f7,f7,f9 97 nop.i 0;; 98} { .mfi 99 nop.m 0 100 // (6) q2 = q1 + e1 * q1 101 (p6) fma.s1 f8=f7,f6,f6 102 nop.i 0;; 103} { .mfi 104 nop.m 0 105 // (7) q = trunc(q2) 106 fcvt.fxu.trunc.s1 f8=f8 107 nop.i 0;; 108} { .mmi 109 // quotient will be in the least significant 32 bits of r8 (if b != 0) 110 getf.sig r8=f8 111 nop.m 0 112 nop.i 0;; 113} 114 115 // 32-BIT UNSIGNED INTEGER DIVIDE ENDS HERE 116 117{ .mmb 118 nop.m 0 119 nop.m 0 120 br.ret.sptk b0;; 121} 122 123.endp __udivsi3 124